Page 1
Ordering number : ENN*6690
LC86P6548
8-Bit Single Chip Microcontroller
with One-Time Programmable PROM
Preliminary
Overview
The LC86P6548 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC866500 series.
This microcontroller has the function and the pin description of the LC866500 series mask ROM version, and 48K-byte
PROM.
Features
(1) Option switching by PROM data
The option function of the LC866500 series can be specified by the PROM data.
LC86P6548 can be checked the function of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity : 49408 bytes
(3) Internal RAM capacity : 1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P6548.
Mask ROM version PROM capacity RAM capacity
LC866548 49152 bytes 1152 bytes
LC866540 40960 bytes 1152 bytes
LC866532 32768 bytes 1152 bytes
LC866528 28672 bytes 896 bytes
LC866524 24576 bytes 896 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package
stamping and the screening. Contact our representative for further information.
CMOS IC
Ver.1.03
80696
91400 RM (IM) SK No.6690-1/22
Page 2
LC86P6548
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 1.0µs to 366µs
(6) Operating temperature : -30°C to +70°C
(7) The pin and the package compatible with the LC866500 series mask ROM devices
(8) Applicable mask ROM version : LC866548/LC866540//LC866532/LC866528/LC86652 4
Notice for use
LC86P6548 is provided for the first release and small shipping of the LC866500 series.
At using, take notice of the followings.
(1) A point of difference LC86P6548 and LC866500 series
Item LC86P6548 LC866548/40/32/28/24
Operation after reset
releasing
Pull-down resistor of
the following pins
•S0/T0 – S6/T6
•S7/T7 – S15/T15
•S16 – S31
•S32 – S47
•S48 – S51
Power dissipa tion Refer to ‘electrical characteristics’ on the semiconductor news.
The option is specified until 3ms after
going to a ‘H’ level to the reset terminal
by dgrees. The program is executed
from 00H of the program counter.
Pull-down resistor
provided/not provided
Not provided
Provided (fixed)
Provided (fixed)
Not provided
Not provided
LC86P6548 uses 25 6 bytes that is add ressed on FF00 H to FFFFH in the pro gram memory as the opti on configur ation data
area. This option configuration cannot execute all options which LC866500 series have. Next tables show the options
that correspond and not correspond to LC86P6548.
• A kind of the option corresponding of the LC86P6548
A kind of option Pins, Circuits Contents of the option
Input/output form of
Input/output ports
Port 0
Port 1
*1
Port 3
*1
*1) Specified in a bit
*2) Specified in nibble unit. T he port of N-channel open drain output does not have the Pull-up MOS Tr..
The program is executed from 00H of the
program counter immediately after going to
a ‘H’ level to reset terminal.
Pull-down resistor
provided/not provided
Specified by the opt ion
Provided (fixed)
Specified by the opt ion
Specified by the opt ion
Not provided
1. N-channel open drain output
2. CMOS output *1
3. Pull-up MOS Tr. proveded
4. Pull-up MOS Tr. not provided *2
1. Input : Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. Input : No Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
No.6690-2/22
Page 3
LC86P6548
• A kind of the option not corresponding of the LC86P6548
A kind of option Pins, Circuits LC86P6548 LC866548/40/32/28/24
Pull-down resistor of
the high voltage
Withstand output terminals
•S0/T0 to S6/T6
•S16 to S31
•S32 to S47
Not provided
Provided (fixed)
Not provided
Specified by the opt ion
Specified by the opt ion
Specified by the opt ion
(2) Option
The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE”.
(3) ROM space
LC86P6548 and LC86 65 00 seri es use 25 6 bytes that is ad dres sed on 0 FF0 0H t o 0F FFFH in the pro gra m memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
The option
specified area
256 bytes
Program area
48K bytes
The option
specified area
Program area
40K bytes
LC866540 LC866548 LC866532 LC866528 LC866524
The option
specified area
Program area
32K bytes
The option
specified area
Program area
28K bytes
The option
specified area
Program area
24K bytes
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
No.6690-3/22
Page 4
LC86P6548
How to use
(1) Specification of option
Programming data for PROM of the LC86P6548 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P6548.
(2) How to program for the PROM
LC86P6548 can be programmed by the EPROM programmer with attachment ; W86EP6548Q.
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL 1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to
“0 to 0FFFFH” and a jumper (D ASE C) must be set to ‘OFF’ at programming
(3) How to use the data security function
“Data security” is the disabled function to read the data of the PROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
1 pin mark
of LSI
.
1 pin
Not data security
W86EP6548Q
No.6690-4/22
Page 5
Pin Assignment
Z
N
N
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
Package Dimension
(unit : mm)
3151
LC86P6548
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
VDD4
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
8079787776757473727170696867666564636261605958575655545352
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9
P30
P31
P32
P33
P16/BUZ
P17/PWM0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P34
P35
P36
P37
RES
P70/INT0
CF1
CF2
VSS1
XT1/P74
XT2/P75
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
S24/PD0
25
P86/AN6
S23/PC7
26
P87/AN7
S22/PC6
27
P71/INT1
S21/PC5
28
P72/INT2/T0I
S20/PC4
29
P72/INT3/T0I
VP
51
50
S19/PC3
49
S18/PC2
48
S17/PC1
47
S16/PC0
46
VDD3
45
S15/T15
44
S14/T14
43
S13/T13
42
S12/T12
41
S11/T11
40
S10/T10
39
S9/T9
38
S8/T8
37
S7/T7
36
S6/T6
35
S5/T5
34
S4/T4
33
S3/T3
32
S2/T2
31
S1/T1
30
S0/T0
SANYO : QIP-100E
No.6690-5/22
Page 6
System Bl ock Diagram
Base Timer
SIO0
SIO1
Timer 0
Timer 1
ADC
INT0-3
Noise Filter
SIO Automatic
transmission
RAM
128 bytes
VFD
Controller
High voltage Output
Interrupt Control
Standby Control
CF
RC
X’tal
Clock
Generator
LC86P6548
Bus Interface
Port 1
Port 3
Port 7
Port 8
IR PLA
A15-A0
PC
D7-D0
TA
CE
OE
DASEC
PROM
Control
PROM(48KB)
ACC
B Register
C Register
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog Timer
No.6690-6/22
Page 7
LC86P6548
LC86P6548 Pin Description
Pin name I/O Function description Option PROM mode
VSS1,2 - Power pin (-) *4 - VDD1,2,3,4 - Power pin (+) *4 - VP - Power pin (+) for the VFD output pull-down resist - PORT0
P00 to P07
PORT1
P10 to P17
PORT3
P30 to P37
PORT7
P70 to P73
to P75
P74
I/O •8-bit input/output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
•15V withstand at N-channel open drain
output
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
I/O •8-bit input/output port
•Input/output in bit unit
•15V withstand at N-channel open drain
output
•4-bit input/output port
•Input/output in bit unit
•2-bit input port
•Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
I/O
I
output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event
input
P74
: 32.768kHz crystal os cillation terminal XT1
P75 : 32.768kHz crystal oscillation terminal XT2
•Interrupt recei ved forms, the vector addresses
high
level
low
level
rising falling rising
&
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
vector
Continue.
•Pull-up resistor :
Provided/Not provided
(each nibble)
•Output form :
CMOS/N-channel open
drain (each bit)
•Output form :
CMOS/N-channel open
drain (each bit)
•Output form :
CMOS/N-channel open
drain (each bit)
-
Data line
D0 to D7
-
PROM control
signals
DASEC (*1)
OE
CE
‚bE
(*2)
(*3)
No.6690-7/22
Page 8
LC86P6548
Pin name I/O Function description Option PROM mode
PORT8
P80 to 83
P84 to 87
S0/T0 to
S6/T6 *6
S7/T7 to
S15/T15
*7
S16 to S31
*8
S32 to S47
*9
I
I/O
O Output for VFD display controller
O •Output for VFD display controller
I/O •Output for VFD display controller Segment
I/O •Output for VFD display controller Segment
•4-bit input port
•Input/output in bit unit
•4-bit input port
•Other function
AD input port (8 port pins)
segment/timing in common
segment/timing with internal pull-down
resistor in common
•Internal pull-down resistor output
output
•Other function
S16 : High voltage input port PC0
S17 : High voltage input port PC1
S18 : High voltage input port PC2
S19 : High voltage input port PC3
S20 : High voltage input port PC4
S21 : High voltage input port PC5
S22 : High voltage input port PC6
S23 : High voltage input port PC7
S24 : High voltage input port PD0
S25 : High voltage input port PD1
S26 : High voltage input port PD2
S27 : High voltage input port PD3
S28 : High voltage input port PD4
S29 : High voltage input port PD5
S30 : High voltage input port PD6
S31 : High voltage input port PD7
•Other function
S32 : High voltage input port PE0
S33 : High voltage input port PE1
S34 : High voltage input port PE2
S35 : High voltage input port PE3
S36 : High voltage input port PE4
S37 : High voltage input port PE5
S38 : High voltage input port PE6
S39 : High voltage input port PE7
S40 : High voltage I/O port PF0
S41 : High voltage I/O port PF1
S42 : High voltage I/O port PF2
S43 : High voltage I/O port PF3
S44 : High voltage I/O port PF4
S45 : High voltage I/O port PF5
S46 : High voltage I/O port PF6
S47 : High voltage I/O port PF7
- -
- -
- TA (*5)
- •Address input
A15 to A0
- -
Continue.
No.6690-8/22
Page 9
LC86P6548
Pin name I/O Function description Option PROM mode
S48 to S51
*9
RES
XT1/
XT2/P75 O •Output pin for 32.768kHz crystal oscillation
CF1 I Input pin for the ceramic resonator oscillation - CF2 O Output pin for the ceramic resonator oscillation - -
All of port options (except pull-up resistor of port 0) can be specified in bit unit.
♦
I/O •Output for VFD display controller Segment
•Other function
S48 : High voltage I/O port PG0
S49 : High voltage I/O port PG1
S50 : High voltage I/O port PG2
S51 : High voltage I/O port PG3
P74
I Reset pin - I •Input pin for 32.768kHz crystal oscillation
•Other function
XT1 : Input port
In case of non use, connect to VDD1.
•Other function
XT2 : Input port P75
In case of non us e, connect to VDD1 at using
as port or unconnect at using as oscillation.
P74
- -
- -
- -
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 Connect like the following figure to reduce noise into a VDD1 terminal.
Shorted the VSS1 terminal to the VSS2 terminal a nd to make the back- u p time long.
*5 TA ! PROM control signal input
*6 S0/T0 to S6/T6 : not provided the pull -down re sistor
*7 S7/T7 to S15/T15 : provided the pull-down resistor (fixed)
*8 S16 to S31 : provided the pull-down resistor (fixed)
*9 S32 to S51 : not provided the pull-down resistor
Power
Supply
Back-up capacitor
LSI
VDD1
VDD2
VDD3
VFD
powers
VDD4
VSS2 VSS1
No.6690-9/22
Page 10
LC86P6548
V
1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C
Parameter Symbol Pins Conditions
Supply voltage
Input voltage
VDDMAX
VDD1, VDD2
VDD3, VDD4
VI(1) •Ports 74,75
VDD1=VDD2
=VDD3=VDD4
-0.3 VDD+
Ratings
[V]
DD
min. typ. max.
-0.3 +7.0
•Ports 80,81,82,83
•Port 8
RES
•
VI(2) VP VDD-45 VDD+
Output voltage VO(1) S0/T0 to S15/T15 VDD-45 VDD+
Input/Output
voltage
VIO(1) •Port 1
•Ports 70,71,72,73
-0.3 VDD+
•Ports 84,85,86,87
•Ports 0, 3 at CMOS
output option
VIO(2) Ports 0, 3 at N-ch open
-0.3 15
drain output option
VIO(3) S16 to S51 VDD-45 VDD+
High
level
output
current
Low
level
output
current
Peak
output
current
Total
output
current
output
current
Total
output
current
IOPH(1) Ports 0, 1, 3 •CMOS output
•At each pins
IOPH(2) S0/T0 to S15/T15 At each pins -30
IOPH(3) S16 to S51 At each pins -15
IOAH(1) Port 0 The total of all pins -30
Σ
IOAH(2) Ports 1, 3 The total of all pins -30
Σ
IOAH(3) S0/T0 to S15/T15 The total of all pins -55
Σ
IOAH(4) S16 to S27 The total of all pins -60
Σ
IOAH(5) S28to S39 The total of all pins -60
Σ
IOAH(6) S40 to S51 The total of all pins -60
Σ
IOPL(1) Ports 0,1,3 At each pins 20 Peak
IOPL(2) •Ports 70,71,72,73
At each pins 15
•Ports 84,85,86,87
IOAL(1) Port 0 The total of all pins 60
Σ
IOAL(2) Po rts 1,3,70 The total of all pins 50
Σ
IOAL(3) •Ports 71,72,73
Σ
The total of all pins 20
-10
•Ports 84,85,86,87
Maximum
Pdmax QFP100E Ta=-30 to+70°C 500
power
dissipation
Operating
Topr -30 70
temperature
range
Storage
Tstg -55 125
temperature
range
0.3
0.3
0.3
0.3
0.3
unit
V
mA
mW
C
°
No.6690-10/22
Page 11
LC86P6548
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Operating
Supply voltage
VDD(1) VDD1=VDD2
=VVDD3=VDD4
0.98µs ≤ t
CYC
t
CYC
≤ 400µs
Hold voltage VHD VDD1=VDD2 RAMs and the
registers hold
voltage at HOLD
mode.
Pull-down
VP VP 4.5 to 6.0 -35 VDD
Voltage
Input high
VIH(1) Port 0 at CMOS output Output disable 4.5 to 6.0
voltage
VIH(2) Port 0 at N-ch open drain
Output di sable 4.5 to 6.0 0.75VDD 13.5
output
VIH(3) •Port 1
•Ports 72,73
Output di sable 4.5 to 6.0 0.75VDD VDD
•Port 3 at CMOS
output
VIH(4) •Port 3 at N-ch open
drain output
VIH(5) •Port 70
Output disable
Tr. OFF
Output di sable 4.5 to 6.0 0.75VDD VDD
Port input/interrupt
•Port 71
•
RES
VIH(6) Port 70
Output disable 4.5 to 6.0 0.9VDD VDD
Watchdog timer
VIH(7) •Port 8
74
•Ports
,75
Output di sable 4.5 to 6.0 0.75VDD VDD
VIH(8) S16 to S51 Output P-channel
Tr. OFF
Input low
voltage
VIL(1) Port 0 at CMOS
output option
VIL(2) Port 0 at N-ch open
Output disable 4.5 to 6.0 VSS 0.2VDD
Output di sable 4.5 to 6.0 VSS 0.25VDD
drain output
VIL(3) •Ports 1,3
Output di sable 4.5 to 6.0 VSS 0.25VDD
•Ports 72,73
VIL(4) •Port 70
Output di sable 4.5 to 6.0 VSS 0.25VDD
Port input/interrupt
•Port 71
•
RES
VIL(5) Port 70
Output disable 4.5 to 6.0 VSS 0. 8VDD
Watchdog timer
VIL(6) •Port 8
74
•Ports
,75
Output di sable 4.5 to 6.0 VSS 0.25VDD
VIL(7) S16 to S51 Output P-channel
Tr. OFF
Operation
CYC
t
4.5 to 6.0 0.98 400 µs
cycle time
Ratings
VDD[V] min. typ. max.
4.5 6.0
2.0 6.0
4.5 to 6.0 0.75VDD 13.5
4.5 to 6.0
4.5 to 6.0 VP 0.2VDD
Continue.
0.33VDD
+1.0
0.33VDD
+1.0
unit
V
VDD
VDD
-1.0
No.6690-11/22
Page 12
LC86P6548
Parameter Symbol Pins Conditions
Oscillation
frequency
range
(Note 1)
Oscillation
stabilizing
time period
(Note 1)
FmCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmCF(2) CF1, CF2 •3MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmRC RC oscillation 4.5 to 6.0 0.3 0.8 3.0
FsXtal XT1, XT2 •32.768kHz
(crysta l os cillation)
•Refer to figure 2
tmsCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tmsCF(2) CF1, CF2 •3MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kHz
(crysta l os cillation)
•Refer to figure 3
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 6
4.5 to 6.0 3
4.5 to 6.0 32.768 kHz
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0 s
unit
MHz
ms
(Note 1) The oscillation constant is shown on table 1.
No.6690-12/22
Page 13
LC86P6548
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
current
Input low
current
Output high
voltage
Output low
voltage
Pull-up MOS
Tr. resistor
IIH(1) Ports 0,3 at open
drain output
IIH(2) •Ports 1,3
•Port 0 without
pull-up MOS Tr.
IIH(3) •Ports 70,71,72,73
•Port 8
IIH(4)
IIH(5) Ports 74,75 VIN=VDD
IIH(6) •S32 to S51 without
IIL(1) •Ports 1,3
IIL(2) •Ports 70,71,72,73
IIL(3)
IIL(4) Ports
VOH(1) IOH=-1.0mA
VOH(2)
VOH(3) IOH=-20mA
VOH(4)
VOH(5) IOH=-5mA
VOH(6)
VOL(1) IOL=10mA
VOL(2)
VOL(3) Port 70 IOL=1mA
VOL(4) •Ports 71,72,73
Rpu Ports 0,1,3 VOH=0.9VDD
RES
VIN=VDD
pull-down resistor
•Port 0 without
pull-up MOS Tr.
•Port 8
RES
VIN=VSS
74
,75 VIN=VSS
Ports 0,1,3 of
CMOS output
S0/T0 to S15/T15
S16 to S51
Ports 0,1,3
•Ports 84,85,86,87
•Output disable
•VIN=13.5V
(including off-leakage
current of the output Tr.)
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VDD
(including off-leakage
current of the output Tr.)
•Output disable
•VIN=VDD
(including off-leakage
current of the output Tr.)
•Output P-channel Tr. OFF.
•VIN=VDD
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VSS
(including off-leakage
current of the output Tr.)
•Output disable
•VIN=VSS
(including off-leakage
current of the output Tr.)
IOH=-0.1mA
•IOH=-1.0mA
•The current of any
unmeasurement pin is not
over 1mA.
•IOH=-1.0mA
•The current of any
unmeasurement pins is not
over 1mA.
IOL=1.6mA
IOL=1.6mA
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
5 Input high
1
1
1
1
1
-1
-1
-1
-1
VDD-1
VDD-0.5
VDD-1.8
VDD-1
VDD-1.8
VDD-1
1.5
0.4
0.4
0.4
15 40 70 KΩ
unit
A
µ
V
Continue.
No.6690-13/22
Page 14
LC86P6548
Parameter Symbol Pins Conditions
IOFF(1) •Output P-channel
leakage current
IOFF(2)
•S0/T0 to S6/T6
•S32 to S51
(without pull-down
resistor)
Tr. OFF
•VOUT=VSS
•Output P- channel
Tr. OFF
•VOUT=VDD-40V
Resistance of
The low level
Hold Tr.
High voltage
Pull-down
resistor
Rinpd S16 to S51 •Output P-channel
Tr. OFF
•Using as input ports
Rpd •S7/T7 to S15/T15
•S16 to S31
•Output P-channel
Tr. OFF
•VOUT=3V
•Vp=-30V
VP pull-down
resistor
Hysteresis
voltage
Rvppd Vp •VSS=GND
•Vp=-30V
VHIS •Port 1
Output disable 4.5 to 6.0 0.1VDD V
•Ports 70,71,72,73,75
•
RES
Pin capacitance CP All pins •f=1MHz
•VIN=VSS for all
unmeasured terminals.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 -1 Output off-
4.5 to 6.0 -30
4.5 to 6.0 200
5.0 60 100 200
5.0 60 100 200
4.5 to 6.0 10 pF
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Cycle t
Low Level
CKCY
CKL
t
SCK0,SCK1 Refer to figure 5 4.5 to 6.0
(1) 2
(1) 1
pulse width
High Level
Input clock
CKH
t
(1)
pulse width
Cycle t
Serial clock
Low Level
pulse width
High Level
Output clock
pulse width
Data set-up time
Data hold time
Serial input
Output delay time
(External clock
using for serial
transfer clock)
Output delay time
(Internal clock
Serial output
using for serial
CKCY
CKL
t
CKH
t
ICK
t
0.1
CKI
t
CKO(1)
t
CKO(2)
t
SCK0,SCK1 •Use pull-up
(2) 2
(2) 1/2t
resistor (1kΩ) in
the open drain
(2)
output.
•Refer to figure 5
•SI0,SI1
•SB0,SB1
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5
7/12
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ) in
the open drain
output.
•Data hold from
SCK0,1
•Refer to figure 5
transfer clock)
Ratings
VDD[V] min. typ. max.
1
4.5 to 6.0
1/2t
4.5 to 6.0
0.1
4.5 to 6.0
1/3
CKCY
CKCY
CYC
t
+0.2
CYC
t
+0.2
unit
µ
KΩ
unit
CYC
t
µ
A
s
No.6690-14/22
Page 15
LC86P6548
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection clock
selected to 1/1.)
INT3/T0IN
(The noise rejection clock
selected to 1/16.)
INT3/T0IN
(The noise rejection clock
selected to 1/64.)
RES
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
Reset acceptable 4.5 to 6.0 200
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 2
4.5 to 6.0 32
4.5 to 6.0 128
unit
CYC
t
µ
High/low level
s
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Resolution N 4.5 to 6.0 8 bit
Absolute precision
(Note 2)
Conversion time tCAD
Analog input
voltage range
input current
ET 4.5 to 6.0 ±1.5 LSB
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
VAIN 4.5 to 6.0 VSS VDD V
IAINH VAIN=VDD 4.5 to 6.0 1 Analog port
IAINL
AN0 to AN7
VAIN=VSS 4.5 to 6.0 -1
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
15.68
(tCYC=
0.98µs)
31.36
(tCYC=
0.98 µs)
65.28
(tCYC=
4.08µs)
130.56
(tCYC=
4.08µs)
unit
s
µ
A
µ
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6690-15/22
Page 16
LC86P6548
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 4)
IDDOP(1) •FmCF=6MHz
IDDOP(2) •FmCF=3MHz
IDDOP(3) •FmCF=0Hz
IDDOP(4)
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
•1/2 divided
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 14 33
4.5 to 6.0 6 18
4.5 to 6.0 4 13
4.5 to 6.0 3 10
Continue.
unit
mA
No.6690-16/22
Page 17
LC86P6548
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 4)
Current dissipation
in HOLD mode
(Note 4)
IDDHALT(1) •HALT mode
IDDHALT(2) •HALT mode
IDDHALT(3) •HALT mode
IDDHALT(4)
IDDHOLD(1) HOLD mode
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 5 14
4.5 to 6.0 2.2 7
4.5 to 6.0 400 1600
4.5 to 6.0 25 100
4.5 to 6.0 0.05 30
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
A
µ
No.6690-17/22
Page 18
LC86P6548
Table 1. Ceramic resonator oscillation recommended constant (main-clock)
Oscillation type Maker Oscillator C1 C2
6MHz ceramic resonator
oscillation
Kyocera
3MHz ceramic resonator
oscillation
Kyocera
Murata
Murata
* Both C1 and C2 must be use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub-clock)
Oscillation type Maker Oscillator C3 C4 Rd Rf
32.768kHz crystal oscillation
* Both C3 and C4 must be use J rank (±5%) and CH characteristics.
(Not in need of high precision, use K rank (±10%) and SL characteristics.)
(Notes) • Please place the oscillation-related parts as close to the oscillation pins as possible with the shortest
possible pattern length since the circuit pattern affects the oscillation frequency.
• If you use other oscillators herein, we provide no guarantee for the characteristics.
CF2 CF1
XT2 XT1
Rf
Rd
C1
CF
C2
C3
X’tal
C4
Figure 1 Main-clock circuit Figure 2 Sub-clock circuit
Ceramic resonator oscillation Crystal oscillation
No.6690-18/22
Page 19
Internal RC resonator
HOLD release signal
Internal RC resonator
Power supply
RES
oscillation
CF1, CF2
XT1, XT2
Operation mode
oscillation
CF1, CF2
XT1, XT2
Operation mode
LC86P6548
Reset time
tmsCF
tssXtal
Instruction
Unfixed
Reset
execution mode
OCR6=1
Instruction execution mode
<Reset time and oscillation stable time>
Valid
tmsCF
tssXtal
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3 Oscillation stable time
VDD
VDD limit
0V
No.6690-19/22
Page 20
LC86P6548
VDD
RES
RES
R
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has be en over inferior limit of
RES
C
supply voltage.
Figure 4 Reset circuit
<AC timing point>
0.5VDD
SCK0
SCK1
SI0
SI1
tCKO
SO0, SO1
SB0, SB1
tCKCY
tCKI tICK
<Timing>
tCKH tCKL
VDD
1KΩ
50pF
Figure 5 Serial input / output test condition
tPIH tPIL
Figure 6 Pulse input timing condition
No.6690-20/22
Page 21
LC86P6548
Notice For Use
The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for
•
Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening
procedure shown in the following figure should always be followed.
It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed.
•
Keeping the dry packing
•
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
After openi ng the packing
•
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on
the substrate. After opening the packing, a controlled environment must be maintained until soldering. The
environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 96
hours.
Unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the
board.
a. Shipping with a blank PROM b. Shipping with a programmed PROM
(Programming the data by yourself) (P rogramming the data by Sanyo)
Recommended process of screening
Reading ascertain of program
QFP QFP
Writing data for
program/Verifying
Heat-soak
150±5°C,24 Hr
VDD=5±0.5V
+1
-0
Mounting
Mounting
No.6690-21/22
Page 22
memo:
LC86P6548
No.6690-22/22
PS
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