Ordering number : ENN4212A
Overview
The LC86P6032 microcontroller, a new addition to the LC866000 series, is a 8-bit single chip CMOS microcontroller with
one-time PROM. This microcontroller has the same function and pin assignment as for the LC866000 series mask ROM
version, and a 32K-byte PROM.
Features
(1) Option switching using PROM data
The optional functions of the LC866000 series can be specified using PROM data.
The functions of the trial products can be evaluated using a mass production board.
(2) Internal one-time PROM capacity : 32768 bytes
(3) Internal RAM capacity : 512 bytes
Mask ROM version PROM capacity RAM capacity
LC866032
LC866028
LC866024
LC866020
LC866016
LC866012
LC866008
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 0.98µs to 400µs
(6) Operating temperature range : -30°C to +70°C
(7) Pin and package compatible with the mask ROM version
(8) Applicable mask ROM version : LC866032/LC866028/LC866024/LC866020/LC866016 /LC866 012
/LC866008
(9) Factory shipment : DIP64S
: QFP64E
Programming service
We offer various services at nominal charges. These include ROM writing, ROM reading, and package stamping and
screening. Contact our local representatives for further information.
32512 bytes
28672 bytes
24576 bytes
20480 bytes
16384 bytes
12288 bytes
8192 bytes
CMOS IC
LC86P6032
8-Bit Single Chip Microcontroller
with One-Time PROM
512 bytes
512 bytes
512 bytes
384 bytes
384 bytes
384 bytes
384 bytes
Ver.1.02G
31293
91400 RM (IM) TW No.4212-1/22
LC86P6032
Notice for use
When using, please take note of the following.
(1) Differences between the LC86P6032 and the LC866000 series
Item LC86P6032 LC866032/28/24/20/16/12/08
Port status at reset Please refer to “Port status at reset” on t he next page.
Operation after releasing
reset
Output form of segment
•S0/T0 to S6/T6
•S7/T7 to S15/T15
•S16 to S23
•S24 to S29
Operating supply
voltage range (VDD)
Power dissipation Refer to “electrical characteristics” on the semiconductor news.
LC86P6032 uses 256 bytes that is addressed on 7F00H to 7FFFH in the program memory as the option
configuration data area. This option configuration cannot execute all options which LC866000 series have. Next
tables show the options that correspond and not correspond to LC86P6032.
• LC86P6032 Options
Option Pins, Circuits Option Settings
Configuration of input/output ports Port 0
Port 1
Port 7 pull-up MOS transistor Port 7
• A kind of option not corresponding LC86P6032
Option Pins, Circuits LC86P6032 LC866032/28/24/20/16/12/08
Pull-down resistor of high
voltage withstand output
terminal
The port operation related to the option is different at reset. Please refer to the next table.
The option is speci fied by degrees within
3ms after applying a ‘H’ level to the reset
pin.
The program located at 00H is
executed.
Pulldown resis tor
Not provided
Provided(fixed)
Provided(fixed)
Not provided
4.5V to 6.0V 2.5V to 6.0V
1. Input : No pull-up MOS transistor
(Can be specified for
each bit.)
(Can be specified for
each bit.)
(Can be specified for
each bit.)
·S0/T0 to S6/T6
·S16 to S23
·S24 to S29
(specified in a bit)
Output : N-channel open drain
2. Input : Pull-up MOS transistor
Output : CMOS
1. Input : Programmable pull-up MOS transistor
Output : N-channel open drain
2. Input : Programmable Pull -up MOS transistor
Output : CMOS
1. Pull-up MOS transist or not provided.
2. Pull-up MOS transist or provided.
Not provided
Provided(fixed)
Not provided
The program located at 00H is executed
immediately after applying a ‘H’ level t o
the reset pin.
Pulldown resistor : Provided/Not provided
Specified by the opt ion
Provided(fixed)
Specified by the opt ion
Specified by the opt ion
Specified by the option
Specified by the opt ion
Specified by the opt ion
No.4212-2/22
LC86P6032
• Port configuration at reset
Pin Option settings LC86P6032 LC866032/28/24/20/16/12/08
P0 Input : No pull-up MOS transistor
Output : N-channel open drain
Input : Pull-up MOS transistor
Output : CMOS
(Same as for the mask version) Input mode without pull-up
MOS transistor (Output is OFF)
Input mode
•The Pull-up MOS transistor is
Input mode with pull-up MOS
transistor (Output is OFF)
not present during reset or several
hundred microseconds after
releasing reset. After that, the
pull-up MOS transistor is present.
(Output is OFF)
P1 Input : Programmable pull-up MOS
transistor
(Same as for the mask version) Input mode without pull-up
MOS transistor (Output is OFF)
Output : N-channel open drain
Input : Programmable pull-up MOS
transistor
(Same as for the mask version) Input mode without pull-up
MOS transistor (Output is OFF)
Output : CMOS
P7 Pull-up MOS transistor not
provided
Pull-up MOS transistor pro v i de d Input mode
(Same as for the mask version) Input mode without pull-up
MOS transistor
Input mode with pull-up MOS
•The Pull-up MOS transistor is
transistor
not present during reset or several
hundred microseconds after
releasing reset. After that, the
pull-up MOS transi st or is present.
(2) Option
The option data is created by the option specified program “SU866000.EXE”. The created option data is linked to the
program area by the linkage loader “L866000.EXE”.
(3) ROM space
LC86P6032 and LC86 60 00 seri es use 2 56 b ytes that is a dd resse d o n 07 F00 H to 07 FFFH in t he pro gr am memory as t he
option specified data area. These program memory capacity are 32512 bytes that is addressed on 0000H to 7EFFH.
7FFFH
7F00H
7EFFH
6FFFH
Option data
area 256 bytes
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0000H
32K
LC866032
LC86P6032
28K
LC866028
24K
LC866024
20K
LC866020
16K
LC866016
12K
LC866012
8K
LC866008
(4) Ordering information
1.When ordering identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
No.4212-3/22
LC86P6032
How to use
(1) Specification of option
LC86P6032 is programmed after specifying option data. The option is specified by the SU866000.EXE. The specified
option file and the file created by our macro assembler (M866000.EXE) are linked by our linker (L866000.EXE) which
creates HEX file, then the option code is put in the option specified area (07F00H to 07FFFH) of its HEX file.
(2) How to program for the EPROM
The LC86P6032 can be programmed by an EPR O M programmer with attac hments W86EP6032D and W86EP6032Q.
- Recommended EPROM programmer
Supplier EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL 1890A
- “27512 (Vpp=12. 5 V) Int el high-sp eed pro gramming” mode availa ble. T he ad dr e ss must be set to “00 00 H to 07 FFFH ”
and the jumper (DASEC) must be set ‘OFF’ at programming
.
(3) How to use the data security function
“Data security” is a function to prevent EPROM data from being read.
Instructions on using the data security function :
1. Set the jumper of attachment “ON”.
2. Attempt to pro gram the E PRO M. The EPROM progr ammer will d isplay an er ror. The error ind icatio n is a result of
normal activity of the data security feature. This is not a problem with the EPROM programmer chip.
(Notes)
• The data security function is not carried out when the data of all addresses contain “FF” at step 2 above.
• Data security cannot be executed when the sequential operation “BLANK=>PROGRAM=>VERIFY” is used at step 2 above.
• Set the jumper “OFF” after execution of data security.
1 pin mark
of LSI
Data security
Data security
1 pin
Not data security Not data security
1 pin
W86EP6032Q W86EP6032D
No.4212-4/22
Pin Assignment
Package Dimension
(unit : mm)
3071
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM
TEST1
RES
XT1
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P70/INT0
P71/INT1
72/INT2/T0IN
73/INT3/T0IN
S0/T0
S1/T1
S2/T2
S3/T3
S4/T4
S5/T5
S6/T6
S7/T7
LC86P6032
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P07
P06
P05
P04
P03
P02
P01
P00
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
VP
VDDVPP
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
SANYO : DIP-64S(750mil)
No.4212-5/22
LC86P6032
Pin Assignment
P17/PWM
P16/BUZ
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P07
P06
P05
P04
P03
P02
P01
P00
6
7
8
9
10
11
12
13
14
15
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
VP
VDDVPP
TEST1
RES
XT1
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P70/INT0
P71/INT1
72/INT2/T0IN
73/INT3/T0IN
484746454443424140393837363534
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
S0/T0
S1/T1
S2/T2
S3/T3
S4/T4
S5/T5
S6/T6
S7/T7
S8/T8
S9/T9
S10/T10
S11/T11
S12/T12
S13/T13
S14/T14
S15/T15
Package Dimension
(unit : mm)
3159
SANYO : QIP-64E
Notes
• The QFP packages should be heat-soaked for 24 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours.
No.4212-6/22
System Bl ock Diagram
Interrupt Control
Stand-by C ontr ol
CF
LC86P6032
IR PLA
PROM
Control
A15-A0
D7-D0
TA
CE
OE
DASEC
VDDVPP
Base Timer
SIO0
SIO1
Timer 0
Timer 1
ADC
RC
X’tal
Clock
Generator
Bus Interface
Port 1
Port 7
Port 8
PROM(32KB)
PC
ACC
B Register
C Register
ALU
PSW
INT0 to 3
Noise Rejec tio n Filte r
Real Time Service
XRAM
(128 bytes)
VFD Controller
High Voltage Output
RAR
RAM
Stack Pointer
Port 0
Watch dog Ti me r
No.4212-7/22
LC86P6032
Pin Description
Pin Description Table
Pin name I/O Function Description Option Function in PROM mode
VSS - Power supply pin (-)
VDD - Power supply pin (+)
VP - Power supply pin (-) for the VFD output
pull-down resist
VDDVPP - Power supply pin (+) *6 Power for programming
PORT0
P00 to P07
PORT1
P10 to P17
PORT7
P70
P71 to P73
PORT8
P80 to P83
S0/T0 to
S6/T6 *7
S7/T7 to
S15/T15
*8
S16 to S23
*9
S24 to S29
*10
I Reset pin
RES
I/O •8-bit Input / output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
I/O •8-bit input/output port
•Data direction can be specified for each bit.
•Other pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus input/output
P12 : SIO0 clock input /output
P13 : SIO1 : data output
P14 : SIO1 : data input/bus input/output
P15 : SIO1 clock input /output
P16 : Buzzer output
P17 : Timer 1 output (PWM output)
•4-bit input port
•Other pin functions
P70 : INT0 input/HOLD release/N-chann el
I/O
Tr. output for watchdog timer
P71 : INT1 input/HOLD release
I
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
•Interrupt received format, vector address
Rising Falling Rising
/falling
INT0
INT1
INT2
INT3
I •4-bit input port
•Other pin functions
AD input port (4 port pins)
O Output for VFD display controller
segment/timing in common
O •Output for VFD display controller
segment/timing in common
•Internal pull-down resistor output
O •Output for VFD display controller
segment
•Internal pull-down resistor output
O •Output for VFD display controller
segment
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
Disable
Enable
Enable
•Pull-up resistor :
Present/Not present
•Output form :
CMOS/N-channel
open drain
Output form :
CMOS/N-channel
open drain
•Pull-up resistor :
Present/Not present
H level L level Vector
Enable
Enable
Disable
Disable
Enable
Enable
Disable
Disable
•S14/T14 : TA (*4)
Address input
03H
0BH
13H
1BH
Data input/output
D0 to D7
Input of PROM control
signal
•DASEC (*1)
OE
(*2)
•
CE
(*3)
•
•S15/T15 : A 14 (*5)
A13 to A0
No.4212-8/22
LC86P6032
Pin name I/O Function Description Option Function in PROM mode
TEST1 O Test pin
Should be left open
XT1 I Input pin for 32.768kHz crystal oscillation
When not used, connect to VDD
XT2 O Output pin for 32.768kHz crystal oscillation
When not used, should be left open
CF1 I Input pin for ceramic resonator oscillation
CF2 O Output pin for ceramic resonator oscillation
• All port options can be specified in bit units.
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 TA ! PROM control signal input
*5 A14 ! Address input
*6 Connect as shown in the following figure to reduce noise into VDD pin.
• Short-circuit the VDD pin to the VDD VPP pin.
VDD
LSI
Power
Supply
VDDVPP
VSS
*7 S0/T0 to S6/T6 : not provi ded the pull -down re sistor
*8 S7/T7 to S15/T15 : provided the pull-down resistor (fixed)
*9 S16 to S23 : provided the pull-down resistor (fixed)
*10 S24 to S29 : not provided the pull-down resistor
No.4212-9/22
LC86P6032
1. Absolute Maximu m Ratings at VSS=0V and Ta=25°C
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD,VDDVPP -0.3 +7.0
Input voltage VI(1) •Ports 71,72,3,8
•
RES
VI(2) VP VDD-4.5
Output voltage VO • S0/T0 to S15/T15
•S16 to S29
Input/Output
voltage
High
level
output
current
Low
level
output
current
(max.)
Operating
temperature range
Storage
temperature range
Peak
output
current
Total
output
current
output
current
Total
output
current
VIO •Ports 0, 1
•Port 70
IOPH(1) Ports 0, 1 •CMOS output
IOPH(2) S0/T0 to S15/T15 •At each pin -30
IOPH(3) S16 to S29 •At each pin -15
IOAH(1) Port 0 Total of all pins -10
∑
IOAH(2) Port 1 Total of all pins -10
∑
IOAH(3) •S0/T0 to S15/T15
∑
•S16 to S29
IOPL(1) Ports 0, 1 At each pin 20 Peak
IOPL(2) Port 70 At each pin 15
IOAL(1) Port 0 Total of all pins 40
∑
IOAL(2) Ports 1, 70 Total of all pins 40
∑
Pdmax(1) DIP64S Ta=-30 to+70°C 760 mW Power dissipation
Pdmax(2) QFP64E Ta=-30 to+70°C 430
Topr -30 +70
Tstg -65 +150
-0.3
VDD-4.5
-0.3
•At each pin
Total of all pins -130
Ratings
VDD[V]
min. typ. max.
VDD+0.3
VDD+0.3
VDD+0.3
VDD+0.3
-4
unit
mA
°
V
C
Notes
• The QFP packages should be heat-soaked for 24 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours.
No.4212-10/22
LC86P6032
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Operating
supply voltage
range
Hold voltage VHD V DD RAM and registers
Pull-down
voltage
Input high
voltage
Input low
voltage
Operation
cycle time
VDD VDD 0.98µs ≤ tCYC ≤
400µs
retain their
pre-HOLD mode
values
VP VP 4.5 to 6.0 -35 VDD
VIH(1) Port 0 (Schmitt) Output disable 4.5 to 6.0 0.4VDD
VIH(2) •Port 1
•Ports 72,73
(Schmitt)
VIH(3) •Port 70
port input/interrupt
•Port 71
(Schmitt)
•
RES
VIH(4) Port 70
Watchdog timer
VIH(5) Port 8 4.5 to 6.0
VIL(1) Port 0 (Schmitt) Output disable 4.5 to 6.0 VSS 0.2VDD
VIL(2) •Port 1
•Ports 72,73
(Schmitt)
VIL(3) •Port 70
port input/interrupt
•Port 71
RES
(Schmitt)
•
VIL(4) Port 70
Watchdog timer
VIL(5) Por t 8 4.5 to 6.0 VSS 0.25VDD
tCYC 4.5 to 6.0 0.98 400 µs
Output disable 4.5 to 6.0
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Output disab le 4.5 to 6. 0 VSS 0.25 VDD
N-channel
Tr. OFF
N-channel
Tr. OFF
VDD[V] min. typ. max.
4.5 to 6.0
4.5 to 6.0 0.9VDD VDD
4.5 to 6.0 VSS 0.25 VDD
4.5 to 6.0 VSS 0.8VDD
Ratings
4.5 6.0
2.0 6.0
VDD
+0.9
0.75VDD
0.75VDD
0.75VDD
VDD
VDD
VDD
-1.0
unit
V
continue
No.4212-11/22
LC86P6032
Parameter Symbol Pins Conditions
Oscillation
frequency
range
(Note 1)
Oscillation
stable time
period
(Note 1)
tmsCF(2) CF1,CF2 •3MHz (ceramic
tssXtal XT1,XT2 •32.768kHz
FmCF(1) CF1,CF2 •12MHz (ceramic
resonator
oscillation)
•Refer to figure 1
FmCF(2) CF1,CF2 •3MHz (ceramic
resonator
oscillation)
•Refer to figure 1
FmRC RC oscillation 4.5 to 6.0 0.4 0.8 2.0
FsXtal XT1,XT2 •32.768kHz
(crysta l re sonator
oscillation)
•Refer to figure 2
tmsCF(1) CF1,CF2 •12MHz (ceramic
resonator
oscillation)
•Refer to figure 3
resonator
oscillation)
•Refer to figure 3
(crystal re s ona tor
oscillation)
•Refer to figure 3
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 11.76 12 12.24 MHz
4.5 to 6.0 2.94 3 3.06
4.5 to 6.0 32.768 kHz
4.5 to 6.0 0.02 0.2 ms
4.5 to 6.0 0.1 1
4.5 to 6.0 1 1.5 s
(Note 1) The oscillation constants are shown on Table 1 and Table 2.
unit
No.4212-12/22
LC86P6032
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Input high
current
Input low
current
Output high
voltage
Output low
voltage
Pull-up MOS
Tr. resistance
IIH(1) •Port 1
•Port 0 without
pull-up MOS Tr.
IIH(2) •Port 7 without
pull-up MOS Tr.
•Port 8
IIH(3)
IIL(1) •Port 1
IIL(2) •Port 7 without
IIL(3)
VOH(1) IOH=-1.0mA 4.5 to 6.0 VDD-1
VOH(2)
VOH(3) S0/T0 to S15/T15 IOH=-20mA 4.5 to 6.0
VOH(4) •IOH=-1mA
VOH(5) S16 to S29 IOH=-5mA 4.5 to 6.0
VOH(6) •IOH=-1mA
VOL(1) Ports 0, 1 IOL=10mA 4.5 to 6.0 1.5
VOL(2) •IOL=1.6mA
VOL(3) Port 70 IOL=1mA 4.5 to 6.0 0.4
Rpu •Ports 0, 1
VIN=VDD 4.5 to 6.0 1
RES
•Port 0 without
pull-up MOS Tr.
pull-up MOS Tr.
•Port 8
VIN=VSS 4.5 to 6.0 -1
RES
Ports 0, 1 at
CMOS output
•Port 7
•Output disabled
•Pull-up MOS Tr.
OFF
•VIN=VDD
(including off-state
leak current of
output Tr.)
VIN=VDD 4.5 to 6.0 1
•Output disabled
•Pull-up MOS Tr.
OFF
•VIN=VSS
(including off-state
leak current of
output Tr.)
VIN=VSS 4.5 to 6.0 -1
IOH=-0.1mA 4.5 to 6.0
•The current IOH at
each pin should be
between 0 and
-1mA.
•The current IOH at
each pin should be
between 0 and
-1mA.
•When the total
current of the
ports 0, 1 is not
over 40mA.
VOH=0.9VDD 4.5 to 6.0 15 40 70 KΩ
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 -1
VDD-0.5
VDD-1.8
4.5 to 6.0 VDD-1
VDD-1.8
4.5 to 6.0 VDD-1
4.5 to 6.0 0.4
unit
A
µ
V
continue
No.4212-13/22
LC86P6032
Parameter Symbol Pins Conditions
•Output P-ch Tr. OFF
•
VOUT=VSS
•Output P-ch Tr. OFF
•
VOUT=VDD-40V
•Output P-ch Tr. OFF
•
VOUT=3V
•
Vp=-30V
Output disable 4.5 to 6.0 0.1VDD V
•
Unmeasured input
leakage
current
Pull-down
resistor
Hysteresis
voltage
Pin
capacitance
IOFF(1)
S0/T0 to S6/T6,
S24 to S29 without
IOFF(2)
pull-down resistor
Rpd S7/T7 to S15/T15,
S16 to S23 with
pull-down resistor
VHIS
•
Ports 0, 1
•
Port 7
RES
•
CP All pins •f=1MHz
pins are set to
VSS level
•
Ta=25°C
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 -1
4.5 to 6.0 -30
5.0 60 100 200 KΩ
4.5 to 6.0 10 pF
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Cycle t
Low-level
CKCY
CKL
t
SCK0,
(1) 4.5 to 6.0 2
SCK1
(1) 4.5 to 6.0 1
Refer to figure 5.
pulse width
High-level
Input clock
CKH
t
(1)
pulse width
Cycle t
Serial clock
Low-level
pulse width
High-level
Output clock
pulse width
Data set up ti me
Data hold time
Serial input
Output delay time
(Serial clock is
external clock)
Output delay time
Serial output
(Serial clock is
internal clock)
CKCY
CKL
t
CKH
t
ICK
t
CKI
t
CKO(1)
t
CKO(2)
t
SCK0,
(2) 4.5 to 6.0 2
SCK1
(2) 4.5 to 6.0 1/2
•Use pull-up
resistor (1kΩ)
when set to open-
(2)
drain output.
•Refer to figure 5.
•SI0,SI1
4.5 to 6.0 0.1
•SB0,SB1
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5.
•SO0,SO1
4.5 to 6.0 7/12
•SB0,SB1
•Use pull-up
resistor (1kΩ)
when set to open drain output.
•Data hold from
SCK0,1
•Refer to figure 5.
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 1/2
4.5 to 6.0 0.1
4.5 to 6.0 1/3
unit
µ
Ratings
unit
CYC
t
CKCY
t
CKCY
t
CYC
t
+0.2
CYC
t
+0.2
A Output off-
s
µ
No.4212-14/22
LC86P6032
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIL(4)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection
clock selected to
1/1.)
INT3/T0IN
(The noise rejection
clock selected to
1/64.)
RES
•Interrupt accept able
•Timer0 pulse
countable
•Interrupt accept able
•Timer0 pulse
countable
•Interrupt accept able
•Timer0 pulse
countable
Reset acceptable 4.5 to 6.0 200
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 2
4.5 to 6.0 128
unit
CYC
t
High/low level
s
µ
6. AD Converter Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Resolution N 4.5 to 6.0 8 bit
Absolute precision ET (Note 2) 4.5 to 6.0 ±1.5 LSB
Conversion time tCAD
Analog input
voltage range
input current
VAIN 4.5 to 6.0 VSS VDD V
IAINH VAIN=VDD 4.5 to 6.0 1 Analog port
IAINL
AN0 to AN3
AD conversion time
= 16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time
= 32 × tCYC
(ADCR2=1)
(Note 3)
VAIN=VSS 4.5 to 6.0 -1
Ratings
VDD[V] min. typ. max. unit
4.5 to 6.0
15.68
(tCYC=
0.98µs)
31.36
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
130.56
(tCYC=
4.08µs)
s
µ
A
µ
(Note 2) Quantizing error (±1/2 LSB) is ignored.
(Note 3) The conversion time is the period from execution of the instruction to start conversion to the completion of shifting
the A/D converted value to the register.
No.4212-15/22
LC86P6032
7. Current Drain Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Current drain during
basic operatio n
(Note 4)
IDDOP(1) •FmCF=12MHz for
IDDOP(2) •FmCF=3MHz for
IDDOP(3) •FmCF=0Hz
IDDOP(4)
VDD
Ceramic resonator
oscillation
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
Ceramic resonator
oscillation
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
(when oscillator
stops)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
RC oscillator
•FmCF=0Hz
(when oscillator
stops)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
crystal oscillator
•Internal RC
oscillator stopped
Continue.
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 13 26
4.5 to 6.0 6.5 14
4.5 to 6.0 4 10
4.5 to 6.0 3.5 9
unit
mA
No.4212-16/22
LC86P6032
Parameter Symbol Pins Conditions
Current drain at
HALT mode
(Note 4)
HOLD mode
(Note 4)
IDDHALT(1) •HALT mode
IDDHALT(2) •HALT mode
IDDHALT(3) •HALT mode
IDDHALT(4)
IDDHOLD(1) 4.5 to 6.0 0.05 30 Current drain at
IDDHOLD(2)
VDD
•FmCF=12MHz for
Ceramic resonator
oscillation
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
•FmCF=3MHz for
Ceramic resonator
oscillation
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
•FmCF=0Hz
(when oscillator
stops)
•FsXtal=32.768kHz
crystal oscillator
•System clock :
RC oscillator
•HALT mode
•FmCF=0Hz
(when oscillator
stops)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
crystal oscillator
•Internal RC
oscillator stopped
VDD HOLD mode
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 5 10
4.5 to 6.0 1.8 4.6
4.5 to 6.0 400 800
4.5 to 6.0 20 60
2.5 to 4.5 0.02 20
(Note 4) The currents of output transistors and pull-up MOS transistors are ignored.
unit
mA
A
µ
No.4212-17/22
LC86P6032
Table 1. Ceramic resonator oscillation circuit recomm ended constants (main-clock)
Oscillation type Supplier Oscillator C1 C2
12MHz ceramic resonato r
oscillation
3MHz ceramic resonator
oscillation
Murata CSA12.0MTZ 33pF 33pF
CSA12.0MT 33pF 33pF
CST12.0MTW on chip
Kyocera KBR-12.0M 33pF 33pF
Murata CSA3.00MG 33pF 33pF
CST3.00MGW on chip
Kyocera KBR-3.0MS 47pF 47pF
* For both C1 and C2, the K rank (±10%) and SL characteristics must be used.
Table 2. Crystal oscillation circuit recommended constants (sub-clock)
Oscillation type Supplier Oscillator C3 C4
Daishinku DT-38(1TA252E00) 18pF 18pF 32.768kHz crystal
oscillation
Kyocera KF-38G-13P0200 18pF 18pF
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1 CF2
XT1 XT2
CF
C2 C1
X’tal
C4 C3
Figure 1 Ceramic resonator oscillation Figure 2 Crystal oscillation
No.4212-18/22
LC86P6032
Power supply
RES
Reset time
VDD
VDD limit
0V
Internal RC
resontor
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Reset Unfixed Instruction execution mode
< Reset time and oscillation stable time. >
HOLD release signal
Valid
Internal RC
resontor
oscillation
tmsCF
CF1, CF2
XT1, XT2
tssXtal
Operation mode
HOLD
Instruction execution mode
< Hold release signal and oscillation stable time. >
Figure 3 Oscillation stable time
VDD
RES
RES
R
(Note) The values of C
RES
and R
RES
should
be determined such that reset time is at
least 200µs, measured from the
C
RES
moment the power exceeds the VDD
lower limit.
Figure 4 Reset circuit
No.4212-19/22
SO0, SO1
SB0, SB1
SCK0
SCK1
SI0
SI1
LC86P6032
0.5VDD
<AC timing point>
tCKCY
tCKL tCKH
tICK tCKI
tCKO
<Timing>
Figure 5 Serial input/output test conditions
tPIL tPIH
Figure 6 Pulse input timing conditions
VDD
1KΩ
50pF
<Test load>
No.4212-20/22
LC86P6032
Notice for use
• The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for SANYO
to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown
in the following figure should always be followed.
• It is not possible to perform a writing test on the blank PROM.. 100% yield, therefore, cannot be guaranteed.
• Should be stored in dry conditions (QFP type only)
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
• After opening the packing (QFP type only)
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the
substrate. After opening the packing, a controlled environment must be maintained until soldering. The environment must be
held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours.
a. Shipping with a blank PROM (Data to be programmed by customer)
This microcomputer is provided DIP/QFP packages, but the condition before mounting is not same.
Refer to the mounting precedure as follows;
DIP
QFP
Programming and verifying
Programming and verifying
Recommended process of screening
Recommended process of screening
Heat-soak
Mounting
+1
-0
150±5°C, 24 Hr
Program reading test
Heat-soak
Baking
Mounting
+1
-0
150±5°C, 24 Hr
Program reading test
Baking before mounting
125°C, 24 hours
No.4212-21/22
LC86P6032
b. Shipping with programmed PROM (Data programmed by Sanyo)
DIP
QFP
Baking before mounting
125°C, 24 hours
Baking
Mounting
Mounting
No.4212-22/22
PS
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