Ordering number : ENN*6688
CMOS IC
LC86P5632
8-Bit Single Chip Microcontroller
with One-Time Programmable PROM
Preliminary
Overview
The LC86P5632 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC865600 series.
This microcontroller has the function and the pin description of the LC865600 series mask ROM version, and 32K-byte
PROM.
DIP/QFP package are available for shipping as well as LC865600 series. It is suitable to set up first release, prototyping,
developing and testing of set.
Features
(1) Option switching by PROM data
The option function of the LC865600 series can be specified by the PROM data.
LC86P5632 can be checked the function of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity : 32768 bytes
(3) Internal RAM capacity : 512 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P5632.
Mask ROM version PROM capacity RAM capacity
LC865632 32512 bytes 512 bytes
LC865628 28672 bytes 512 bytes
LC865624 24576 bytes 512 bytes
LC865620 20480 bytes 384 bytes
LC865616 16384 bytes 384 bytes
LC865612 12288 bytes 384 bytes
LC865608 8192 bytes 384 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping
and the screening. Contact our representative for further information.
Ver.1.01
22699
91400 RM (IM) HK No.6688-1/23
LC86P5632
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 0.98µs to 400µs
(6) Operating temperature : -30°C to +70°C
(7) The pin and the package compatible with the LC865600 series mask ROM devices
(8) Applicable mask ROM version : LC865632/ LC865628/ LC865624/LC865620/LC865616/
LC865612/ LC865608
(9) Factory shipment : DIP64S, QFP64E
Notice for use
LC86P5632 is provided for the first release and small shipping of the LC865600 series.
At using, take notice of the followings.
(1) A point of difference LC86P5632 and LC865600 series
Item LC86P5632 LC865632/28/24/20/16/12/08
Port form at reset Please refer “Port form at reset “ on next page.
Operation after reset
releasing
Operating supply voltage
range (VDD)
Total output current
[∑IOAH(1)]
[∑IOAH(2)]
Power dissipation
[IDDOP(1)]
[IDDOP(2)]
[IDDOP(3)]
[IDDOP(4)]
• A kind of the option corresponding of the LC86P5632
A kind of option Pins, Circuits Contents of the option
Input/output form of
Input/output ports
Pull-up MOS Tr. Of port7 port7
The port operation related the option is different at reset. Refer to the next table.
The option is specified until 3ms
after going to a ‘H’ level to the reset
terminal by dgrees. The program
The program is executed from 00H of
the program counter immediately after
going to a ‘H’ level to reset terminal.
is executed from 00H of the
program counter.
4.5V to 6.0V 2.7V to 6.0V
Refer to ‘electrical characteristics’ on the semiconductor news.
Port 0
(Specified in a bit)
1. Input : No pull-up MOS Tr.
Output : N-channel open drain
2. Input : P ull-up MOS Tr.
Output : CMOS
Port 1,2
(Specified in a bit)
1. Input : P rogrammable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Pro grammable pull-up MOS Tr.
Output : CMOS
Port 3,4,5
(Specified in a bit)
1. Input : No Programmable pull-up MOS
Tr.
Output : N-channel open drain
2. Input : P rogrammable pull-up MOS Tr.
Output : CMOS
1. Pull-up MOS Tr. not provided
(Specified in a bit)
2. Pull-up MOS Tr. provided
P74
*
has on pull-up resistor option.
No.6688-2/23
LC86P5632
• Port form at reset
Pin Contents of the option LC86P5632 LC865632/28/24 /20/16/12/08
Input : Not pull-up MOS Tr.
P0
Output : N-channel open drain
Input : Pull-up MOS Tr.
Output : CMOS
(Same as the mask version) Input mode without pull-up
MOS Tr. (Output is OFF)
Input mode
•The pull-up MOS Tr. is not provided
Input mode without pull-up
MOS Tr. (Output is OFF)
during reset or several hundred
microseconds after releasing reset.
After that, the pull-up MOS Tr. is
provided. (Output is OFF)
Input : Programmable pull-up
P1,
P2
MOS Tr.
(Same as the mask version) Input mode without pull-up
MOS Tr. (Output is OFF)
Output : N-channel open drain
Input : Programmable pull-up
MOS Tr.
(Same as the mask version) Input mode without pull-up
MOS Tr. (Output is OFF)
Output : CMOS
P3,
P4,
P5
Input : Not Programmable
pull-up MOS Tr.
Output : N-channel open drain
Input : Programmable pull-up
MOS Tr.
(Same as the mask version) Input mode without pull-up
MOS Tr. (Output is OFF)
(Same as the mask version) Input mode without pull-up
MOS Tr. (Output is OFF)
Output : CMOS
Pull-up MOS Tr. not provided (Same as the mask version) Input mode without pull-up
P7
MOS Tr.
Pull-up MOS Tr. provided
Input mode
•The pull-up MOS Tr. is not provided
Input mode without pull-up
MOS Tr.
during reset or several hundred
microseconds after releasing reset.
After that, the pull-up MOS Tr. is
provided.
(2) Option
LC86P5632 uses 256 bytes which is addressed on 7F00 H to 7FFFH in the program memory as option data area . This
area does not affect the execution of program but the program memory capacity of LC865632 is 32512 bytes which is
addressed on 0000H to 7EFFH.
The option data is created by the option specified program “SU865000.EXE”. The created option data is linked to the
program area by linkage loader “L865000.EXE”.
No.6688-3/23
LC86P5632
(3) ROM space
7FFFH
7F00H
7EFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
Option data
area 256 bytes
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
0000H
Program area
32K bytes
LC865632
Program area
28K bytes
LC865628
Program area
24K bytes
LC865624
Program area
20K bytes
LC865620
Program area
16K bytes
LC865616
Program area
12K bytes
LC865612
Program area
8K bytes
LC865608
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the
mask ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
How to use
(1) Specification of option
Programming data for PROM of the LC86P5632 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P5632.
(2) How to program for the PROM
LC86P5632 can be programmed by the EPROM programmer with attachment ; W86EP5032D,
W86EP5032Q.
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL 1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The addr ess must be set to
“0000H to 7FFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming
(3) How to use the data security function
“Data security” is the disabled function to read the data of the PROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
.
No.6688-4/23
LC86P5632
Notes
• Data security is not executed when the data of all address have ‘FF’ at the sequence 2 above.
• The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
Data security
Data security
1 pin mark
of LSI
1 pin
Not data security
1 pin
Not data security
W86EP5032D W86EP5032Q
No.6688-5/23
P11/SI0/SB0
P14/SI1/SB1
P72/INT2/T0IN
P73/INT3/T0IN
Package Dimension
(unit : mm)
3071
P10/SO0
P12/SCK0
P13/SO1
P15/SCK1
P16/BUZ
P17/PWM
TEST1
RES
XT1/
P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P70/INT0
P71/INT1
P30
P31
P32
P33
LC86P5632
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P07
P06
P05
P04
P03
P02
P01
P00
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34
SANYO : DIP-64S(750mil)
No.6688-6/23
LC86P5632
P17/PWM
P16/BUZ
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P07
P06
P05
P04
P03
P02
P01
P00
TEST1
RES
P74
XT1/
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
48474645444342
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
414039383736353433
6
7
8
9
10
11
12
13
14
15
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
P70/INT0
P71/INT1
P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P72/INT2/T0IN
P73/INT3/T0IN
Package Dimension
(unit : mm)
3159
SANYO: QIP-64E
Notes
• The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6688-7/23
System Bl ock Diagram
Interrupt Control
Standby Control
X’tal
Base Timer
SIO0
SIO1
Timer 0
Timer 1
ADC
INT0 to 3
Noise Filter
Real Time
Service
XRAM
(128 bytes)
CF
RC
Clock
Generator
LC86P5632
Bus Interface
Port 1
Port 7
Port 8
Port 2
Port 3
Port 4
Port 5
IR PLA
EPROM
Control
EPROM (32KB)
PC
ACC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
Port 0
Watch Do g Timer
A15-A0
D7-D0
TA
CE
OE
DASEC
VDDVPP
No.6688-8/23
LC86P5632
LC86P5632 Pin description
Pin name I/O Function description Option PROM mode
VSS - Power pin (-) - VDD - Power pin (+) - VDDVPP - Power pin (+) - Power for programming
PORT0
P00 to P07
PORT1
P10 to P17
PORT2
P20 to P27
PORT3
P30 to P37
PORT4
P40 to P47
PORT5
P50 to P51
PORT7
P70
P74
P71 to
I/O •8-bit input/output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Bu zzer output
P17 Timer 1 output (PWM0 output)
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
I/O •2-bit input/output port
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
•5-bit input port
•Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
outp ut for watchdog timer
P71 : INT1 input/HOLD release input
I/O
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event
I
input
P74
: 32.768kHz cry s ta l oscillation terminal XT1
•Interrupt recei ved forms,
rising falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
the vector addresses
rising
falling
&
high
level
Continue.
low
level
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
•Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
has no pull-up
•
P74
resistor.
vector
-
Data line
D0 to D7
Address input
A7 to A0
Address input
A14 to A8 (*5)
P47 : TA (*4)
Input of PROM
control sign als
DASEC (*1)
(*2)
OE
(*3)
CE
No.6688-9/23
LC86P5632
Pin name I/O Function description Option PROM mode
PORT8
P80 to 87
RES
TEST1
P74
XT1/
XT2 O •Output pin for 32.768kHz crystal oscillation
CF1 I Input pin for the ceramic resonator oscillation - CF2 O Output pin for the ceramic resonator oscillation - -
All of port options can be specified in bit unit.
♦
I •8-bit input port
•Other function
AD input port (AN7 to AN0)
I Reset pin - -
O Test pin
Should be left unconnected.
I •Input pin for 32.768kHz crystal oscillation
•Other function : Input port
In case of non use, connect to VDD.
•Other function
In case of non use, should be left unconnected.
P74
- -
- -
- -
- -
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 TA ! PROM control signal input
*5 A14 ! Address input
* Connect like the following figure to reduce noise into a VDD terminal.
Short-circuit the VDD terminal to the VDDVPP te r mina l.
Short-circuit the VSS ter mina l to the VSS termin al.
VDD
LSI
Power
Supply
VDDVPP
VSS VSS
No.6688-10/23
LC86P5632
V
1. Absolute Maximu m Ratings at VSS=0V and Ta=25°C
Parameter Symbol Pins Conditions
Ratings
DD[V] min. typ. max.
Supply voltage VDDMAX VDD,VDDVPP VDD=VDDVPP -0.3 +7.0
Input voltage VI(1)
•Ports 71,72,73,
74
-0.3 VDD+0.3
unit
V
•Port 8
RES
•
voltage
VIO(1) •Ports 0,1,2
•Ports 3,4,5 at CMOS
-0.3 VDD+0.3 Input/Output
output
VIO(2) Ports 3,4,5 at N-ch open
-0.3 15
drain output option
High
level
output
current
Peak
output
current
Total
IOPH(1) •Ports 0,1,2,3,4,5 •CMOS output
•At each pins
IOAH(1)
Σ
Ports 0,1,2 The total of all pins -25
-4
mA
output
current
ΣIOAH(2)
Ports 3,4,5
The total of all pins -20
Low
level
output
current
dissipation
Operating
output
current
Total
output
current
IOPL(1) Ports 0,1,2,3,4,5 At each pins 20 Peak
IOPL(2) Port 70 At each pins 15
ΣIOAL(1)
IOAL(2)
Σ
ΣIOAL(3)
Ports 0,1,70 The total of all pins 40
Port 2 The total of all pins 40
Ports 3,4,5 The total of all pins 80
Pdmax(1) DIP64S Ta=-30 to+70°C 720 Maximum power
Pdmax(2) QFP64E Ta=-30 to+70°C 420
Topr -30 70
mW
C
°
temperature
range
Storage
Tstg -65 150
temperature
range
Notes
• The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6688-11/23
LC86P5632
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Operating
Supply voltage
VDD(1) VDD
0.98µs≤tCYC
tCYC≤400µs
Hold voltage VHD VDD RAMs and the
registers hold
voltage at HOLD
mode.
Input high
VIH(1) Port 0 (Schmitt) Output disable 4.5 to 6.0
voltage
VIH(2) •Ports 1,2
Output disable 4.5 to 6.0 0.75VDD VDD
•Ports 72,73 (Schmitt)
VIH(3) •Port 70
(Port input/interrupt)
Output N-channel
Tr. OFF
•Port 71
RES
•
VIH(4) Port 70
(Watchdog timer)
VIH(5)
•Port
•Port 8
VIH(6) Ports 3,4,5 of
74
(Schmitt)
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Output disable 4.5 to 6.0 0.75VDD VDD
CMOS output (Schmitt)
VIH(7) Ports 3,4,5 of open drain
Output disable 4.5 to 6.0 0.75VDD 13.5
output (Schmitt)
Input low
voltage
VIL(1) Port 0 (Schmitt) Output disable 4.5 to 6.0 VSS 0.2VDD
VIL(2) •Ports 1,2,3,4,5
Output disable 4.5 to 6.0 VSS 0.25VDD
•Ports 72,73 (Schmitt)
VIL(3) •Port 70
N-channel Tr.OFF 4.5 to 6.0 VSS 0.25VDD
(Port input/interrupt)
•Port 71
RES
•
VIL(4) Port 70
(Schmitt)
N-channel Tr.OFF 4.5 to 6.0 VSS
(Watchdog timer)
VIL(5)
•Port
74
N-channel Tr.OFF 4.5 to 6.0 VSS 0.25VDD
•Port 8
Operation
tCYC 4.5 to 6.0 0.98 400
cycle time
Oscillation
frequency
range
(Note 1)
FmCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmCF(2) CF1, CF2 •1.5MHz
(ceramic resonator
oscillation)
•Refer to figure 1
FmRC RC oscillation 4.5 to 6.0 0.3 0.8 3.0
FsXtal XT1, XT2 •32.768kHz
(crystal oscillation)
•Refer to figure 2
Continue.
Ratings
VDD[V] min. typ. max.
4.5 6.0
unit
V
2.0 6.0
4VDD
0.
+0.9
VDD
4.5 to 6.0 0.75VDD VDD
4.5 to 6.0 0.9VDD VDD
4.5 to 6.0 0.75VDD VDD
8VDD
0.
-1.0
µs
4.5 to 6.0 6
MHz
4.5 to 6.0 1.5
4.5 to 6.0 32.768 kHz
No.6688-12/23
LC86P5632
Parameter Symbol Pins Conditions
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tmsCF(2) CF1, CF2 •1.5MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kHz
(crystal oscillation)
”Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
unit
ms
4.5 to 6.0
4.5 to 6.0 s
No.6688-13/23
LC86P5632
0
D
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Input high
current
IIH(1) Ports 3,4,5 at open
drain output
•Output disa ble
•VIN=13.5V
Ratings
VDD[V] min. typ. max.
unit
4.5 to 6.0 5
µA
(including off-leakage
current of the output Tr.)
IIH(2) •Port 0 without
pull-up MOS Tr .
•Ports 1,2,3,4,5
•Output disa ble
•Pull-up MOS Tr. OFF.
•VIN=VDD
4.5 to 6.0 1
(including off-leakage
current of the output Tr.)
IIH(3) •Ports 70,71,72,73
VIN=VDD 4.5 to 6.0 1
without pull-up
MOS Tr.
•Port 8
Input low
current
IIH(4)
RES
IIL(1) •Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr .
VIN=VDD 4.5 to 6.0 1
•Output disa ble
4.5 to 6.0 -1
•Pull-up MOS Tr. OFF.
•VIN=VSS
(including off-leakage
current of the output Tr.)
IIL(2) •Ports 70,71,72,73
VIN=VSS 4.5 to 6.0 -1
without pull-up
MOS Tr.
•Port 8
VIN=VSS 4.5 to 6.0 -1
IOH=-0.1mA 4.5 to 6.0 VDD-0.5
IOL=1.6mA 4.5 to 6.0 0.4
IOL=0.5mA 4.5 to 6.0 0.4
VOH=0.9VDD 4.5 to 6.0 15 40 70
Output disable 4.5 to 6.0
.1VD
4.5 to 6.0 10 pF
•VIN=VSS for all
V
kΩ
V
voltage
Output low
voltage
IIL(3)
VOH(1) IOH=-1.0mA 4.5 to 6.0 VDD-1 Output high
VOH(2)
VOL(1) IOL=10mA 4.5 to 6.0 1.5
VOL(2)
VOL(3) IOL=1mA 4.5 to 6.0 0.4
RES
Ports 0,1,2,3,4,5 at
CMOS output
Ports 0,1,2 , 3,4,5
Port 70
VOL(4)
Pull-up MOS
Tr. resistor
Hysteresis
voltage
Pin
Rpu •Ports 0,1,2,3,4,5
•Ports 70,71,72,73
VHIS •Ports 0,1,2,3,4,5
•Ports 70,71,72,73
RES
•
CP All pins •f=1MHz
capacitance
unmeasured terminals.
•Ta=25°C
No.6688-14/23
LC86P5632
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Cycle tCKCY(1) 2
Low Level
tCKL(1) 1
SCK0,S CK1 Refer t o figure 5 4.5 to 6.0
pulse width
High Level
Input clock
pulse width
Cycle tCKCY(2) 2
Serial clock
Low Level
pulse width
High Level
Output clock
pulse width
Data set-up time
Data hold time
Serial input
Output delay time
(External clock
using for serial
transfer clock)
Output delay time
(Internal cloc k
Serial output
using for serial
tCKH(1)
SCK0,SCK1 •Use pull-up
tCKL(2) 1/2tCKCY
resistor (1kΩ) in
the open drain
tCKH(2)
output.
•Refer to figure 5
tICK 0.1
•SI0,SI1
•SB0,SB1
tCKI
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5
tCKO(1) 7/12
•SO0,SO1
•SB0,SB1
•Use pull-up
resistor (1kΩ) in
the open drain
output.
tCKO(2)
•Data hold from
SCK0,1
•Refer to figure 5
transfer clock)
Ratings
VDD[V] min. typ. max.
1
4.5 to 6.0
1/2tCKCY
4.5 to 6.0
0.1
4.5 to 6.0
tCYC
+0.2
1/3
tCYC
+0.2
unit
tCYC
µs
No.6688-15/23
LC86P5632
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
High/low le vel
pulse width
tPIH(1)
tPIL(1)
•INT0, INT1
•INT2/T0IN
•Interrupt acceptable
•Timer0-countable
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
unit
tCYC
•INT3
tPIH(2)
tPIL(2)
INT3
(The noise rejection clock
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0 2
selected to 1/1.)
tPIH(3)
tPIL(3)
INT3
(The noise rejection clock
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0 32
selected to 1/16.)
tPIL(4)
RES
Reset acceptable 4.5 to 6.0 200
µs
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS=0V
Parameter Symbol Pins Conditions
Ratings
VDD[V] min. typ. max.
unit
Resolution N 4.5 to 6.0 8 bit
Absolute precision
ET 4.5 to 6.0 ±1.5 LSB
(Note 2)
Conversion time tCAD
AD conversion time =
16 × tCYC
(ADCR2=0)
4.5 to 6.0
15.68
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
µs
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
(Note 3)
Analog input
VAIN 4.5 to 6.0 VSS VDD V
AN0 to AN7
voltage range
input current
IAINH VAIN=VDD 4.5 to 6.0 1 Analog port
IAINL
VAIN=VSS 4.5 to 6.0 -1
A
µ
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6688-16/23
LC86P5632
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 4)
IDDOP(1) •FmCF=6MHz
VDD
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDOP(2) •FmCF=1.5MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDOP(3) •FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
IDDOP(4)
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
Continue.
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 13 26
4.5 to 6.0 7 14
4.5 to 6.0 4 10
4.5 to 6.0 4 8
unit
mA
No.6688-17/23
LC86P5632
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 4)
IDDHALT(1) •HALT mode
•FmCF=6MHz
Ceramic resonator
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 5 10
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDHALT(2) •HALT mode
4.5 to 6.0 2.2 4.6
•FmCF=1.5MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
IDDHALT(3) •HALT mode
4.5 to 6.0 550 1000
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
IDDHALT(4)
•HALT mode
4.5 to 6.0 25 100
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
in HOLD mode
(Note 4)
IDDHOLD(1) 4.5 to 6.0 0.05 30 Current dissipation
IDDHOLD(2)
VDD HOLD mode
2.5 to 4.5 0.02 20
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
µA
No.6688-18/23
LC86P5632
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type Maker Oscillator C1 C2 Rf Rd
12MHz ceramic
resonator
oscillation
3MHz ceramic resonator
oscillation
Murata
Murata
CSA12.0MTZ 33pF 33pF OPEN
CSA12.0MTZ 39pF 30pF OPEN
CST12.0MTW on chip OPEN
CSA3.00MG040 100pF 100pF OPEN
CST3.00MGW040 on chip OPEN
560Ω
0Ω
560Ω
1.5Ω
1.5Ω
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type Maker Oscillator C3 C4
Kyocera KF-38G-13P0200 18pF 18pF 32.768kHz crystal
oscillation
Seiko Epson MC-306,C-002RX,32.768kHz 4pF 4pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
CF1 CF2
XT1 XT2
Rf
CF
Rd
X’tal
C2 C1
C4 C3
Figure 1 Main-clock circuit Figure 2 Sub-clock circuit
Ceramic oscillation circuit Crystal oscillation
No.6688-19/23
LC86P5632
Power supply
VDD
VDD limit
0V
RES
Reset time
Internal RC
resontor
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Reset Unfixed Instruction execution mode
<Reset time and oscillation stable time>
HOLD release signal
Valid
Internal RC
resontor
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3 Oscillation stable time
No.6688-20/23
LC86P5632
p
VDD
RES
R
RES
RES
C
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has be en over inferior limit of
supply voltage.
Figure 4 Reset circuit
<AC timing point>
0.5VDD
tCKCY
VDD
SCK0
SCK1
SI0
SI1
SO0, SO1
SB0, SB1
tCKL tCKH
tICK tCKI
tCKO
<Timing>
1KΩ
F
50
<Test load>
Figure 5 Serial input / output test condition
tPIL tPIH
Figure 6 Pulse input timing condition
No.6688-21/23
LC86P5632
Notice for use
The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for
•
Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening
procedure shown in the following figure should always be followed.
It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed.
•
Keeping the dry packing
•
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
• After openi ng th e packing
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on
the substrate. After opening the packing, a controlled environment must be maintained until soldering. The
environment must be held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 96
hours.
Unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the
board.
a. Shipping with a blank PROM (Programming the data by yourself)
Programming and verifying
Recommended process of screening
Reading ascertation of program
b. Shipping with a programmed PROM (Programming the data by Sanyo)
DIP
Programming and verifying
Recommended process of screening
Heat-soak
150±5°C, 24 Hr
+1
-0
Mounting
DIP QFP
Mounting Mounting
150±5°C, 24 Hr
Reading ascertation of program
QFP
Heat-soak
Mounting
+1
-0
No.6688-22/23
LC86P5632
No.6688-23/23
PS
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