Page 1
Ordering number : ENN*6749
CMOS IC
LC86E7248
8-Bit Single Chip Microcontroller
with the UVEPROM
Preliminary
Overview
The LC86E7248 is a CMOS 8-bit single chip microcontroller with UVEPROM for the LC867200 series. This
microcontroller has the function and the pin description of the LC867200 series mask ROM version, and 48K-byte EPROM.
The program data is rewritable. It is suitable to develop the program.
Features
(1) Option switching by EPROM data
The option function of the LC867200 series can be specified by the EPROM data.
LC86E7248 can be checked the functions of the trial pieces using the mass production board.
(2) Internal EPROM capacity : 49408 bytes
(3) Internal RAM capacity : 1152 bytes
Used EPROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86E7248.
Mask ROM version EPROM capacity RAM capacity
LC867248 49152 bytes 1152 bytes
LC867240 40960 bytes 1152 bytes
LC867232 32768 bytes 1152 bytes
LC867224 24576 bytes 1152 bytes
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 1µs to 366µs
(6) Operating temperature : +10°C to +40°C
(7) The pin compatible with the LC867200 series mask ROM devices
(8) Applicable mask ROM version : LC867248/40/32/24
(9) Factory shipment : QFC100S (with window)
Ver.1.02
80196
91400 RM (IM) SK No.6749-1/19
Page 2
LC86E7248
Notice for use
At using, take notice of the followings.
(1) A point of difference LC86E7248 and LC867200 series
Item LC86E7248 LC867248/40/32/24
Operation after reset
releasing
Operating supply
voltage range (VDD)
Operating temperature
range (Topr)
Power dessipat ion Refer to ‘electrical ch aracteristics’ on the semiconductor news.
The option is specified until 3ms after
going to a ‘H’ level to the reset
terminal by degrees. The program is
executed from 00H of the program
counter.
4.5V to 6.0V 2.5V to 6.0V
+10°C to +40°C -30°C to +70°C
LC86E7248 uses 256 bytes tha t is addr essed on 0F F00H t o FFFF H in the pro gram memory as the option configur ation d a ta
area. This option configuration cannot execute all options which LC867200 series have. Next tables show the options
that correspond and not correspond to LC86E7248.
• A kind of the option corresponding of the LC86E7248
A kind of option Pins, Circuits Contents of the option
Input/output form of
input/output ports
Pull-up MOS Tr. of
input port
Port 0
Port 1
*1
Port 3
*1
Ports 70, 71, 72, 73
*1
1. N-channel open drain output
2. CMOS output *1
1. Pull-up MOS Tr.
2. No Pull-up MOS Tr. *2
1. Input : Programmable pull-up MOS Tr.
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. Input : No Programmable pull-up MOS Tr.
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
*1) Specified in a bit.
*2) Specified in nibble unit. Pull-up MOS Tr. is not provided in N-channel open drain output port.
The port operation related the option is different at reset. Refer to the next table.
The program is executed from 00H of
the program counter i mmediately after
going to a ‘H’ level to the reset
terminal.
Output : N-channel open drain
Output : N-channel open drain
No.6749-2/19
Page 3
LC86E7248
(1) Option
The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE” .
(2) ROM space
LC86E7248 and LC8672 00 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Option
data area
Program area
48K bytes
LC867248 LC867240
Program area
40K bytes
Option
data area
Program area
32K bytes
LC867232
Option
data area
Program area
28K bytes
LC867224
No.6749-3/19
Page 4
LC86E7248
How to use
(1) Specification of option
Programming data for PROM of the LC86E7248 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HE X formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P6548.
(2) How to program for the EPROM
The LC86E7248 can be programmed by EPROM programmer with attachment ; W86EP7248Q
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL1890A
• “27512 (Vpp=12.5V) Intel high speed pro gramming” mode available. Th e addre ss must be set to “0 to 0FFFFH ” and a
jumper (DASEC) must be set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK=>PROGRAM=>VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
(4) How to eliminate
The programming data can be erased by using the EPROM eraser.
(5) Shielding
The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use.
Data security
W86EP7248Q
Not data security
No.6749-4/19
Page 5
Pin Assi gnment
N
N
V2/PL5
V1/PL4
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30
P31
VSS3
VDD3
P32
P33
P34
P35
P00
P01
P02
P03
P04
P05
LC86E7248
V3/PL6
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
VSS2
8079787776757473727170696867666564636261605958575655545352
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2 3 4 5 6 7 8 9
P06
P07
P10/SO0
P13/SO1
P12/SCK0
P11/SI0/SB0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P74
RES
P16/BUZ
P70/INT0
P15/SCK1
P17/PWM0
P14/SI1/SB1
CF1
CF2
VSS1
XT1/
XT2/P75
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
VDD2
25
P86/AN6
S25/PD1
26
P87/AN7
S24/PD0
27
P71/INT1
S23/PC7
28
P72/INT2/T0I
S22/PC6
29
P73/INT3/T0I
S21/PC5
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
S0/PA0
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
SANYO : QFC100S
No.6749-5/19
Page 6
System Bl ock Diagram
Interrupt Control
Stand-by C ontr ol
CF
LC86E7248
IR PLA
EPROM
Control
A15-A0
D7-D0
TA
CE
OE
DASEC
RC
X’tal
Base Timer Bus Interface
SIO0
SIO1
Timer 0
Timer 1
Real Time Service
RAM 128 bytes
Clock
Generator
INT0-3 Noise
Rejection Filter
Port 1
Port 7
Port 8
Port 3
ADC
EPROM (48KB)
PC
ACC
B Register
C Register
ALU
PSW
RAR
LCD Display
Controller
SO0 - S7 (PA)
S8 - S13 (PB)
S16 - S23 (PC)
S24 - S31 (PD)
S32 - S39 (PE)
S40 - S47 (PF)
COM0-COM3(PL)
RAM
Stack Pointer
Port 0
Watchdog T i mer
No.6749-6/19
Page 7
LC86E7248
Pin Description
Pin name I/O Function description Option PROM mode
VSS1, 2, 3
*1
VDD1, 2, 3
*1
PORT0
P00 - P07
PORT1
P10 - P17
PORT3
P30 - P35
PORT7
P70
P71 - P73
P74
Port8
P80 – P87
I/O • 8-bit input/output port
I/O • 8-bit input/output port
I/O • 6-bit input/output port
I/O
, P75
- Power pin (–) - -
- Power pin (+) - -
Input/output in nibble units
• Input for port 0 interrupt
• Input for HOLD release
Input/output can be specified in bit unit
• Other pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus input/output
P12 : SIO0 clock input/output
P13 : SIO1 data output
P14 : SIO1 data input/bus input/output
P15 : SIO1 clock input/output
P16 : Buzzer output
P17 : Timer1 output (PWM output)
• Input/output can be specified in bit unit
• 6-bit input port
• Other pin functions
P70 : INT0 input/HOLD release input/
N-ch Tr. output for watchdog timer
I
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
• Interrupt recei ved form, vector address
rising falling rising
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
I
I • 8-bit input port
: XT1 terminal for crystal oscillation
P74
P75 : XT2 terminal for crystal oscillation
• Other func tion
AD input port (8 port pins)
falling
&
high
level
low
level
• Pull-up resistor :
Provided/Not provided
(specified in nibble units)
• Output form (P00 – P07) :
CMOS/N-channel open drain
(specified in a bit)
• Output form :
CMOS/N-channel open drain
(specified in a bit)
• Output form :
CMOS/N-channel open drain
(specified in a bit)
Pull-up resistor :
Provided/Not provided
(specified in a bit)
(P70, P71, P72, P73)
, P75 don’t have the pull-up
*
P74
resistor option.
vector
- -
-
Data line
D0 to D7
-
Power for
programming
PROM control
signals
DASEC (*2)
OE
CE
(*3)
(*4)
No.6749-7/19
Page 8
LC86E7248
Pin name I/O Function description Option PROM mode
Port A
(S0/PA0 –
S7/PA7)
Port B
(S8/PB0 –
S15/PB7)
Port C
(S16/PC0 –
S23/PC7)
Port D
(S24/PD0 –
S31/PD7)
Port E
(S32/PE0 –
S39/PE7)
Port F
(S40/PF0 –
S47/PF7)
Port L
(COM0/PL0
–
COM3/PL3)
V1/PL4 –
V3/PL6
RES
I Reset pin - -
XT1/
P74
XT2/P75 O
CF1 I Input pin for ceramic resonator
CF2 O Output pin for ceramic resonator
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Segment output terminal for LCD display
• Can be used as a general input/output
port
I/O • Common output terminal for LCD display
• Can be used as a general input port
I • Bias power terminal for LCD drive
• Can be used as a general input port
I • Input pin for 32.768kHz crystal
oscillation
In case of non use, connect to VDD.
• Other func tion
A general input port
• Output pin for 32.768kHz crystal
oscillation
In case of non use, should be left
unconnected
(I)
• Other func tion
A general input port P75
oscillation
oscillation
P74
- Address input
A0 to A7
- Address input
A8 to A13
- PROM control
signal input
• TA (*5)
Address input
• A14, A15
- -
- -
- -
- -
- -
- -
- -
- -
- -
* All of port options can be specified in a bit unit except the pull-up resistor of port 0.
[Notes] • The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other.
• The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
*2 Memory select input for data security
*3 Output enable input
*4 Chip enable input
*5 TA ! PROM control signal input
Power
Supply
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.6749-8/19
Page 9
LC86E7248
1. Absolute Maximum Ratings at Ta=25°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD1, VDD2
VDD3
LCD display
voltage
Input voltage VI •Ports 71, 72, 73
Input/output
voltage
High
level
output
current
Low
level
output
current
Maximum power
dissipation
Operating
temperature
range
Storage
temperature
range
output
current
Total
output
current
Peak
output
current
Total
output
current
VLCD V1/PL6, V2/PL5
V3/PL4
•Ports
•Port 8, Port L
RES
•
VIO •Port 0, 1, 3
•Port 70
•Ports A,B,C,D,E,F
IOPH(1) Ports 0, 1, 3 -4 Peak
IOPH(2) Ports A,B,C,D,E,F
Σ
IOAH(1) Ports 0, 1, 32, 33,
34, 35
Σ
IOAH(2) Ports 30, 31 Total all pins -4
Σ
IOAH(3) Ports S0 to S25 Total all pins -25
Σ
IOAH(4) Ports S26 to S47 Total all pins -25
IOPL(1) Ports 0, 1, 3 At each pi ns 20
IOPL(2) Ports A,B,C,D,E,F At each pins 20
IOPL(3) Port 70 At each pins 15
Σ
IOAL(1) Ports 0, 1, 32, 33,
34, 35
Σ
IOAL(2) Ports 30, 31 Total all pins 20
Σ
IOAL(3) Ports S0 to S25 Total all pins 39
Σ
IOAL(4) Ports S26 to S47 Total all pins 33
Σ
IOAL(5) Port 70 Total all pins 10
Pdmax QFC100S Ta=+10 to+40°C 515
Topr +10 +40
Tstg -55 +125
, 75
74
VDD1=VDD2=
VDD3
VDD1=VDD2=
VDD3
-0.3 VDD+0.3
-0.3 VDD+0.3
•CMOS output
•At each pins
Total all pins -38
Total all pins 50
Ratings
[V]
min. typ. max.
VDD
-0.3 +7.0
-0.3 VDD
-4
unit
V
mA
mW
°
C
No.6749-9/19
Page 10
LC86E7248
2. Recommended Operating Range at Ta=+10°C to +40°C, VSS =0V
Parameter Symbol Pins Conditions
Operating
supply voltage
range
Hold voltage VHD VDD1, VDD2, VDD3 RAMs and the registers
Input high
voltage
Input low
voltage
cycle time
Oscillation
frequency
range
(Note 1)
Oscillation
stabilizing
time period
(Note 1)
VDD(1) 0.98µs ≤ tCYC
VDD(2)
VIH(1) Port 0 Output disable 4.5-6.0 0.4VDD
VIH(2) •Ports 1, 3
VIH(3) •Port 70
VIH(4) Port 70
VIH(5) •Port 8 Output N-channel
VIL(1) Port 0 Output disable 4.5-6.0 VSS 0.2VDD
VIL(2) •Ports 1, 3
VIL(3) •Port 70
VIL(4) Port 70
VIL(5) •Port 8 Output N-channel
tCYC
FmCF(1) CF1, CF2 •6MHz (ceramic
FmCF(2) CF1, CF2 •3MHz (ceramic
FmRC RC oscillation 4.5-6.0 0.4 0.8 3.0
FsXtal XT1, XT2 •32.768kHz (cry st al
tmsCF(1) CF1, CF2 •6MHz (ceramic
tmsCF(2) CF1, CF2 •3MHz (ceramic
tssXtal XT1, XT2 •32.768kHz (crystal
VDD1, VDD2, VDD3
•Ports A,B,C,D,E,F,L
•Ports 72, 73
Port input/interrupt
•Port 71
RES
•
Watchdog timer
•Ports A,B,C,D,E,F,L
•Ports 72, 73
Port input/interrupt
•Port 71
RES
•
Watchdog timer
≤
400µs
3.9µs ≤ tCYC
≤
400µs
hold voltage at HOLD
mode.
Output disable 4.5-6.0 0.75VDD VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Tr. OFF
Output disable 4.5-6.0 VSS 0.25VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Tr. OFF
resonator oscillation)
•Refer to figure 1
resonator oscillation)
•Refer to figure 1
oscillation)
•Refer to figure 2
resonator oscillation)
•Refer to figure 3
resonator oscillation)
•Refer to figure 3
oscillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5 6.0
2.5 6.0
2.0 6.0
VDD
+0.9
4.5-6.0 0.75VDD VDD
4.5-6.0 0.9VDD VDD
4.5-6.0 0.75VDD VDD
4.5-6.0 VSS 0.25VDD
4.5-6.0 VSS 0.8VDD
-1.0
4.5-6.0 VSS 0.25VDD
4.5-6.0 0.98 400 Operation
4.5-6.0 3.9 400
4.5-6.0 6
4.5-6.0 3
4.5-6.0 32.768 kHz
4.5-6.0
4.5-6.0
4.5-6.0 s
unit
V
µ
s
MHz
ms
No.6749-10/19
Page 11
LC86E7248
3. Electrical Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Input high
current
Input low
current
voltage
Output low
voltage
IIH(1) •Port 1
•Port 0 without
pull-up MOS Tr.
IIH(2) •Port 7 without
pull-up MOS Tr.
•Port 8
IIH(3) Port 3 VIN=VDD 4.5-6.0 1
IIH(4) Ports A,B,C,D,E,F,L VIN=VDD 4.5-6.0 1
IIH(5)
IIH(6) Ports
IIL(1) •Port 1
IIL(2) •Port 7 without
IIL(3) Port 3 VIN=VSS 4.5-6.0 -1
IIL(4) Ports A,B,C,D,E,F,L VIN=VSS 4.5-6.0 -1
IIL(5)
IIL(6) Ports
VOH(1) Ports 0,1 of
VOH(2) •Port 3 of CMOS
VOL(1) IOL=10mA 4.5-6.0 1.5
VOL(2)
VOL(3) Port 70 IOL=1mA 4.5-6.0 0.4
VOL(4) IOL=10mA 4.5-6.0 1.5
VOL(5)
VOL(6) IOL=8mA 4.5-6.0 1.5
VOL(7)
VIN=VDD 4.5-6.0 1
RES
74
,75 Using as port
•Port 0 without
pull-up MOS Tr.
pull-up MOS Tr.
•Port 8
RES
VIN=VSS 4.5-6.0 -1
,75 Using as port
74
CMOS output
output
•Ports A,B,C,D,E,F
of CMOS output
Ports 0, 1
Port 3
Ports A,B,C,D,E,F
of CMOS output
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VDD
(incl uding the off leak current of the
output Tr.)
VIN=VDD 4.5-6.0 1
VIN=VDD
•Output disable
•Pull-up MOS Tr.
OFF. VIN=VSS
(incl uding the off leak current of the
output Tr.)
VIN=VSS 4.5-6.0 -1
VIN=VSS
IOH=-1.0mA 4.5-6.0 VDD-1 Output high
IOH=-1.0mA 4.5-6.0 VDD-1
IOL=1.6mA 4.5-6.0 0.4
IOL=1.6mA 4.5-6.0 0.4
IOL=1.6mA 4.5-6.0 0.4
Ratings
VDD[V] min. typ. max.
4.5-6.0 1
4.5-6.0 1
4.5-6.0 -1
4.5-6.0 -1
Continue.
unit
µ
A
V
No.6749-11/19
Page 12
LC86E7248
Parameter Symbol Pins Conditions
VODLS S0 to S47 •Deferen ce voltage
regulation
VODLC COM0 to COM3 •Deferen ce voltage
RLCD(1) Resistance at a
resistor
RLCD(2) •Resistance at a
Pull-up MOS
Tr. resistor
Hysteresis
voltage
Pin capacitance CP All pins •f=1MHz
Rpu •Ports 0, 1, 3
•Ports A,B,C,D,E,F
•Ports 70, 71, 72, 73
VHIS •Port 1
•Ports 70, 71, 72, 73
•
RES
to ideal value
•VLCD, 2/3VLCD,
1/3VLCD
to ideal value
•VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
ladder resisto r
ladder resistor
•1/2R mode
VOH=0.9VDD 4.5-6.0 15 40 70
Output disable 4.5-6.0 0.1VDD V
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
4.5-6.0 0 ±0.2 LCD output
4.5-6.0 0 ±0.2
4.5-6.0 60 LCD ladder
4.5-6.0 30
4.5-6.0 10 pF
4. Serial Input / Output Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Cycle tCKCY(1) 2
Low Level
pulse width
High Level
Input clock
pulse width
Cycle tCKCY(2) 2
Serial clock
Serial input
Serial output
Low Level
pulse width
High Level
Output clock
pulse width
Data set up ti me
Data hold time
Output delay time
(Serial clock is
external clock)
Output delay time
(Serial clock is
internal clock)
tCKL(1) 1
tCKH(1)
tCKL(2) 1/2
tCKH(2)
tICK 4.5-6.0 0.1
tCKI
tCKO(1) 4.5-6.0 7/12tCYC
tCKO(2)
SCK0,
SCK1
SCK0,
SCK1
•SI0,SI1
•SB0,SB1
•SO0, SO1
•SB0, SB1
Refer to figure 5. 4.5-6.0
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Refer to figure 5.
•Data set-up to
SCK0, 1
•Data hold from
SCK0, 1
•Refer to figure 5.
•Use pull-up
resistor (1kΩ)
when open drain
output.
•Data hold from
SCK0, 1
•Refer to figure 5.
Ratings
VDD[V] min. typ. max.
1
4.5-6.0
1/2
4.5-6.0 0.1
4.5-6.0 1/3tCYC
tCKCY
tCKCY
+0.2
+0.2
unit
V
kΩ
unit
tCYC
µ
s
No.6749-12/19
Page 13
LC86E7248
5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
High/low level
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection
clock is selected to 1/1.)
INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
RES
Reset acceptable 4.5-6.0 200
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
Ratings
VDD[V] min. typ. max.
4.5-6.0 1
4.5-6.0 2
4.5-6.0 32
4.5-6.0 128
unit
tCYC
µ
s
6. AD Converter Characteristics at Ta=+10°C to + 40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Resolution NAD 4.5-6.0 8 bit
Absolute precision
(Note 2)
Conversion time tCAD
Analog input
voltage range
input current
ETAD 4.5-6.0 ±1.5 LSB
AD conversion time = 16
×
tCYC
(ADCR2=0)
(Note 3)
AD conversion time = 32
×
tCYC
(ADCR2=1)
(Note 3)
VAIN 4.5-6.0 VSS VDD V
IAINH VAIN=VDD 4.5-6.0 1 Analog port
IAINL
AN0 - AN7
VAIN=VSS 4.5-6.0 -1
Ratings
VDD[V] min. typ. max.
4.5-6.0
15.68
(tCYC=
0.98µs)
31.36
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
130.56
(tCYC=
4.08µs)
unit
µ
s
µ
A
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6749-13/19
Page 14
LC86E7248
7. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 4)
IDDOP(1) •FmCF=6MHz
IDDOP(2) •FmCF=3MHz
IDDOP(3) •FmCF=0Hz
IDDOP(4)
VDD1=
VDD2=
VDD3
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Ratings
VDD[V] min. typ. max.
4.5-6.0 15 30
4.5-6.0 6 15
4.5-6.0 4 13
4.5-6.0 4 9
Continue.
unit
mA
No.6749-14/19
Page 15
LC86E7248
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 4)
Current dissipation
in HOLD mode
(Note 4)
IDDHALT(1) •HALT mode
IDDHALT(2) •HALT mode
IDDHALT(3) •HALT mode
IDDHALT(4)
IDDHALT(5)
IDDHOLD(1) VDD1=
VDD1=
VDD2=
VDD3
VDD2=
VDD3
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•HALT mode
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
HOLD mode
Ratings
VDD[V] min. typ. max.
4.5-6.0 6 11
4.5-6.0 2.2 9
4.5-6.0 500 1700
4.5-6.0 25 100
4.5-6.0 0.05 30
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
µ
A
No.6749-15/19
Page 16
LC86E7248
Table 1. Ceramic resonator oscillation guaranteed constant (main clock)
Oscillation type Maker Oscillator C1 C2
6MHz ceramic resonator
oscillation
3MHz ceramic resonator
oscillation
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type Maker Oscillator C3 C4 Rd
32.768kHz crystal
oscillation
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1 CF2
XT1 XT2
Rd
CF
C2 C1
X’tal
C4 C3
Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit
No.6749-16/19
Page 17
LC86E7248
y
Power suppl
RES
Reset time
VDD
VDD limit
0V
tmsCF
Internal RC
resonator oscillation
CF1, CF2
XT1, XT2
tssXtal
Instruction
Operation mode
Unfixed Reset Instruction execution mode
execution mode
OCR6=1
< Reset time and oscillation stable time >
HOLD release signal
Valid
Internal RC
resonator oscillation
CF1, CF2
XT1, XT2
tmsCF
tssXtal
Operation mode
HOLD Instruction execution mode
< HOLD release signal and oscilla tion s table time >
Figure 3 Oscillation stable time
No.6749-17/19
Page 18
LC86E7248
,
VDD
RES
R
RES
(Note) Fix the value of C
RES
, R
RES
that is
sure to reset until 200µs, after Power
supply has be en over inferior limit of
RES
C
supply voltage.
Figure 4 Reset circuit
<AC timing point>
0.5VDD
tCKCY
VDD
SCK0
SCK1
SI0
SI1
SO0, SO1
SB0
SB1
tCKL tCKH
tICK tCKI
tCKO
<Timing>
1kΩ
50pF
<Test load>
Figure 5 Serial input / output test condition
tPIL tPIH
Figure 6 Pulse input timing condition
No.6749-18/19
Page 19
LC86E7248
No.6749-19/19
PS
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