Page 1
Ordering number : ENN*6748
CMOS IC
LC86E7148
8-Bit Single Chip Microcontroller
with the UVEPROM
Preliminary
Overview
The LC86E7148 is a CMOS 8-bit single chip microcontroller with UVEPROM for the LC867100 series. This
microcontroller has the function and the pin description of the LC867100 series mask ROM version, and 48K-byte EPROM.
The program data is rewritable. It is suitable to develop the program.
Features
(1) Option switching by EPROM data
The option function of the LC867100 series can be specified by the EPROM data.
LC86E7148 can be checked the functions of the trial pieces using the mass production board.
(2) Internal EPROM capacity : 49152 bytes
(3) Internal RAM capacity : 1152 bytes
Used EPROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86E7148.
Mask ROM version EPROM capacity RAM capacity
LC867148 49152 bytes 1152 bytes
LC867140 40960 bytes 1152 bytes
LC867132 32768 bytes 768 bytes
LC867128 28672 bytes 768 bytes
LC867124 24576 bytes 768 bytes
LC867120 20480 bytes 640 bytes
LC867116 16384 bytes 640 bytes
LC867112 12288 bytes 512 bytes
LC867108 8192 bytes 512 bytes
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 1µs to 366µs
(6) Operating temperature : +10°C to +40°C
(7) The pin compatible with the LC867100 series mask ROM devices
(8) Applicable mask ROM version : LC867148/LC867140/LC867132/LC8671 28/LC867124/LC867120
/LC867116/LC867112/LC867108
(9) Factory shipment : QIC80S
Ver.1.01A
D1694
91400 RM (IM) HK No.6748-1/20
Page 2
LC86E7148
Notice for use
At using, take notice of the followings.
(1) A point of difference LC86E7148 and LC867100 series
Item LC86E7148 LC867148/40/32/28/24/20/16/12/08
Port form at reset Please refer ‘Port form at reset’ on next page.
Operation after reset
releasing
Operating supply
voltage range (VDD)
Total output current
[∑IOAL(2)]
[∑IOAL(3)]
Power dessipation
LC86E7148 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data
area. This option configuration can execute all options which LC867100 series have. Next tables show the options that
correspond and not correspond to LC86E7148.
• A kind of the option corresponding of the LC86E7148
A kind of option Pins, Circuits Contents of the option
Input/output form of
input/output ports
Pull-up MOS Tr. of
input port
*1) Specified in a bit.
*2) Specified in nibble unit. Pull-up MOS Tr. is not provided in N-channel open drain output port.
The port operation related the option is different at reset. Refer to the next table.
The option is specified until 3ms after
going to a ‘H’ level to the reset terminal
by degrees. The program is executed from
00H of the program counter.
4.5V to 6.0V 2.5V to 6.0V
Refer to ‘electrical characteristics’ on the semiconductor news.
Port 0
(specified in a bit)
Port 1
(specified in a bit)
*1
Port 7
(specified in a bit) *1
Each of P74 and P75 has no
option
1. Input : No Pull-up MOS Tr.
Output : N-channel open drain *1
2. Input : Pull-up MOS Tr.
Output : CMOS *2
1. Input : Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. No Pull-up MOS Tr.
2. Pull-up MOS Tr.
The program is executed from 00H of the
program counter immediately after going
to a ‘H’ level to the reset terminal.
No.6748-2/20
Page 3
LC86E7148
(2) Option
The option data is created by the option specified program “SU86K.EXE”. The created option data is linked to the
program area by linkage loader “L86K.EXE”.
(3) ROM space
LC86E7148 and LC867100 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
Option data
area 256 bytes
Program area
48K bytes
LC867148 LC867140
Option data
area 256 bytes
Program area
20K bytes
LC867120 LC867116
Option
Data Area
Program area
40K bytes
Option
Data Area
Program area
16K bytes
Option
Data Area
Program area
32K bytes
LC867132
Option
Data Area
Program area
12K bytes
LC867112
Option
Data Area
Program area
28K bytes
LC867128
Option
Data Area
Program area
8K bytes
LC867108
Option
Data Area
Program area
24K bytes
LC867124
No.6748-3/20
Page 4
LC86E7148
How to use
(1) Specification of option
The LC86E7148 must be programmed after specifying option data. The option is specified by “SU86K.EXE”. The
specified option file and the file created by our macro assembler “M86K.EXE” are linked by our linkage loader
“L86K.EXE” which creates .HE X file, then the option code is put i n the option specified area ( 0FF00H to 0FFFFH) of
its .HEX file.
(2) How to program for the EPROM
The LC86E7148 can be programmed by EPROM programmer with attachment ; W86EP7148Q
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. T he address must be set to “0 to 0FFFFH” and a
jumper (DASEC) must be set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FFH’ at the sequence 2 above.
• The programming by a sequential operation “BLANK=>PROGRAM=>VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the d ata security.
(4) How to eliminate
The programming data can be erased by using the EPROM eraser.
(5) Shielding
The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use.
Data security
Not data security
W86EP7148Q
No.6748-4/20
Page 5
Pin Assignment
COM1/PL1
COM2/PL2
COM3/PL3
VSS2
VDD2
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
COM0/PL0
V1/PL4
V2/PL5
V3/PL6
S31/PD7
S30/PD6
64
63
62
61
60
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9
P13/SO1
P14/SI1/SB1
59
P16/BUZ
P70/INT0
P15/SCK1
P17/PWM0
S29/PD5
58
RES
S28/PD4
57
XT1/P74
S27/PD3
56
XT2/P75
S26/PD2
55
10
VSS1
S25/PD1
54
11
CF1
LC86E7148
S24/PD0
S23/PC7
S22/PC6
S21/PC5
53
52
51
50
12
13
14
15
CF2
VDD1
P80/AN0
P81/AN1
S20/PC4
49
16
P82/AN2
S19/PC3
48
17
P83/AN3
S18/PC2
47
18
P84/AN4
S17/PC1
46
19
P85/AN5
S16/PC0
45
20
P86/AN6
S13/PB5
44
21
P87/AN7
S12/PB4
43
22
P90/DA0
VSS3
42
23
P91/DA1
VDD3
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
P92/DA2
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
S0/PA0
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P93/DA3
No.6748-5/20
Page 6
System Bl ock Diagram
y
SIO0
SIO1
Timer 0
Timer 1
Real Time Service
RAM
128 b
tes
LCD
Controller
S0 – S7 (PA)
S8 – S13 (PB)
S16 – S23 (PC)
S24 – S31 (PD)
COM0 – COM3(PL)
Interrupt Control
Stand-by C ontr ol
CF
RC
X’tal
Clock
Generator
Bus Interface Base Timer
LC86E7148
Port 1
Port 7
Port 8
Port 9
ADC
INT0 - 3
Nose Filter
DAC
IR
EPROM
Control
EPROM(48KB)
PC
ACC
B Register
C Register
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog T i mer
PLA
ALU
A15-A0
D7-D0
TA
CE
OE
DASEC
No.6748-6/20
Page 7
LC86E7148
Pin Description
Pin name I/O Function description Option PROM mode
VSS1 *1 - Power pin (–) -
VSS2 *1 - Power pin (–) -
VSS3 *1 - Power pin (–) -
VDD1 *1 - Power pin (+) -
VDD2 *1 - Po wer pin (+) -
VDD3 *1 - Po wer pin (+) -
PORT0
P00 - P07
I/O • 8-bit input/output port
Input/output in nibble units
• Input for port 0 interrupt
• Input for HOLD release
• Pull-up resistor :
Provided/Not provided
(specified in nibble units)
• Output form (P00 – P07) :
CMOS/N-channel open drain
(specified in a bit)
PORT1
P10 - P17
I/O • 8-bit input/output port
Input/output can be specified in bit unit
• Other pin functi ons
• Output form :
CMOS/N-channel open drain
(specified in a bit)
Data line
D0 to D7
P10 SIO0 data output
P11 SIO0 d ata input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 d ata input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer1 output (PWM output)
PORT7
P70
P71 - P73
P74
- P75
• 6-bit input port
• Other pin functi ons
P70 : INT0 input/HOLD release input/
I/O
N-channel Tr. output for watchdog timer
P71 : INT1 input/HOLD release input
I
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
• Interrupt received form, vector address
rising falling rising
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
I
P74
: XT1 terminal for crystal oscillation
falling
&
high
level
Pull-up resistor :
Provided/Not provided
(specified in a bit)
(P70, P71, P72 , P73)
P74
, P75 don’t have the pull-up
*
resistor option.
low
vector
level
Power for
programming
PROM control
signals
DASEC(*2)
(*3)
OE
(*4)
CE
P75 : XT2 terminal for crystal oscillation
Port8
P80 – P87
I • 8-bit input port
• Other function
-
AD input port (8 port pins)
PORT9
P90 - P93
I/O • 4-bit input/output port
• Other function
-
DA output port (4 port pins)
AD input port (4 port pins)
No.6748-7/20
Page 8
LC86E7148
Pin name I/O Function description Option PROM mode
PORT A
(S0/PA0 –
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
- Address input
A0 to A7
S7/PA7)
PORT B
(S8/PB0 –
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
- Address input
A8 to A13
S13/PB5)
PORT C
(S16/PC0 –
S23/PC7)
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
- PROM control
signal input
•TA(*5)
Address input
•A14,A15
PORT D
(S24/PD0 –
I/O • Segment output terminal for LCD display
• Can be used as a general input/output port
-
S31/PD7)
PORT L
(COM0/PL0 –
I/O • Common output terminal for LCD display
• Can be used as a general input port
-
COM3/PL3)
V1/PL4 –
V3/PL6
RES
XT1/
P74
I • Bias power terminal for LCD drive
-
• Can be used as a general input port
I Reset pin -
I • Input pin for 32.768kHz crystal oscillation
-
In case of non use, connect to VDD.
• Other function
P74
A general input port
XT2/P75 O
• Output pin for 32.768kHz crystal oscillation
In case of non use, should be left unconnected
( I )
• Other function
-
A general input port P75
CF1 I Input pin for ceramic resonator oscillation -
CF2 O Output pin for ceramic resonator oscillation -
* All of port options can be specified in bit unit except the pull-up resistor of port 0.
[Notes] • The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other.
• The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other.
*1 Connect like the following figure to reduce noise into a VDD terminals.
Power
Supply
LSI
VDD1
VDD2
VDD3
VSS1 VSaS2
VSS3
*2 Memory select input for data security
*3 Output enable input
*4 Chip enable input
*5 TA ! PROM contro l signal input
No.6748-8/20
Page 9
LC86E7148
V
1. Absolute Maximum Ratings at Ta=25°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD1, VDD2
VDD3
LCD display
voltage
VLCD V1/PL6, V2/PL5
V3/PL4
Input voltage VI •Ports 71, 72, 73
•Ports
74
, 75
VDD1=VDD2=
VDD3
VDD1=VDD2=
VDD3
-0.3 VDD+0.3
•Port 8, Port L
RES
•
Input/output
voltage
VIO •Ports 0, 1
•Port 9
-0.3 VDD+0.3
•Ports A, B, C, D
High
level
output
current
Peak
output
current
Total
output
current
Low
level
output
Peak
output
current
current
Total
output
current
Maximum powe r
IOPH(1) Ports 0, 1 -4
IOPH(2) Ports A, B, C, D -4
•CMOS output
•At each pins
IOPH(3) Port 9
IOAH(1)
Σ
ΣIOAH(2)
IOAH(3)
Σ
ΣIOAH(4)
Ports 0, 1 Total all pins -30
Ports A, B Total all pins -20
Ports C, D Total all pins -20
Port 9 T otal all pins -20
IOPL(1) Ports 0, 1 At each pins 20
IOPL(2) Ports A, B, C, D At each pins 20
IOPL(3) Port 9 At each pins 20
IOPL(4) Port 70 At each pins 15
IOAL(1)
Σ
ΣIOAL(2)
IOAL(3)
Σ
ΣIOAL(4)
IOAL(5)
Σ
Pdmax QIC80S
Ports 0, 1 Total all pins 40
Ports A, B Total all pins 24
Ports C, D Total all pins 24
Port 9 T otal all pins 15
Port 70 Total all pins 10
Ta=+10 to+40°C
dissipation
Operating
Topr +10 +40
temperature
range
Storage
Tstg -65 +150
temperature
range
Notes •The QFP packages should be heat-soaked for 12 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
•After pre-baking a controlled environment must be maintained until soldering. T he environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 24 hours.
Ratings
DD[V] min. typ. max.
-0.3 +7.0
-0.3 VDD
-4
515
unit
V
mA
mW
C
°
No.6748-9/20
Page 10
LC86E7148
2. Recommended Operating Range at Ta=+10°C to +40°C, VSS=0V
Parameter Symbol Pins Conditions
VDD(1)
supply voltage
range
VDD(2)
Hold voltage VHD VDD1, VDD2,VDD3 RAMs and the
Input high
VIH(1) Port 0 Output disable 4.5-6.0 0.4VDD
voltage
VIH(2) •Ports 1, 9
VIH(3) •Port 70
VIH(4) Port 70
VIH(5) •Port 8 Output N-channel
Input low
voltage
VIL(1) Port 0 Output disable 4.5-6.0 VSS 0.2VDD
VIL(2) •Ports 1, 9
VIL(3) •Port 70
VIL(4) Port 70
VIL(5) •Port 8 Output N-channel
tCYC
cycle time
VDD1,VDD2,VDD3
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
Port input/interrupt
•Port 71
RES
•
(Schmitt)
Watchdog timer
•Ports A, B, C, D
•Ports 72, 73 (Schmitt)
Port input/interrupt
•Port 71
RES
•
(Schmitt)
Watchdog timer
0.98µs ≤ tCYC
≤ 400µs
3.9µs ≤ tCYC
≤ 400µs
registers hold
voltage at HOLD
mode.
Output disable 4.5-6.0 0.75VDD VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Tr. OFF
Output disable 4.5-6.0 VSS 0.25VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Tr. OFF
Ratings
VDD[V] min. typ. max.
4.5 6.0 Operating
2.5 6.0
2.0 6.0
VDD
+0.9
4.5-6.0 0.75VDD VDD
4.5-6.0 0.9VDD VDD
4.5-6.0 0.75VDD VDD
4.5-6.0 VSS 0.25VDD
4.5-6.0 VSS 0.8VDD
-1.0
4.5-6.0 VSS 0.25VDD
4.5-6.0 0.98 400 Operation
4.5-6.0 3.9 400
unit
V
s
µ
No.6748-10/20
Page 11
LC86E7148
Parameter Symbol Pins Conditions
Oscillation
frequency
range
(Note 1)
FmCF(1) CF1, CF2 •6MHz (ceramic
resonator oscillation)
•Refer to figure 1
FmCF(2) CF1, CF2 •3MHz (ceramic
resonator oscillation)
•Refer to figure 1
FmRC RC oscillation 4.5-6.0 0.4 0.8 3.0
FsXtal XT1, XT2 •32.768kHz
(crystal oscillation)
•Refer to figure 2
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tmsCF(2) CF1, CF2 •3MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kHz
(crystal oscillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5-6.0 5.88 6 6.12
unit
MHz
4.5-6.0 2.94 3 3.06
4.5-6.0 32.768 kHz
4.5-6.0
ms
4.5-6.0
4.5-6.0 s
No.6748-11/20
Page 12
LC86E7148
3. Electrical Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Input high
current
IIH(1) •Port 1
•Port 0 without
pull-up MOS Tr.
•Output disa ble
•Pull-up MOS Tr.
OFF. VIN=VDD
(including the off leak current of the
output Tr.)
IIH(2) •Port 7 without
VIN=VDD 4.5-6.0 1
pull-up MOS Tr.
•Por t 8
IIH(3) Port 9 VIN=VDD 4.5-6.0 1
IIH(4) Ports A, B, C, D, L VIN=VDD 4.5-6.0 1
IIH(5)
IIH(6)
RES
Ports
74
,75
VIN=VDD 4.5-6.0 1
Using as port
VIN=VDD
Input low
current
IIL(1) •Port 1
•Port 0 without
pull-up MOS Tr.
•Output disa ble
•Pull-up MOS Tr.
OFF. VIN=VSS
(including the off-
leak current of the
output Tr.)
IIL(2) •Port 7 without
VIN=VSS 4.5-6.0 -1
pull-up MOS Tr.
•Por t 8
IIL(3) Port 9 VIN=VSS 4.5-6.0 -1
IIL(4) P orts A, B, C, D, L VIN=VSS 4.5-6.0 -1
IIL(5)
IIL(6)
RES
Ports
74
,75
VIN=VSS 4.5-6.0 -1
Using as port
VIN=VSS
voltage
VOH(1) Ports 0,1 of
CMOS output
VOH(2) •Port 9 of CMOS
IOH=-1.0mA 4.5-6.0 VDD-1 Output high
IOH=-1.0mA 4.5-6.0 VDD-1
output
•Ports A, B, C, D
of CMOS output
Output low
voltage
VOL(1) IOL=10mA 4.5-6.0 1.5
VOL(2)
Ports 0, 1
IOL=1.6mA 4.5-6.0 0.4
VOL(3) Port 70 IOL=1mA 4.5-6.0 0.4
VOL(4) IOL=6mA 4.5-6.0 1.5
VOL(5)
VOL(6) IOL=8mA 4.5-6.0 1.5
VOL(7)
Port 9
Ports A, B, C, D
of CMOS output
IOL=1.2mA 4.5-6.0 0.4
IOL=1.6mA 4.5-6.0 0.4
Continue.
Ratings
VDD[V] min. typ. max.
4.5-6.0 1
4.5-6.0 1
4.5-6.0 -1
4.5-6.0 -1
unit
µA
V
No.6748-12/20
Page 13
LC86E7148
Parameter Symbol Pins Conditions
regulation
VODLS S0 to S13,
S16 to S31
•Deference voltage
to ideal value
Ratings
VDD[V] min. typ. max.
4.5-6.0 0 ±0.2 LCD output
•VLC D, 2/3VLCD ,
1/3VLCD
VODLC COM0 to COM3 •Deference voltage
4.5-6.0 0 ±0.2
to ideal value
•VLC D, 2/3VLCD ,
1/2VLCD, 1/3VLCD
resistor
RLCD(1) Resistance at a
ladder resistor
RLCD(2) •Resistance at a
4.5-6.0 60 LCD ladder
4.5-6.0 30
ladder resistor
•1/2R mode
Pull-up MOS
Tr. resistor
Rpu •Ports 0, 1
•Ports A, B, C, D
VOH=0.9VDD 4.5-6.0 15 40 70
•Ports 70, 71, 72, 73
Hysteresis
voltage
Pin capacitance CP All pins •f=1MHz
VHIS •Ports 0, 1
•Ports 70, 71, 72, 73
RES
•
Output disable 4.5-6.0 0.1VDD V
4.5-6.0 10 pF
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
4. Serial Input / Output Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Cycle tCKCY(1) 4.5-6.0 2
Low Level
tCKL(1) 4.5-6.0 1
SCK0,
SCK1
Refer to figure 5.
pulse width
High Level
Input clock
pulse width
Cycle tCKCY(2) 4.5-6.0 2
Serial clock
Low Level
pulse width
High Level
Output clock
pulse width
Data set up time
Data hold time
Serial input
Output delay time
(Serial clock is
external clock)
Output delay time
Serial output
(Serial clock is
internal clock)
tCKH(1)
SCK0,
tCKL(2) 4.5-6.0 1/2
SCK1
•Use pull-up
resistor (1kΩ)
when open drain
tCKH(2)
output.
•Refer to figure 5.
tICK 4.5-6.0 0.1
•SI0,SI1
•SB0,SB1
•Data set-up to
SCK0, 1
•Data hold from
tCKI
SCK0, 1
•Refer to figure 5.
tCKO(1) 4.5-6.0 7/12tCYC
•SO0, SO1
•SB0, SB1
•Use pull-up
resistor (1kΩ)
when open drain
output.
tCKO(2)
•Data hold from
SCK0, 1
•Refer to figure 5.
Ratings
VDD[V] min. typ. max.
4.5-6.0 1
4.5-6.0 1/2
4.5-6.0 0.1
4.5-6.0 1/3tCYC
tCKCY
tCKCY
+0.2
+0.2
unit
V
kΩ
unit
tCYC
s
µ
No.6748-13/20
Page 14
LC86E7148
5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
High/low level
pulse width
6. AD Converter Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
RES
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
Reset acceptable 4.5-6.0 200
Ratings
VDD[V] min. typ. max.
4.5-6.0 1
4.5-6.0 2
4.5-6.0 32
4.5-6.0 128
unit
tCYC
s
µ
Parameter Symbol Pins Conditions
Resolution NAD 4.5-6.0 8 bit
Absolute precision
(Note 2)
Conversion time tCAD
Analog input
voltage range
input current
(Note 2) Absolute precision excepts quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
ETAD 4.5-6.0 ±1.5 LSB
AD conversion time =
16 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
VAIN 4.5-6.0 VSS VDD V
IAINH VAIN=VDD 4.5-6.0 1 Analog port
IAINL
AN0 - AN11
VAIN=VSS 4.5-6.0 -1
Ratings
VDD[V] min. typ. max.
15.
4.5-6.0
68
(tCYC=
0.98µs)
31.36
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
130.56
(tCYC=
4.08µs)
unit
s
µ
µA
No.6748-14/20
Page 15
LC86E7148
7. DA Converter Charact er istics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Parameter Symbol Pins Conditions
Resolution NDA 4.5-6.0 8 bit
Total error
Settling time tSAD (Note 4) 4.5-6.0 0.5
Analog output
voltage range
Output resistor RODA (Note 5) 4.5-6.0 4
VAOUT DA0 to DA3
8 bit mode 1.0
9 bit mode 0.8
9.5 bit mode
8 bit mode VSS VDD
9 bit mode (1) VSS 1/2VDD
9 bit mode (2) 1/2VDD VDD
9.5 bit mode
(Note 4) Settling time means the time from executing the DA conversion instruction to generating the analog voltage output
corresponding to the digital data on the specific port.
(Note 5) DA data = 80H
8. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS=VSS1=VSS2=VSS3=0V
Ratings
VDD[V] min. typ. max.
4.5-6.0
0.7
4.5-6.0
1/3VDD 2/3VDD
unit
%
µ
V
kΩ
s
Parameter Symbol Pins Conditions
Current dissipation
during basic
operation
(Note 6)
IDDOP(1) •FmCF=6MHz
IDDOP(2) •FmCF=3MHz
IDDOP(3) •FmCF=0Hz
IDDOP(4)
VDD1=
VDD2=
VDD3
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Continue.
VDD[V]
4.5-6.0
4.5-6.0
4.5-6.0
4.5-6.0
min. typ. max.
Ratings
15 30
unit
mA
6 15
4 13
4 9
No.6748-15/20
Page 16
LC86E7148
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 6)
IDDHALT(1) •HALT mode
VDD1=
VDD2=
VDD3
•FmCF=6MHz
Ceramic resonator
Ratings
VDD[V] min. typ. max.
4.5-6.0 6 11
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
IDDHALT(2) •HALT mode
4.5-6.0 2.2 9
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
IDDHALT(3) •HALT mode
4.5-6.0 500 1700
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
IDDHALT(4)
•HALT mode
4.5-6.0 25 100
FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
IDDHALT(5)
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Current dissipation
in HOLD mode
(Note 6)
IDDHOLD(1) VDD1=
VDD2=
VDD3
HOLD mode
4.5-6.0 0.05 30
(Note 6) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
µA
No.6748-16/20
Page 17
LC86E7148
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type Maker Oscillator C1 C2
6MHz ceramic resonator
oscillation
Kyocera
CSA6.00MG 33pF 33pF Murata
CST6.00MGW on chip
KBR-6.0MSA 33pF 33pF
PBRC6.00A(chip
33pF 33pF
type)
KBR-6.0MKS
on chip
PBRC6.00B(chip
type)
3MHz ceramic resonator
oscillation
CSA3.00MG 33pF 33pF Murata
CST3.00MGW on chip
Kyocera KBR-3.0MS 47pF 47pF
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub clock)
Oscillation type Maker Oscillator C3 C4
32.768kHz crystal
oscillation
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL
characteristics.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation
pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1 CF2 XT1 XT2
CF
C2 C1
X’tal
C4 C3
Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit
No.6748-17/20
Page 18
LC86E7148
Power supply
RES
Reset time
VDD
VDD limit
0V
Internal RC
resonator oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed Instruction execution mode Reset
Instruction
execution mode
OCR6=1
<Reset time and oscillation stable time>
HOLD release signal
Valid
Internal RC
resonator oscillation
CF1, CF2
tmsCF
XT1, XT2
tssXtal
Operation mode
HOLD
Instruction execution mode
<HOLD release signal and oscillation stable time>
Figure 3 Oscillation stable time
No.6748-18/20
Page 19
LC86E7148
tCKO
tC
tICK tC
tC
tCKC
VDD
RES
RES
R
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has be en over infer ior limit of
RES
C
supply voltage.
Figure 4 Reset circuit
<AC timing point>
0.5VDD
Y
SCK0
SCK1
SI0
SI1
SO0, SO1
SB0, SB1
KL
<Timing>
KH
KI
Figure 5 Serial input / output test condition
tPIH tPIL
Figure 6 Pulse input timing condition
1kΩ
50pF
<Test load>
No.6748-19/20
Page 20
LC86E7148
No.6748-20/20
PS
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