Page 1
Ordering number : ENN*6744
CMOS IC
LC86E5632
8-Bit Single Chip Microcontroller
with the One-Time Programmable UVEPROM
Preliminary
Overview
The LC86E5632 is a CMOS 8-bit single chip microcontroller with one-time UVEPROM for the LC865600 series.
This microcontroller has the function and the pin description of the LC865600 series mask ROM version, and 32K-byte
EPROM. The program data is rewritable.
It is suitable to develop i ng the program.
Features
(1) Option switching by EPROM data
The option function of the LC865600 series can be specified by the EPROM data.
LC86E5632 can be checked the function of the trial pieces using the mass production board.
(2) Internal one-time EPROM capacity : 32768 bytes
(3) Internal RAM capacity : 512 bytes
Mask ROM version PROM capacity RAM capacity
LC865632 32512 bytes 512 bytes
LC865628 28672 bytes 512 bytes
LC865624 24576 bytes 512 bytes
LC865620 20480 bytes 384 bytes
LC865616 16384 bytes 384 bytes
LC865612 12288 bytes 384 bytes
LC865608 8192 bytes 384 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package
stamping and the screening. Contact our representative for further information.
Ver.1.02
30399
91400 RM (IM) HK No.6744-1/21
Page 2
LC86E5632
(4) Operating supply voltage : 4.5V to 6.0V
(5) Instruction cycle time : 0.98µs to 400µs
(6) Operating temperature : +10°C to +40°C
(7) The pin compa tible with mask ROM version
(8) Applicable mask ROM version : LC865632/ LC865628/ LC865624/LC865620/LC865616/
LC865612/ LC865608
(9) Factory shipment : DIC64S, QFC64E
Notice for use
LC86E5632 is provided for the first release and small shipping of the LC865600 series.
At using, take notice of the followings.
(1) A point of difference LC86E5632 and LC865600 series
Item LC86E5632 LC865632/28/24/20/16/12/08
Port form at reset Please refer “Port form at reset” on next page.
Operation after reset
releasing
Operating supply voltage
range (VDD)
Operating temperature
range (Topg)
Total output current
[∑IOAH(1)]
[∑IOAH(2)]
Power dissipation
[IDDOP(1)]
[IDDOP(2)]
[IDDOP(3)]
[IDDOP(4)]
The option is specified until 3ms after
going to a ‘H’ level to the reset terminal
by dgrees. The program is executed
from 00H of the program counter.
4.5V to 6.0V
°
+10
to +40
C
Refer to ‘electrical ch aracteristics’ on t he semiconductor news.
°
C
• A kind of the option corresponding of the LC86E5632
A kind of option Pins, Circuits Contents of the option
Input/output form of
Input/output ports
Pull-up MOS Tr. Of port7 port7
Port 0
(Specified in a bi t)
Port 1,2
(Specified in a bi t)
Port 3,4,5
(Specified in a bi t)
(Specified in a bi t)
The port operation related the option is different at reset. Refer to the next table.
The program is executed from 00H of the
program counter immediately after going to
a ‘H’ level to reset terminal.
2.7V to 6.0V
°
-30
to +70
C
1. Input : No pull-up MOS Tr.
Output : N-channel open drain
2. Input : Pull-up MOS Tr.
Output : CMOS
1. Input : Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. Input : No Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input : Programmable pull-up MOS Tr.
Output : CMOS
1. Pull-up MOS Tr. not provided
2. Pull-up MOS Tr. provide d
*
has on pull-up resistor option.
P74
°
C
No.6744-2/21
Page 3
LC86E5632
•Port form at reset
Pin
P0
P1,
P2
P3,
P4,
P5
P7
Contents of the option
Input : Not pull-up MOS Tr.
Output : N-channel open drain
Input : Pull-up MOS Tr.
Output : CMOS
Input : Programmable pull-up
MOS Tr.
Output : N-channel open drain
Input : Programmable pull-up
MOS Tr.
Output : CMOS
Input : Not Programmable
pull-up MOS Tr.
Output : N-channel open drain
Input : Programmable pull-up
MOS Tr.
Output : CMOS
Pull-up MOS Tr. not provided (Same as the mask version) Input mode without pull-up
Pull-up MOS Tr. provided
(Same as the mask version) Input mode without pull-up
Input mode
•The pull-up MOS Tr. is not provided
during reset or several hundred
microseconds after releasi ng reset.
After that, the pull-up MOS Tr. is
provided. (Output is OFF)
(Same as the mask version) Input mode without pull-up
(Same as the mask version) Input mode without pull-up
(Same as the mask version) Input mode without pull-up
(Same as the mask version) Input mode without pull-up
Input mode
•The pull-up MOS Tr. is not provided
during reset or several hundred
microseconds after releasi ng reset.
After that, the pull-up MOS Tr. is
provided.
LC86E5632 LC865632/28/24/20/16/12/08
MOS Tr. (Output is OFF)
Input mode without pull-up
MOS Tr. (Output is OFF)
MOS Tr. (Output is OFF)
MOS Tr. (Output is OFF)
MOS Tr. (Output is OFF)
MOS Tr. (Output is OFF)
MOS Tr.
Input mode without pull-up
MOS Tr.
(2) Option
LC86E5632 uses 256 bytes which is addressed on 7F00H to 7FFFH in the program memory as option data area. This
area does not affect the execution of program but the program memory capacity of LC865632 is 32512 bytes which is
addressed on 0000H to 7EFFH.
The option data is created by the option specified program “SU865000.EXE”. The created option data is linked to the
program area by linkage loader “L865000.EXE”.
No.6744-3/21
Page 4
LC86E5632
(3) ROM space
7FFFH
7F00H
7EFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
Opt ion data
Area 256 bytes
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
Program area
32K bytes
Program area
28K bytes
Program area
24K bytes
Program area
20K bytes
Program area
16K bytes
Program area
12K bytes
Program area
8K bytes
0000H
LC865632 LC865628 LC865624 LC865620 LC865616 LC865612 LC865608
How to use
(1) Specification of option
Programming data for EPROM of the LC86E5632 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P5632.
(2) How to program for the EPROM
LC86E5632 can be programmed by the EPROM programmer with attachment ; W86EP5032D,
W86EP5032Q.
• Recommended EPROM programmer
Productor EPROM programmer
Advantest R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100, PKW-3000
Minato electronics MODEL 1890A
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to
“0000H to 7FFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FF’ at the sequence 2 above.
• The programming by a sequential operation “BLANK⇒PROGRAM⇒VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
.
No.6744-4/21
Page 5
LC86E5632
(4) How to eliminate
The programming data can be erased by using the EPROM eraser.
(5) Shielding
The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use.
Data security
Data security
1 pin mark
of LSI
1 pin
Not data security
1 pin
Not data security
W86EP5032D W86EP5032Q
No.6744-5/21
Page 6
Pin Assignment
SANYO:DIC64S
SANYO:QFC64E
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM
TEST1
RES
XT1/P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P30
P31
P32
P33
TEST1
RES
XT1/P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
LC86E5632
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P17/PWM
P16/BUZ
P15/SCK1
P14/SI1/SB1
48
47
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
45
1 2 3 4 5 6 7 8 9
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P13/SO1
44
P30
P12/SCK0
P31
43
P11/SI0/SB0
P32
42
P10/SO0
41
P33
P07
40
P34
P06
39
10
P35
P05
38
11
P36
P04
37
12
P37
P03
36
13
P40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P02
35
14
P41
P07
P06
P05
P04
P03
P02
P01
P00
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34
P01
P00
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
15
16
P42
P43
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
No.6744-6/21
Page 7
System Bl ock Diagram
Base Timer
SIO0
SIO1
Timer 0
Timer 1
ADC
INT0 to 3
Noise Filtter
Real Time Service
RAM
(128 bytes)
Interrupt Control
Standby Control
CF
RC
X’tal
LC86E5632
Clock
Generator
Bus Interface ACC
Port 1
Port 7
Port 8
Port 2
Port 3
Port 4
Port 5
IR PLA
EPROM
Control
EPROM (32KB)
PC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
Port 0
Watch Do g Timer
A15-A0
D7-D0
TA
CE
OE
DASEC
VDDVPP
No.6744-7/21
Page 8
LC86E5632
LC86E5632 Pin description
Pin name I/O Function description Option PROM mode
VSS - Power pin (-) - VDD - Power pin (+) - VDDVPP - Power p in (+) - Power for programming
PORT0
P00 to P07
PORT1
P10 to P17
PORT2
P20 to P27
PORT3
P30 to P37
PORT4
P40 to P47
PORT5
P50 to P51
PORT7
P70
P71 to
P74
I/O •8-bit input/output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
I/O •2-bit input/output port
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
•5-bit input port
•Other pin functions
P70 : INT0 in put/HOLD release/N-channel Tr.
I/O
I
output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event
input
: 32.768kHz cry s ta l oscillation terminal XT1
P74
•Interrupt recei ved forms,
rising falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
the vector addresse s
rising
falling
&
high
level
Continue.
low
level
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
•Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
P74
has no pull-up
•
resistor.
vector
-
Data line
D0 to D7
Address input
A7 t o A0
Address input
A14 to A8 (*5)
P47 : TA (*4)
Input of PROM
control sign als
DASEC (*1)
OE
(*2)
CE
(*3)
No.6744-8/21
Page 9
LC86E5632
Pin name I/O Function description Option PROM mode
PORT8
P80 to 87
RES
TEST1
P74
XT1/
XT2 O •Output pin for 32.768kHz crystal oscillation
CF1 I Input pin for the ceramic resonator oscillation - CF2 O Output pin for the ceramic resonator oscillation - -
All of port options can be specified in bit unit.
♦
I •8-bit input por t
•Other function
AD input port (AN7 to AN0)
I Reset pin - -
O Test pin
Should be left unconnected.
I •Input pin for 32.768kHz crystal oscillation
•Other function : Input port
In case of non use, connect to VDD.
•Other function
In case of non use, shoul d be left unconnected.
P74
- -
- -
- -
- -
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 TA ! PROM control signal input
*5 A14 ! Address input
* Connect like the following figure to reduce noise into a VDD terminal.
Short-circuit the VDD ter min al to the VDDVPP terminal .
Short-circuit the VSS termina l to the VSS terminal.
Power
Supply
VDD
LSI
VDDVPP
VSS VSS
No.6744-9/21
Page 10
LC86E5632
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter Symbol Pins Conditions
Ratings
[V]
VDD
min. typ. max.
Supply voltage VDDMAX VDD,VDDVPP VDD=VDDVPP -0.3 +7.0
Input voltage VI(1) •Ports 71,72,73,74
-0.3 VDD+0.3
•Port 8
RES
•
voltage
VIO(1) •Ports 0,1,2
•Ports 3,4,5 at CMOS
-0.3 VDD+0.3 Input/Output
output
VIO(2) Ports 3,4,5 at N-ch open
-0.3 15
drain output option
High
level
output
current
Peak
output
current
Total
IOPH(1) •Ports 0,1,2,3,4,5 •CMOS output
-4
•At each pins
Σ
IOAH(1) Ports 0,1,2 The total of all pins -25
output
current
IOAH(2) Ports 3,4,5
The total of all pins -20
Σ
Low
level
output
current
output
current
Total
output
current
IOPL(1) Ports 0,1 ,2,3,4,5 At each pins 20 Peak
IOPL(2) Port 70 At each pins 15
Σ
IOAL(1) Po rts 0,1,70 The total of all pins 40
Σ
IOAL(2) Port 2 The total of all pins 40
Σ
IOAL(3) Ports 3,4,5 The total of all pins 80
Pdmax(1) DIP64S Ta=+10 to+40°C 720 Maximum power
dissipation
Operating
Pdmax(2) QFP64E Ta=+10 to+40°C 420
Topr 10 40
Temperature range
Storage
Tstg -65 150
Temperature range
unit
V
mA
mW
°
C
No.6744-10/21
Page 11
LC86E5632
2. Recommended Operating Range at Ta=+10°C to +40°C, VSS=0V
Parameter Symbol Pins Conditions
≤
400µs
CYC
Operating
Supply voltage
Hold voltage VHD VDD RAMs and the
Input high
voltage
VIH(7) Ports 3,4,5 of open drain
Input low
voltage
Operation
cycle time
Oscillation
frequency
range
(Note 1)
VDD(1) VDD 0.98µs ≤ t
CYC
t
registers hold vo ltage
at HOLD mode.
VIH(1) Port 0 (Schmitt) Output disable 4.5 to 6.0 0. 4VDD
VIH(2) •Ports 1,2
•Ports 72,73 (Schmitt)
VIH(3) •Port 70
(Port input/interrupt)
•Port 71
RES
•
VIH(4) Port 70
(Watchdog timer)
VIH(5) •Port74
•Port 8
VIH(6) Ports 3,4,5 of
CMOS output (Schmitt)
output (Schmitt)
VIL(1) Port 0 (Schmitt) Output disable 4.5 to 6.0 VSS 0.2VDD
VIL(2) •Ports 1,2,3,4,5
•Ports 72,73 (Schmitt)
VIL(3) •Port 70
(Port input/interrupt)
•Port 71
RES
•
VIL(4) Port 70
(Watchdog timer)
VIL(5) •Port
CYC
t
4.5 to 6.0 0.98 400 µs
FmCF(1) CF1, CF2 •6MHz
FmCF(2) CF1, CF2 •1.5MHz
FmRC RC oscillation 4.5 to 6.0 0.3 0.8 3.0
FsXtal XT1, XT2 •32.768kHz
74
•Port 8
(Schmitt)
(Schmitt)
Output disable 4.5 to 6.0 0.75VDD VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
Output disable 4.5 to 6.0 0.75VDD VDD
Output disable 4.5 to 6.0 0.75VDD 13.5
Output disable 4.5 to 6.0 VSS 0.25VDD
N-channel Tr.OFF 4.5 to 6.0 VSS 0.25VDD
N-channel Tr.OFF 4 .5 to 6.0 VSS 0. 8VDD
N-channel Tr.OFF 4.5 to 6.0 VSS 0.25VDD
(ceramic resonator
oscillation)
•Refer to figure 1
(ceramic resonator
oscillation)
•Refer to figure 1
(crysta l os cillation)
•Refer to figure 2
Continue.
Ratings
VDD[V] min. typ. max.
4.5 6.0
2.0 6.0
VDD
+0.9
4.5 to 6.0 0.75VDD VDD
4.5 to 6.0 0.9VDD VDD
4.5 to 6.0 0.75VDD VDD
-1.0
4.5 to 6.0 6
4.5 to 6.0 1.5
4.5 to 6.0 32.768 kHz
unit
V
MHz
No.6744-11/21
Page 12
LC86E5632
Parameter Symbol Pins Conditions
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1) CF1, CF2 •6MHz
(ceramic resonator oscillation)
•Refer to figure 3
tmsCF(2) CF1, CF2 •1.5MHz
(ceramic resonator oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kHz (c rystal osc il l a tio n)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0 s
unit
ms
No.6744-12/21
Page 13
LC86E5632
3. Electrical Characteristics at Ta=+10°C to +40°C, VSS=0V
Parameter Symbol Pins Conditions
Input high
current
Input low
current
voltage
Output low
voltage
Pull-up MOS
Tr. resistor
Hysteresis
voltage
Pin capacitance CP All pins •f=1MHz
IIH(1) Ports 3,4,5 at open
drain output
IIH(2) •Port 0 without
pull-up MOS Tr.
•Ports 1,2,3,4,5
IIH(3) •Ports 70,71,72,73
without pull-up
MOS Tr.
•Port 8
RES
IIH(4)
IIL(1) •Ports 1,2,3,4,5
IIL(2) •Ports 70,71,72,73
IIL(3)
VOH(1) IOH=-1.0mA 4.5 to 6.0 VDD-1 Output high
VOH(2)
VOL(1) IOL=10mA 4.5 to 6.0 1.5
VOL(2)
VOL(3) IOL=1mA 4.5 to 6.0 0.4
VOL(4)
Rpu •Ports 0,1,2,3,4,5
VHIS •Ports 0,1,2,3,4,5
VIN=VDD 4.5 to 6.0 1
•Port 0 without
pull-up MOS Tr.
without pull-up
MOS Tr.
•Port 8
VIN=VSS 4.5 to 6.0 -1
RES
Ports 0,1,2,3,4,5 at
CMOS output
Ports 0,1,2,3,4,5
Port 70
•Ports 70,71,72,73
•Ports 70,71,72,73
•
RES
•Output disable
•VIN=13.5V
(including off-leakage
current of the output Tr .)
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VDD
(including off-leakage
current of the output Tr .)
VIN=VDD 4.5 to 6.0 1
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VSS
(including off-leakage
current of the output Tr .)
VIN=VSS 4.5 to 6.0 -1
IOH=-0.1mA 4.5 to 6.0 VDD-0.5
IOL=1.6mA 4.5 to 6.0 0.4
IOL=0.5mA 4.5 to 6.0 0.4
VOH=0.9VDD 4.5 to 6.0 15 40 70 kΩ
Output disable 4.5 to 6.0
•VIN=VSS for all
unmeasured terminals.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 5
4.5 to 6.0 1
4.5 to 6.0 -1
0.1VDD
4.5 to 6.0 10 pF
unit
µ
V
V
A
No.6744-13/21
Page 14
LC86E5632
4. Serial Input/Output Characteristics at Ta=+10°C to +40°C, VSS=0V
Parameter Symbol Pins Conditions
Cycle t
Low Level
CKCY
CKL
t
(1) 1
SCK0,
(1) 2
Refer to figure 5 4.5 to 6.0
SCK1
pulse width
High Level
Input clock
CKH
t
(1)
pulse width
Serial clock
Low Level
pulse width
Cycle t
High Level
Output clock
pulse width
Data set-up time
Data hold time
Serial input
Output delay time
(External clock
using for serial
transfer clock)
Output delay time
(Internal clock
Serial output
using for serial
CKCY
(2) 2
SCK0,
CKL
t
(2) 1/2t
SCK1
•Use pull- up
resistor (1kΩ) in
the open drain
CKH
t
(2)
output.
•Refer to figure 5
ICK
0.1
t
CKI
t
•SI0,SI1
•SB0,SB1
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5
CKO(1)
t
7/12
•SO0,SO1
•SB0,SB1
•Use pull- up
resistor (1kΩ) in
the open drain
output.
CKO(2)
t
•Data hold from
SCK0,1
•Refer to figure 5
transfer clock)
Ratings
VDD[V] min. typ. max.
1
4.5 to 6.0
CKCY
CKCY
1/2t
4.5 to 6.0
0.1
4.5 to 6.0
CYC
t
+0.2
1/3
CYC
t
+0.2
unit
CYC
t
µ
s
No.6744-14/21
Page 15
LC86E5632
5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS=0V
Parameter Symbol Pins Conditions
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIL(4)
•INT0, INT1
•INT2/T0IN
•INT3
INT3
(The noise rejection clock
selected to 1/1.)
INT3
(The noise rejection clock
selected to 1/16.)
RES
Reset acceptable 4.5 to 6.0 200
•Interrupt accept able
•Timer0-countable
•Interrupt accep table
•Timer0-countable
•Interrupt accept able
•Timer0-countable
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 1
4.5 to 6.0 2
4.5 to 6.0 32
unit
CYC
t
High/low level
µ
s
6. AD Converter Characteristics at Ta=+10°C to + 40°C, VSS=0V
Parameter Symbol Pins Conditions
Resolution N 4.5 to 6.0 8 bit
Absolute precision
(Note 2)
Conversion time tCAD
Analog input
voltage range
input current
ET 4.5 to 6.0 ±1.5 LSB
AD conversion time = 16
×
tCYC
(ADCR2= 0) (N o te 3)
AD conversion time = 32
×
tCYC
(ADCR2= 1) (N o te 3)
VAIN 4.5 to 6.0 VSS VDD V
IAINH VAIN=VDD 4.5 to 6.0 1 Analog port
IAINL
AN0 to AN7
VAIN=VSS 4.5 to 6.0 -1
Ratings
VDD[V] min. typ. max.
4.5 to 6.0
15.68
(tCYC=
0.98µs)
31.36
(tCYC=
0.98µs)
65.28
(tCYC=
4.08µs)
130.56
(tCYC=
4.08µs)
unit
µ
s
µ
A
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the comp lete digital
conversion value to the register.
No.6744-15/21
Page 16
LC86E5632
7. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS=0V
Parameter Symbol Pins Conditions
Current dissipation
during basic operation
(Note 4)
IDDOP(1) •FmCF=6MHz
IDDOP(2) •FmCF=1.5MHz
IDDOP(3) •FmCF=0Hz
IDDOP(4)
VDD
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
Continue.
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 13 26
4.5 to 6.0 7 14
4.5 to 6.0 4 10
4.5 to 6.0 4 8
unit
mA
No.6744-16/21
Page 17
LC86E5632
Parameter Symbol Pins Conditions
Current dissipation
in HALT mode
(Note 4)
in HOLD mode
(Note 4)
IDDHALT(1) •HALT mode
IDDHALT(2) •HALT mode
IDDHALT(3) •HALT mode
IDDHALT(4)
IDDHOLD(1) 4.5 to 6.0 0.05 30 Current dissipation
IDDHOLD(2)
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•FmCF=1.5MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•HALT mode
FmCF=0Hz
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
VDD HOLD mode
Ratings
VDD[V] min. typ. max.
4.5 to 6.0 5 10
4.5 to 6.0 2.2 4.6
4.5 to 6.0 550 1000
4.5 to 6.0 25 100
2.5 to 4.5 0.02 20
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
unit
mA
µ
A
No.6744-17/21
Page 18
LC86E5632
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type Maker Oscillator C1 C2 Rf Rd
12MHz ceramic resonato r
oscillation
oscillation
Murata
Murata
CSA12.0MTZ 33pF 33pF OPEN 560Ω
CSA12.0MTZ 39pF 30pF OPEN 0Ω
CST12.0MTW on chip OPEN 560Ω
CSA3.00MG040 100pF 100pF OPEN 1.5Ω 3MHz ceramic resonator
CST3.00MGW040 on chip OPEN 1.5Ω
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type Maker Oscillator C3 C4
Kyocera KF-38G-13P0200 18pF 18pF 32.768kHz crystal oscillation
Seiko Epson MC-306,C-002RX,32.768kHz 4pF 4pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
CF1 CF2
XT1 XT2
C1
Rf
CF
Rd
C2
C3
X’tal
C4
Ceramic oscillation circuit Crystal oscillation
Figure 1 Main-clock circuit Figure 2 Sub-clock circuit
No.6744-18/21
Page 19
LC86E5632
Power supply
VDD
VDD limit
OV
RES
Reset time
Interrnal RC
resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Operation mode
Unfixed Reset Instruction execution mode
< Reset time and oscillation stabilizing time. >
HOLD release signal
Valid
Interrnal RC
resonator
oscillation
CF1, CF2
tmsCF
XT1, XT2
tssXtal
Operation mode
HOLD Instruction execution mode
< HOLD release signal and oscillation stabilizing time. >
Figure 3 Oscillation stable time
No.6744-19/21
Page 20
LC86E5632
tCKO
tC
tICK tC
tC
tCKC
VDD
RES
R
RES
(Note) Fix the value of C
RES
, R
RES
that is
sure to reset until 200µs, after Power
supply has be en over inferior limit o f
supply voltage.
RES
C
Figure 4 Reset circuit
<AC timing point>
0.5VDD
SCK0
SCK1
KL
SI0
SI1
SO0, SO1
SB0, SB1
Y
KH
1KΩ
KI
50pF
<Timing>
<Test load>
Figure 5 Serial input / output test condition
tPIH tPIL
Figure 6 Pulse input timing condition
No.6744-20/21
Page 21
LC86E5632
No.6744-21/21
PS
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