Datasheet LC868116A, LC868112A, LC868108A Datasheet (SANYO)

Ordering number : ENN*6724

CMOS IC

LC868116/12/08A

8-Bit Single Chip Microcontroller with

16/12/08K-Byte ROM and 640-Byte RAM On Chip

Preliminary
Overview

The LC868116A/12A/08A microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional
blocks :

- CPU : Operable at a minimum bus cycle time of 0.5µs (microseconds)

- On-chip ROM maximum capacity : 16K bytes

- On-chip RAM capacity : 640 bytes

- Dot-matrix liquid crystal display (LCD) automatic display controller / driver

- Externa l memory

- 16-bit timer / counter (or two 8-bit timers)

- 16-bit timer / PWM (or two 8-bit timers)

- Two 8-bit synchronous serial -interface circuits

- 13-source 9-level vectored interrupt system

All of the above functions are fabricated on a single chip

Ver.1.1
21998

91400 RM (IM) HO No.6724-1/28

LC868116/12/08A

Features

(1) Read Only Memory (ROM) : LC868116A 16384 × 8 bits

: LC868112A 12288 × 8 bits
: LC868108A 8192 × 8 bits

(2) Random Access Memory (RAM) : 512 × 8 bits (calculation area)
128

8 bits (display area)

×

(3) Bus Cycle Time / Instruction Cycle Time

Bus cycle

time

0.5µs 1µs

1µs 2µs

2µs 4µs

7.5µs 15µs

3.8µs 7.5µs

183µs 366µs

91.5µs 183µs

Instruction

cycle time

System clock

oscillation

Ceramic (CF)

Oscillation

Voltage Note

frequency

12MHz OCR7=0

4.5-6.0V

6MHz

Ceramic (CF)

6MHz OCR7=0

4.5-6.0V

3MHz

Ceramic (CF)

3MHz OCR7=0

2.5-6.0V

1.5MHz

Internal RC 800kHz 2.5-6.0V

Crystal (XTAL) 32.768kHz 2.5-6.0V

OCR7=1

OCR7=1

OCR7=1
OCR7=0
OCR7=1
OCR7=0
OCR7=1

* Bus cycle time means ROM-read period.
OCR7 : Bit-7 of the oscillation control register.

(4) Ports

- Input / output ports : 6 ports (47 terminals)
Input/output port programmable in a nibble : 1 port (8 terminals)
Input/output port programmable every function unit : 1 port (7 terminals)
Input/output port programmable in a bit : 4 ports (32 terminals)

- Input port : 1 port (4 terminals)

- Ports at external memory mode

1. External Latch
Port 0 : Address output of lower 8-bit, input/output of data
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output

2. No External Latch
Port 0 : Input/output of data
Port 3 : Address output of lower 8-bit
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
(Set whether the external latch is used or not by program.)

- LCD segment driver output ports : 48 terminals

(Function change available : segment/common)

- LCD common driver output ports : 16 terminals
(1/32 duty maximum : at using segment output ports as common output by mask option)

(5) External memory access

- Externa l progra m memor y acce ss function

External program memory capacity : 64K bytes
Programable switch internal program/external program
(At initial : Internal program)
Enable/disable control of external program ! internal p rogr am memo ry switch

excluding

external memory

access function

for external

memory acce ss

No.6724-2/28

LC868116/12/08A

- Ports
Port 2 : Address output of upper 8-bit

Uses

EROE terminal (OE signal of the external ROM)

1. Using the external latch
Port 0 : Address output of lower 8-bit, data input port
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)

2. Not use the external latch
Port 0 : Input port of data
Port 3 : Addres s output of lowe r 8-bit

- External data memory access function

Using the LDC instruction
External memory capacity : 16M bytes

1. Internal prog ram memory
Switch the reference of internal ROM data/external ROM data by program.

2. External program memory

Reference external ROM data only.
Ports
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output

Uses

EROE terminal (OE signal of the external ROM)

1. Using external latch

Port 0 : Address output of lower 8-bit, input port of data

Uses the ADLC terminal (latch clock of the lower 8-bit address signal)

2. Not use external latch

Port 0 : Input port of data

Port 3 : Addres s output of lowe r 8-bit

- External RAM memory access function
Using the LDX, STX instruction
External memory capacity : 16M bytes
Ports

Port 2 : Address output of upper 8-bit
Port 5 : Bank address output

Uses the P46 terminal (
Uses the P47 terminal (

OE signal of external RAM) : the LDX instruction execution
WE signal of external RAM) : the STX instruction execution

1. Using the external latch circuit
Port 0 : Address output of lower 8-bit, input/output port of data
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)

2. Not use the external latch circuit
Port 0 : Input/output port of data
Port 3 : Addres s output of lowe r 8-bit

(6) LCD automatic display controller

- Display duty : 1/4 - 1/32 duty

* Up to 1/32 display duty can be specified by program. V DD allows up to 6V. Select the preferable LCD panel within

this range.

- Displ ay bias : 1/4, 1/5, 1/ 7 bias

- Programmable character display / graphic display

- Character display

1. On-chip char acter generator ROM
ROM capacity : 8960 bits
Character font : 5 × 7 dots
Number of Characters : 256

No.6724-3/28

LC868116/12/08A

2. LCD instruction
Display : ON/OFF
Cursor : ON/OFF/BLINK
Character blink : ON/OFF
Character scroll : Control by specified starting address

- Graphic display

LC868100 series : 1024 dots Maximum
External segment driver : Enable to extend of LCD drive

- LCD contrast

LCD display contrast programmable

- LCD display power supply

Doubler circuit available wi thin VDD≤3V.
* Doubler generates up to 6V.

- LCD driver

Following two kinds of combination can be selected by mask option

No. Segment output port Common output port

1 48 16
2 32 32

* Up to 32 commons can be specified by mask option. As maximum LCD display voltage is 6V, please select

the preferable LCD panel and the display condition with this range.

* In general, the LCD driver cannot be expanded.

(7) Serial-interface

- Two 8-bit serial-interf ace circuits

LSB first / MSB first function available

- Internal 8-bit baud-rate generator in common with two serial-interface circuits

(8) Timers

- Timer0 (T0L, T0H)
16-bit timer / counter
2-bit prescaler + 8-bit programmable prescaler

Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter

- Timer1 (T1L, T1H)
16-bit timer / PWM

Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)

- Base timer

Every 500ms overflow system for a clock application (using 32.768kHz crystal oscilla tion for Base timer clock)
The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0

(9) Buzzer output

- The Buzzer sound frequency selectable ; 4KHz, 2KHz

(10) Remote control receiver circuit (using P73/INT3/T0IN terminal)

- Noise rejection available

- The interrupt polarity selectable

No.6724-4/28

LC868116/12/08A

(11) Watchdog timer

- The watchdog timer is taken on RC outside. (using P70/INT0 terminal)

- Watchdog timer operation selectable : interrupt system, system reset

(12) Interrupts system

- 13-source 9-level vectored interrupts :

1. External interrupt INT0 (includes watchdog timer)

2. External interrupt INT1

3. External interrupt INT2, timer / counter T0L (timer 0 lower 8 bits)

4. External interrupt INT3, base timer

5. Timer / counter T0H (timer 0 upper 8-bit)

6. Timer T1L (timer 1 lower 8-bit), Timer T1H (timer 1 upper 8-bit)

7. Serial interface SIO0

8. Serial interface SIO1

9. Port 0 or Port 3

- Interrupt priority contr ol availa b le

Microcomputer allows 3 levels of interrupt; low level, high level and highest level of multiplex interrupt. It can specify
a low level or a high level interrupt priority from INT2/T0L through port 0 or port 3 (the above interrupt number from
three through nine). It can also specify a low level or the highest level interrupt priority to INT0 and INT1.

(13) Sub-routine stack levels

- 128 levels (Max.) : stack area included in RAM area

(14) Multiplication and division

- 16 bits × 8-bit (7 instruction cycle times)

- 16 bits / 8-bit (7 instruction cycle times)

(15) Three oscillation circuits

- On-chip RC oscillation circuit using for the system clock, for the LCD display and for the step-up circuit.

- On-chip CF oscillation circuit using for the system clock, for the LCD display and for the step-up circuit.

- On-chip crystal oscillation circuit using for the system clock, for time-base clock and for the LCD display.

(16) Standby function

- HALT mode function

The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This operation mode can be released by the interrupt request signals or setting to low level for the reset terminal

RES).

(

- HOLD mode function

The HOLD mode is used to freeze all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations:

• Reset terminal (

RES) set to low level.

• Set to assigned level to INT0/1 terminals.

• Set to assigned level to Port 0/3.

(17) Factory shipment

- Chip

QIC160 package shipping available for sample evaluation.

(18) Development support tools

- Evaluation (EVA) chip : LC868099

- Emulator : EVA86000 + ECB868000 (Evaluation chip board)

No.6724-5/28

Pin Assignment

Chip size : 4.98mm × 6.26mm
Pad size : 106µm × 106µm
Bonding area size : 90µm × 90µm
Chip thickness : 480µm±20µm

CF2

CF1

VSS

XT2

XT1

RES

EROE

ADLC

P27

LC868116/12/08A

P26

P25

P24

P23

P22

P21

P20

P07

P06

P05

P04

P03

P02

P01

P00

P37

P36

P35

P34

P33

P32

P31

P30

VDD

VDD

S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34

S1
S2
S3
S4
S5
S6
S7
S8
S9

(0, 0)

P50
P51
P52
P53
P54
P55
P56
P57
P17
P16
P15
P14
P13
P12
P11
P10
P73
P72
P71
P70
P47
P46
P44
P43
P42
P41
P40
VSS

CUP1
CUP2
VOUT2
VLCD
V5

S35C7S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

S47

S48

C16

C15

C14

C13

C9C8C6C5C4C3C2C1V1

C12

C11

C10

V2

V4

V3

No.6724-6/28

LC868116/12/08A

Pad Name and coordinates table

Pad
No.

Name

Coordinates Coordinates Coordinates

Xµm Yµm

Pad
No.

Name

Xµm Yµm
1 VDD -2240 2236 47 S46 -700 -2875 93 P16 2240 960
2 S1 -2240 2100 48 S47 -565 -2875 94 P17 2240 1096
3 S2 -2240 1965 49 S48 -429 -2875 95 P57 2240 1231
4 S3 -2240 1829 50 C16 -293 -2875 96 P56 2240 1367
5 S4 -2240 1694 51 C15 -158 -2875 97 P55 2240 1502
6 S5 -2240 1558 52 C14 -22 -2875 98 P54 2240 1638
7 S6 -2240 1422 53 C13 113 -2875 99 P53 2240 1774
8 S7 -2240 1287 54 C12 249 -2875 100 P52 2240 1909
9 S8 -2240 1151 55 C11 385 -2875 101 P51 2240 2045

10 S9 -2240 1016 56 C10 520 -2875 102 P50 2240 2180
11 S10 -2240 880 57 C9 656 -2875 103 VDD 2123 2875
12 S11 -2240 744 58 C8 791 -2875 104 P30 1987 2875
13 S12 -2240 609 59 C7 927 -2875 105 P31 1852 2875
14 S13 -2240 473 60 C6 1063 -2875 106 P32 1716 2875
15 S14 -2240 338 61 C5 1198 -2875 107 P33 1581 2875
16 S15 -2240 202 62 C4 1334 -2875 108 P34 1445 2875
17 S16 -2240 66 63 C3 1469 -2875 109 P35 1309 2875
18 S17 -2240 -69 64 C2 1605 -2875 110 P36 1174 2875
19 S18 -2240 -205 65 C1 1741 -2875 111 P37 1038 2875
20 S19 -2240 -340 66 V1 1876 -2875 112 P00 903 2875
21 S20 -2240 -476 67 V2 2012 -2875 113 P01 767 2875
22 S21 -2240 -612 68 V3 2147 -2875 114 P02 631 2875
23 S22 -2240 -747 69 V4 2283 -2875 115 P03 496 2875
24 S23 -2240 -883 70 V5 2240 -2479 116 P04 360 2875
25 S24 -2240 -1018 71 VLCD 2240 -2344 117 P05 225 2875
26 S25 -2240 -1154 72 VOUT2 2240 -2208 118 P06 89 2875
27 S26 -2240 -1290 73 CUP2 2240 -2072 119 P07 -47 2875
28 S27 -2240 -1425 74 CUP1 2240 -1937 120 P20 -182 2875
29 S28 -2240 -1561 75 VSS 2240 -1481 121 P21 -318 2875
30 S29 -2240 -1696 76 P40 2240 -1345 122 P22 -453 2875
31 S30 -2240 -1832 77 P41 2240 -1210 123 P23 -589 2875
32 S31 -2240 -1968 78 P42 2240 -1074 124 P24 -725 2875
33 S32 -2240 -2103 79 P43 2240 -938 125 P25 -860 2875
34 S33 -2240 -2239 80 P44 2240 -803 126 P26 -996 2875
35 S34 -2240 -2374 81 P46 2240 -667 127 P27 -1131 2875
36 S35 -2192 -2875 82 P47 2240 -532 128 ADLC -1267 2875
37 S36 -2056 -2875 83 P70 2240 -396 129

38 S37 -1921 -2875 84 P71 2240 -260 130
39 S38 -1785 -2875 85 P72 2240 -125 131 XT1 -1674 2875

40 S39 -1649 -2875 86 P73 2240 11 132 XT2 -1809 2875
41 S40 -1514 -2875 87 P10 2240 146 133 VSS -1945 2875
42 S41 -1378 -2875 88 P11 2240 282 134 CF1 -2081 2875
43 S42 -1243 -2875 89 P12 2240 418 135 CF2 -2216 2875
44 S43 -1107 -2875 90 P13 2240 553
45 S44 -971 -2875 91 P14 2240 689

46 S45 -836 -2875 92 P15 2240 824
The values (X, Y) indicate the coordinates of each pad center with the center of the chip as the origin.
Connect the substrate of chip to VSS or open.

Pad
No.

Name

EROE

RES

Xµm Yµm

-1403 2875

-1538 2875

No.6724-7/28

System Bl ock Diagram

LC868116/12/08A

Base Timer

SIO0

SIO1

Timer 0

Interrupt Control

Standby Control

CF

RC

Clock

X'tal

Generator

Bus Interface

Port 1

Port 7

IR PLA

ROM

PC

ACC

B Register

C Register

ALU

Timer 1

INT0-3

Noise Rejection Filter

XRAM

128 Bytes

CGROM

LCD Display

Controller

LCD Driver

Port 2

Port 3

Port 4

Port 5

EXT Register Watchdog Timer

PSW

RAR

RAM

Stack Pointer

Port 0

No.6724-8/28

LC868116/12/08A

Pin Description

Name No. I/O Function description Option

VSS 75,133 - Power terminal (-) ­VDD 1,103 - Power terminal (+) ­VLCD 71 - Power terminal (+) for LCD driver *2 ­V1 to V5 66-70 - Voltage supply terminals to LCD drivers *2 ­VOUT2 72 -

Output terminals for doubler VOUT2 ≅ 2X(VDD-VSS)

­CUP1,2 74,73 - Capacitor connecting terminals for doubler, tripler ­Port0

P00 to P07

112-119

I/O •8-bit input/output port

•Input/output can be specified in 4-bit

•External memory mode

1. EXT resistor bit 2=0

•Pull-up resistor :

Provided/Not provided

•Output form :

CMOS/N-ch open drain
Address output of lower 8-bit, input/output
of data

2. EXT resistor bit 2=1

•Input/output of data

•Input for key interrupt (P30INT=0) *1
Port1
P10 to P17

87-94

•8-bit input/output port

I/O

•Input/output can be specified in a bit

•Output form :
CMOS/N-ch open drain

•Another functions

P10

SIO0 data output

P11

SIO0 data input, bus input/output

P12

SIO0 clock input/output

P13

SIO1 data output

P14

SIO1 data input, bus input/output

P15

SIO1 clock input/output

P16

Buzzer output

P17

Timer 1 output (PWM output)

Port2
P20 to P27 120-127

I/O •8-bit input/output port

•Input/output can be specified in a bit

•Output form :
CMOS/N-ch open drain

•External memory mode

Address output of upper 8-bit
Port3
P30 to P37 104-111

I/O •8-bit input/output port

•Input/output in a bit

•External memory mode

1. EXT resistor bit 2=0 : input/output port

•Pull-up resistor :
Provided/Not provided

•Output form :
CMOS/N-ch open drain

2. EXT resistor bit 2=1 : address output of lower
8-bit for external memory

•Input for key interrupt (P30INT=L) *1

*1 P30INT : Bit 0 of Port 3 interrupt control register.
*2 The structure of the LCD power supply is shown below.

VLCD

V5

V4

V3

Resistor for
LCD contrast

adjustment

Note : If the microcontroller is operated at 3V, the voltage doubler

output (VOUT2) should be connected to the LCD power
terminal (VLCD ) .

(o r the output of an external voltage doubler should be

connected to VLCD)

V2

V1

VSS

No.6724-9/28

LC868116/12/08A

Name No. I/O Function description Option

Port4
P40 to P44
P46, P47

76-80
81,82

•7-bit input/output port

I/O

•Input/output can be specified each upper

2 b its and lower 5 bits

•Another functions

P40

CL1 Latch clock

P41

CL2 Shift clock

P42

DO Output data

P43

M Alternate signal

P44

FRM Frame signal

P46

RD

P47

Read signal

WR

Write signal

•Pull-up resistor :
Provided/Not provided

•Output form :
CMOS/N-ch open drain

(P40-P44 : LCD display extend signal,

P4 6, P47 : External RAM access signal)
Port5
P50 to P57

102-95

I/O •8-bit input/output port

•Input/output in bit unit

•External memory mode

1. EXT resistor bit 3=0 : input/output

•Pull-up resistor :
Provided/Not provided

•Output form :
CMOS/N-ch open drain

2. EXT resistor bit 3=1 : bank address output for

external memory
Port7

P70 to P73

83-86

•4-bit input port

I

•Another functions

P70

P71
P72
P73

INT0 input/HOLD release/N-ch Tr.
output for watchdog timer
INT1 input/HOLD release
INT2 input/timer 0 event input
INT3 input with noise filter/timer 0

•Pull-up resistor :
Provided/Not provided

event input

•Interrupt received form, vector address
leading trailing leading

&

high

level

low

level

vector

trailing
INT0
INT1
INT2
INT3

enable
enable
enable
enable

enable
enable
enable
enable

disable

disable

enable
enable

enable

enable
disable
disable

enable

enable
disable
disable

03H

0BH

13H

1BH

No.6724-10/28

LC868116/12/08A

Name No. I/O Function description Option
C1 to C16 65-50 O LCD o u tput terminals fo r common ­S1 to S48 2-49 O LCD output terminals for segment LCD output terminals :

segment/common

RES

130 I Reset -

ADLC 128 O Address control signal for external memory -

EROE

XT1 131 I Input for 32.768kHz crystal oscillation

129 O Enable signal of external ROM output -

-

In case of non use, connect to VDD

XT2 132 O Output for 32.768kHz crystal oscillation

-

In case of non use, should be left unconnected

CF1 134 I Input for ceramic resonator oscillation

-

In case of non use, connect to VDD

CF2 135 O Output for ceramic resonator oscillation

-

In case of non use, should be left unconnected

* Port options can be specified in a bit.

* A state of port at initial

Pin name Input/output mode A state of pull-up resistor specified at pull-up option

Port 0, 7 Input Fixed pull-up resistor exist

Ports 1, 2

Input Programmable pull-up resistor OFF

Ports 3, 5

Port 4 Input Programmable pull-up resistor ON

Name Output level

C1 to C16 VSS (Display OFF)

S1 to S48 VSS (Display OFF)

No.6724-11/28

LC868116/12/08A

V

1. Absolute Maximum Ratings at VSS=0V and Ta=25°C

Parameter Symbol Pins Conditions

Ratings

DD[V] min. typ. max.
Supply voltage VDDMAX VDD -0.3 +7.0
Input voltage

VI(1) •Ports 71,72,73

•

RES

-0.3 VDD+0.3

unit

V

VI(2) VLCD -0.3 +7.0

Output voltage

VO(1) •C1 to C16

-0.3 VLCD+0.3

•S1 to S48

VO(2) •VOUT2

-0.3 VDD+0.3

•CUP1,CUP2

-0.3 VDD+0.3

-0.3 VDD+0.3

•CMOS output

-4

mA

•At each pin

Total all pins -25

At each pin 20

Total all pins 40

C

°

Input/output
voltage
High
level
output
current

Peak
output
current
Total
output
current

Low
level
output
current

Peak
output
current

Total
output
current

Operating

VO(3)

ADLC,

EROE

VIO(1) •Ports 0,1,2,3,4,5

•Port 70

IOPH(1) •Ports 0,1,2,3,4,5

EROE

ΣIOAH(1)

•ADLC,

•Ports 0,2,3

•C1-C16,S1-S48

EROE

ΣIOAH(2)

•ADLC,
Ports 1, 4, 5 Total all pins -25

IOPL(1) •Ports 0,1,2,3,4,5

•ADLC,

EROE

IOPL(2) Port 70 At each pin 15
ΣIOAL(1)

IOAL(2)

Σ

ΣIOAL(3)

IOAL(4)

Σ
ΣIOAL(5)

IOAL(6)

Σ
ΣIOAL(7)

Port 0 Total all pins 40

•Port 2

EROE

•ADLC,
Port 3 Total all pins 40
Ports 1, 5 Total all pins 40
Port 4 Total all pins 40
Port 70 Total all pins 15
C1-C16,S1-S48 Total all pins 30

Topr -30 +70
temperature
range
Storage

Tstg -65 +150
temperature
range

Notes :
The specifications above are for a die mounted in a QIC160 type package.
However, we ship this product as a die only, not a package chip.
Therefore, the operational characteristics may vary depending on the user’s packaging techniques.

No.6724-12/28

LC868116/12/08A

2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

Operating
supply voltage
range

VDD(1)

VDD(2)

VDD

0.98µs ≤ tCYC ≤
400µs

1.9µs ≤ tCYC ≤
400µs

VDD(3)

3.9µs ≤ tCYC ≤
400µs

Hold voltage VHD VDD RAMs and the

registers hold
voltage at HOLD
mode.

VLCD VLCD

voltage
Input high

VIH(1) Port 0 (Schmitt) Output disable 2.5-6.0 0.4VDD

voltage

VIH(2) •Ports 1,2,3,4,5

Output disable 2.5 -6.0 0.75VDD VDD

•Ports 72,73
(Schmitt)

VIH(3) •Port 70 for

Port input/interrupt

Output N-channel
Tr. OFF

•Port 71

RES

•

(Schmitt)

Input low
voltage

VIH(4) Port 70 for watchdog

timer
VIL(1) Port 0 (Schmitt) Output disable 2.5-6.0 VSS 0.2VDD
VIL(2) •Ports 1,2,4,5

Output N-channel
Tr. OFF

Output disable 2.5 -6.0 VSS 0.25VDD

•Ports 72,73

(Schmitt)
VIL(3) •Port 70

Port input/interrupt

Output N-channel
Tr. OFF

•Port 71

RES

•

Operation
cycle time

VIL(4) Port 70 for watchdog

timer
tCYC

Output N-channel
Tr. OFF

memory acce ss
function
for external
memory acce ss

Oscillation
frequency
range

(Note 1)

FmCF(1) CF1, CF2 •12MHz

(ceramic resonator
oscillation)

•Refer to figure 1

FmCF(2) CF1, CF2 •6MHz

(ceramic resonator
oscillation)

•Refer to figure 1

FmCF(3) CF1, CF2 •3MHz

(ceramic resonator
oscillation)

•Refer to figure 1
FmRC RC oscillation 2.5-6.0 0.4 0.8 2.0
FsXtal XT1, XT2 •32.768kHz

(crystal oscillation)

•Refer to figure 2

Continue.

Ratings

VDD[V] min. typ. max.

4.5 6.0

unit

V

4.5 6.0

2.5 6.0

2.0 6.0

2.5-3.0 VDD 6.0 LCD display

3.0-6.0 VDD 6.0
VDD

+0.9

2.5-6.0 0.75VDD VDD

2.5-6.0 0.9VDD VDD

2.5-6.0 VSS 0.25VDD

2.5-6.0 VSS 0.8VDD

-1.0

4.5-6.0 0.98 400 excluding external

s

µ

2.5-6.0 3.9 400

4.5-6.0 1.9 400

2.5-6.0 3.9 400

4.5-6.0 11.76 12 12.24

MHz

4.5-6.0 5.88 6 6.12

2.5-6.0 2.94 3 3.06

2.5-6.0 32.768 kHz

No.6724-13/28

LC868116/12/08A

Parameter Symbol Pins Conditions

Oscillation
stabilizing
time period

(Note 1)

tmsCF(1) CF1, CF2 •12MHz

(ceramic resonator
oscillation)

•Refer to figure 3

tmsCF(2) CF1, CF2 •6MHz

(ceramic resonator
oscillation)

•Refer to figure 3

(ceramic resonator
oscillation)

•Refer to figure 3

tssXtal XT1, XT2 •32.768kHz

(crystal oscillation)

•Refer to figure 3

(Note 1) The oscillation constant is shown on table 1 and table 2.

Ratings

VDD[V] min. typ. max.

4.5-6.0 0.02 0.3

4.5-6.0 0.02 0.3

4.5-6.0 0.1 1 tmsCF(3) CF1, CF2 •3MHz

2.5-6.0 0.1 3

4.5-6.0 1 1.5

2.5-6.0 1 3

unit

ms

s

No.6724-14/28

LC868116/12/08A

3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

Input high
current

IIH(1) •Ports 1,2,3,4,5

•Port 0 without
pull-up MO S Tr.

•Out put dis a ble

•Pull-up MOS Tr. OFF

•VIN=VDD
(including the off­ leak current of the
output Tr.)

IIH(2) Port 7 without

pull-up MOS Tr.

•Output Nch Tr. OFF

•VIN=VDD
(including the off­ leak current of the
output Tr.)
VIN=VDD 2.5-6.0 1

•Out put dis a ble

•Pull-up MOS Tr. OFF

•VIN=VSS

Input low
current

IIH(3)

RES

IIL(1) •Ports 1,2,3,4,5

•Port 0 without
pull-up MO S Tr.

(including the off­ leak current of the
output Tr.)

IIL(2) Port 7 without

pull-up MOS Tr.

•Output Nch Tr. OFF

•VIN=VSS
(including the off­ leak current of the
output Tr.)

Output high
voltage

Output low
voltage

IIL(3)
VOH(1) IOH=-10mA 4.5-6.0 VDD-2.2

VOH(2)
VOH(3) IOH=-1.0mA 4.5-6.0 VDD-1
VOH(4)

VOL(1) IOL=10mA 4.5-6.0 1.5
VOL(2) IOL=1.6mA 4.5-6.0 0.4

RES

Port 0 of
CMOS output

•Ports 1,2,3,4,5 of
CMOS output

•ADLC,

EROE

•Ports 0,1,2,3,4,5

•ADLC,

EROE

VOL(3)

VIN=VSS 2.5-6.0 -1

IOH=-1mA 2.5-6.0 VDD-0.4

IOH=-0.1mA 2.5-6.0 VDD-0.5

•IOL=1.0mA

•The current of any
measurement pin is
not over 1mA.

Tr. resistor
Hysteresis

voltage

VOL(4) IOL=1mA 4.5-6.0 0.4
VOL(5)
Rpu •Ports 0,1,2,3,4,5

VHIS •Ports 0,1,2,3,4,5

Port 70

•Port 7

•Port 7

•

RES

IOL=0.5mA 2.5-6.0 0.4
VOH=0.9VDD

Output disable 2.5-6.0 0.1VDD V

Pin capacitance CP All pins •f=1MHz

•Unmeasurement
terminals for the
input are set to
VSS level.

•Ta=25°C

Ratings

VDD[V] min. typ. max.

2.5-6.0 1

unit

A

µ

2.5-6.0 1

2.5-6.0 -1

2.5-6.0 -1

V

2.5-6.0 0.4

4.5-6.0 15 40 70 Pull-up MOS

kΩ

2.5-4.5 25 60 120

2.5-6.0 10 pF

No.6724-15/28

LC868116/12/08A

4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

Cycle tCKCY(1) 2
Low Level

tCKL(1) 1

SCK0,
SCK1

Refer to figure 5. 2.5-6.0

pulse width
High Level

Input clock

pulse width
Cycle tCKCY(2) 2

Serial clock

Low Level
pulse width
High Level

Output clock

pulse width

Data set up time

Data hold time

Serial input

Output delay time
(Serial clock is
external clock)

tCKH(1)

SCK0,

tCKL(2) 1/2

SCK1

•Use pull-up
resistor (1kΩ)
when Nch open-

tCKH(2)

drain output.

•Refer to figure 5.

tICK

•SI0,SI1

•SB0,SB1

•Data set-up to
SCK0,1

•Data hold from

tCKI

SCK0,1

•Refer to figure 5.

tCKO(1) •SO0,SO1

•SB0,SB1

•Data set-up to
SCK0,1

•Use pull-up
resistor (1kΩ)
when Nch open­ drain output.

•Refer to figure 5.
Output delay time
(Serial clock is

Serial output

internal clock)

tCKO(2) •SO0,SO1

•SB0,SB1

•Data hold from

SCK0,1

•Use pull-up

resistor (1kΩ)
when Nch open­ drain output.

•Refer to figure 5.

Ratings

VDD[V] min. typ. max.

1

2.5-6.0

tCKCY

1/2

tCKCY

4.5-6.0 0.1

2.5-6.0 0.4

4.5-6.0 0.1

2.5-6.0 0.4

4.5-6.0 7/12
tCYC

+0.2

2.5-6.0 7/12
tCYC

+1

4.5-6.0 1/3
tCYC

+0.2

2.5-6.0 1/3
tCYC

+1

unit

tCYC

s

µ

No.6724-16/28

LC868116/12/08A

5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

High/low level
pulse width

tPIH(1)
tPIL(1)

•INT0, INT1

•INT2/T0IN

•Interrupt acceptable

•Timer0-countable

•Refer to figure 6
tPIH(2)
tPIL(2)

•INT3/T0IN

(The noise rejection

•Interrupt acceptable

•Timer0-countable
clock is selected to
1/1.)

•Refer to figure 6

tPIH(3)
tPIL(3)

•INT3/T0IN
(The noise rejection

•Interrupt acceptable

•Timer0-countable
clock is selected to
1/16.)

•Refer to figure 6

tPIH(4)
tPIL(4)

•INT3/T0IN
(The noise rejection

•Interrupt acceptable

•Timer0-countable
clock is selected to
1/64.)

•Refer to figure 6

tPIL(5)

•

RES

Reset acceptable 2.5-6.0 200

•Refer to figure 6

Ratings

VDD[V] min. typ. max.

2.5-6.0 1

2.5-6.0 2

2.5-6.0 32

2.5-6.0 128

unit

tCYC

µs

No.6724-17/28

LC868116/12/08A

6. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V

Parameter Symbol Pins Conditions

Current
drain
during basic
operation

(Note 2)

IDDOP(1) •FmCF=12MHz

VDD

Ceramic resonator
oscillation

•FsXtal=32.768kHz
crystal oscillation

•System clock :
12MHz

•Internal RC
oscillation stops

IDDOP(2) •FmCF=6MHz

Ceramic resonator
oscillation

•FsXtal=32.768kHz
crystal oscillation

•System clock :
6MHz

•Internal RC

oscillation stops
IDDOP(3) 0 3 9
IDDOP(4) 1
IDDOP(5)

•FmCF=3MHz

Ceramic resonator

oscillation

•FsXtal=32.768kHz

crystal oscillation

•System clock :

3MHz

•Internal RC

oscillation stops
IDDOP(6) 0 0.7 3.4

IDDOP(7) 1
IDDOP(8) 0 0.4 2.8
IDDOP(9)

•FmCF=0Hz

(when oscillation

stops)

•FsXtal=32.768kHz

crystal oscillation

•System clock :

RC oscillation
IDDOP(10) 0 38 150

IDDOP(11) 1
IDDOP(12) 0 15 70
IDDOP(13)

•FmCF=0Hz

(when oscillation

stops)

•FsXtal=32.768kHz

crystal oscillation

•System clock :

32.768kHz

•Internal RC

oscillation stops

*OSCR : Bit 7 of the oscillation control register.

Continue.

Ratings

OCR7 VDD[V] min. typ. max.

0 4.5-6.0 10 25

1 4.5-6.0 10 25

4.5-6.0
6 15

0 2.5-4.5 1.5 5

4.5-6.0

1.2 4.5

2.5-4.5

1

0.8 3.6

4.5-6.0
60 300

2.5-4.5

1

25 120

unit
mA

A

µ

No.6724-18/28

LC868116/12/08A

Parameter Symbol Pins Conditions

Current
drain in
HALT mode

(Note 2)

IDDHALT(1) •HALT mode

VDD

•FmCF=12MHz
Ceramic resonator
oscillation

OCR7 VDD[V] min. typ. max.

Ratings

0 4.5-6.0 5.0 14

•FsXtal=32.768kHz
crystal oscillation

•System clock :
12MHz

•Internal RC
oscillation stops

IDDHALT(2) •HALT mode

1 4.5-6.0 5.0 14

•FmCF=6MHz
Ceramic resonator
oscillation

•FsXtal=32.768kHz
crystal oscillation

•System clock :
6MHz

•Internal RC

oscillation stops
IDDHALT(3) 0 2.3 7
IDDHALT(4) 1
IDDHALT(5)

•HALT mode

•FmCF=3MHz

Ceramic resonator

4.5-6.0

4.5 15

0 2.5-4.5 0.8 4

oscillation

•FsXtal=32.768kHz

crystal oscillation

•System clock :

3MHz

•Internal RC

oscillation stops
IDDHALT(6) 0 400 1600
IDDHALT(7) 1
IDDHALT(8) 0 200 1300
IDDHALT(9)

•HALT mode

•FmCF=0Hz

(when oscillation

stops)

4.5-6.0
600 2400

2.5-4.5

1

350 1500

•FsXtal=32.768kHz
crystal oscillation

•System clock :
RC oscillation

IDDHALT(10) 0 25 100
IDDHALT(11) 1
IDDHALT(12) 0 8 55
IDDHALT(13)

•HALT mode

•FmCF=0Hz
(when oscillation
stops)

4.5-6.0
36 140

2.5-4.5

1

12 85

•FsXtal=32.768kHz
crystal oscillation

•System clock :

32.768kHz

•Internal RC
oscillation stops

drain in
HOLD mode

IDDHOLD(1) 4.5-6.0 0.05 30 Current
IDDHOLD(2)

VDD HOLD mode

2.5-4.5 0.02 20

(Note 2)
(Note 2) The currents of the output transistors, pull-up transistors and the LCD bleeder resistors are ignored.
Refer to figure 7.

unit
mA

A

µ

No.6724-19/28

LC868116/12/08A

7. LCD Voltage and LCD Driver Characteristics at Ta=-30°C to +70°C, VSS=0V

Parameter Symbol Pins, Conditions

|VD1|
voltage (X : 1 to 5)
(i : 1 to 16)

•Only a Ci terminal for – 1 5µA

•LCD display ON

•1/5 bias

VDD[V] min. typ. max.

2.9 120 VX-Ci drop

5.0 200

•V5=VDD

2.9 -120 VX-Ci drop

5.0 -200

voltage (X : 1 to 5)
(i : 1 to 16)

|VD2|

•Only a Ci terminal for + 15µA

•LCD display ON

•1/5 bias

•V5=VDD

2.9 120 VX-Si drop

5.0 200

voltage (X : 1 to 5)
(i : 1 to 48)

|VD3|

•Only a Si terminal for -15µA

•LCD display ON

•1/5 bias

•V5=VDD

2.9 -120 VX-Si drop

5.0 -200

voltage (i : 1 to 5)
(i : 1 to 48)

|VD4|

•Only a Si terminal for +15µA

•LCD display ON

•1/5 bias

•V5=VDD

•LCD clock frequency=0Hz

•LCD display ON

•1/5 bias

•V5=VDD

•Refer to figure 9

2.9 V4 output voltage VV4

5.0

2.9 V3 output voltage VV3

5.0

2.9 V2 output voltage VV2

5.0

2.9 V1 output voltage VV1

5.0
LCD display
current

ILCD2

•LCD display ON

•1/5 bias

•VLCD=VDD

•V1-V5 are opened

20kΩ
mode

4KΩ
mode

2.9 15 29 60

2.9 75 150 300

•Refer to figure 8
Step-up output
voltage

VOUT2

•V1-V5 resistor=20kΩ

•LCD display ON

•LVCR0=1 (doubler)

•VOUT2

•VDD=2.5 to 3.0V

•C5=C6=0.1µF

•Refer to figure 10

•IL=100µA

•step-up clock
: RC oscillation

•IL=500µA

•step-up clock
: RC oscillation

•IL=100µA

2.7 4.4 4.6 5.4

2.7 4.2 4.5 5.4

2.7 4.3 4.5 5.4

•step-up clock
: crystal
oscillation

•IL=500µA

2.7 4.0 4.3 5.4

•step-up clock
: crystal

oscillation
Contrast current
(VLCD termin al)

ILC1 VCCR=1 5 0.8 1.6 3.2
ILC2 VCCR=2 5 0.4 0.8 1.6
ILC3 VCCR=4 5 0.2 0.4 0.8
ILC4 VCCR=8 5 0.1 0.2 0.4
ILC5

•LCD display ON

•V5=VDD-0.5V

•VLCD=VDD

•Refer to figure 11
VCCR=10H 5 0.05 0.1 0.2

VCCR : The LCD contrast control register
LVCR0 : Bit 0 of the LCD bias control register

Ratings

unit
mV

0.75VDD 0.80VDD 0.85VDD

V

0.55VDD 0.60VDD 0.65VDD

0.35VDD 0.40VDD 0.45VDD

0.15VDD 0.20VDD 0.25VDD

5 25 50 100 ILCD1

µ

5 125 250 500

V

3 5.6 5.8 6.0

3 5.2 5.6 6.0

3 5.4 5.7 6.0

3 5.0 5.4 6.0

mA

µA

A

No.6724-20/28

LC868116/12/08A

Table 1. Ceramic resonator oscillation recommended constant (main clock)

Oscillation type Maker Oscillator C1 C2

12MHz ceramic resonator

oscillation

CSA12.0MT 33pF 33pF Murata

CST12.00MTW on chip

Kyocera KBR-12.0M 33pF 33pF

6MHz ceramic resonator

oscillation

Kyocera

Murata
on chip

on chip

3MHz ceramic resonator

oscillation

CSA3.0MG 33pF 33pF Murata

CST3.0MGW on chip

Kyocera KBR-3.0MS 47pF 47pF

* Both C1 and C2 must use K rank (±10%) and SL characteristics.

Table 2. Crystal oscillation guaranteed constant (sub clock)

Oscillation type Maker Oscillator C3 C4

CITIZEN CFS-308 18pF 18pF 32.768kHz crystal

oscillation

SII DT-VT-200 18pF 18pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)

(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close

to the oscillation pins as possible with the shortest possible pattern length.

•If you use other oscillators herein, we provide no guarantee for the characteristics.

CF1 CF2 XT1 XT2

CF

C2 C1

X’tal

C4 C3

Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit

No.6724-21/28

LC868116/12/08A

Power supply

RES

Reset time

VDD
VDD limit
0V

Internal RC oscillation

CF1, CF2

XT1, XT2

tmsCF

tssXtal

Operation mode

Unstable

Execution of instructions Reset

Reset time and oscillation stable time

HOLD release signal

Valid

Internal RC oscillation

CF1, CF2

tmsCF

tssXtal

XT1, XT2

Operation mode

HOLD

Execution of instructions

HOLD release signal and oscillation stable time

Figure 3 Oscillation stable time

No.6724-22/28

LC868116/12/08A

VDD

RES

R

RES

RES

C

(Note) Fix the value of CRES, RRES that is

sure to reset until 200µs, after Power
supply has be en over inferior limit o f
supply voltage.

Figure 4 Reset circuit

0.5VDD

<AC Timing Point>

tCKCY

tCKH tCKL

VDD

SCK0
SCK1

SI0
SI1

tCKO

SO0, SO1

SB0, SB1

tCKI tICK

<Timing>

1KΩ

50pF

<Test Load>

Figure 5 Serial input / output test condition

tPIH tPIL

Figure 6 P u l se input t iming condi ti on

No.6724-23/28

LC868116/12/08A

VDD

A

VDD

OPEN

VDD

CUP1
CUP2

VOUT2

CF1 XT2CF2 XT1

VSS

VSS

V5

V1

VLCD

OPEN

VDD

CUP1
CUP2

VOUT2

CF1 XT2CF2 XT1

VSS

VSS

V5

OPEN

V1

VLCD

A

VDD

Figure 7 Current dissipation measurement Figure 8 LCD display current measurement

OPEN

VDD
CUP1
CUP2

VOUT2
VLCD

VDD

VSSCF1 XT2CF2 XT1

VDD

V5
V4

V1

IL

VDD

VDD

VOUT2
CUP1
CUP2

CF1 XT2CF2 XT1

VSS

V5

OPEN

V1

VLCD

VSS

V

V

VSS

Figure 9 Output voltage of V1-V4 measurement Figure 10 Step up output voltage measurement

VDD

A

OPEN

VDD

CUP1
CUP2

VOUT2

CF1 XT2CF2 XT1

VSS

VSS

VLCD

V5

VDD-0.5V

V4

OPEN

V1

Figure 11 Contrast current measurement

No.6724-24/28

LC868116/12/08A

8. AC Characteristics at Ta=-30°C to +70°C, VSS=0V

Load capacity : 100pF (Port 0, ADLC,
Load capacity : 80pF (Output terminals except above)

*tCLCL=1/12 tCYC

External program memory timing

Parameter Symbol Pads and Conditions

EROE

EROE

EROE

pulse width

! address in

For

tELEH

From

For

tEHAV

EROE

EROE

Refer to figure 12.

1 tCYC

SCLK

tLHLL

ADLC

EROE

Port 0

tAVLL

A7-A0

tLLEL

tLLAX

tELEH

tELIV

tEHIX

EROE )

tEHAV

IR A7-A0

Ratings

VDD[V] min. max.

4.5 - 6.0 2tCLCL-40 ADLC pulse width tLHLL

2.5 - 6.0 2tCLCL-160

4.5 - 6.0 tCLCL-40 Address settling time tAVLL For ADLC

2.5 - 6.0 tCLCL-160

4.5 - 6.0 tCLCL-35 Address hold time tLLAX For ADLC

2.5 - 6.0 tCLCL-140

4.5 - 6.0 tCLCL-25 ADLC ! control signal tLLEL

2.5 - 6.0 tCLCL-100

4.5 - 6.0 3tCLCL-35

2.5 - 6.0 3tCLCL-140

4.5 - 6.0 3tCLCL-125 Data delay time tELIV

2.5 - 6.0 3tCLCL-400

4.5 - 6.0 0 Data hold time tEHIX

2.5 - 6.0 0

4.5 - 6.0 tCLCL-8

2.5 - 6.0 tCLCL-32

tCLCL

unit

ns

Port 2

Port 3

EROE

Port 0

Port 2

Port 3

Port 5

A15-A8

A7-A0

A7-A0 DATA

A15-A8

A7-A0

Bank

A15-A8

Figure 12 Timing of the external Program Memory/Data Memory

A7-A0

No.6724-25/28

LC868116/12/08A

Ext ernal data memory timing

Parameter Symbol Pads and Conditions

RD

pulse width

WR

pulse width

tRLRH

tWLWH

Data address hold time tLLAX

For ADLC (at STX)

RD

RD

RD

From

From

From

tAVLL For ADLC

time
ADLC ! control signal

Data in

WR

=1

Control signal ! ADLC

tLLWL

tQVWH

tWHLH

For

For

For

From

For

For

RD

WR

WR

RD

WR

WR

Refer to figure 13.

tCLCL

Ratings

VDD[V] min. max.

4.5 - 6.0 6tCLCL-80

2.5 - 6.0 6tCLCL-320

4.5 - 6.0 6tCLCL-80

2.5 - 6.0 6tCLCL-320

4.5 - 6.0 2tCLCL-35 For ADLC (at LDX)

2.5 - 6.0 2tCLCL-140

4.5 - 6.0 2tCLCL-35

2.5 - 6.0 2tCLCL-140

4.5 - 6.0 5tCLCL-125 Data delay time tRLDV

2.5 - 6.0 5tCLCL-400

4.5 - 6.0 0 Data hold time tRHDX

2.5 - 6.0 0

4.5 - 6.0 2tCLCL-70 2tCLCL+70 Data floating time tRHDZ

2.5 - 6.0 2tCLCL-280 2tCLCL+280

4.5 - 6.0 tCLCL-40 Data address setting

2.5 - 6.0 tCLCL-160

4.5 - 6.0 3tCLCL-50 3tCLCL+50 tLLRL

2.5 - 6.0 3tCLCL-200 3tCLCL+200

4.5 - 6.0 3tCLCL-50 3tCLCL+50

2.5 - 6.0 3tCLCL-200 3tCLCL+200

4.5 - 6.0 tCLCL-60 Data settling time tQVWL

2.5 - 6.0 tCLCL-240

4.5 - 6.0 7tCLCL-140

2.5 - 6.0 7tCLCL-560

4.5 - 6.0 tCLCL-50 Data hold time tWHQX

2.5 - 6.0 tCLCL-200

4.5 - 6.0 tCLCL-50 tCLCL+50 tRHLH

2.5 - 6.0 tCLCL-200 tCLCL+200

4.5 - 6.0 tCLCL-50 tCLCL+50

2.5 - 6.0 tCLCL-200 tCLCL+200

1 tCYC

unit

ns

SCLK

ADLC

EROE

RD

Port 0

WR

Port 0

Port 2

Port 5

Port 3

tLLRL

tAVLL tLLAX

(at reading)

A7-A0

tLLWL tWLWH tWHLH

tLLAX

(at writing)

A7-A0 DATA

tQVWL tWHQX

tRLRH tRHLH

tRLDV

tRHDZ

tRHDX

DATA Z

tQVWH

A15-A8

Bank

A7-A0

Figure 13 Timing of the external RAM

No.6724-26/28

LC868116/12/08A

2

Evaluation Sample (ES)

•

The factory shipment of this microcomputer is chip.
But there are two types of shipment of evaluation sample.
One type is chip and the other is package (QIC160).
If you selected package type, please refer to the following pin assignment and layout, and make the user target board.

• Pin Assignment of evaluation sample (Package type)

VDD
P30

P31
P32
P33
P34
P35
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
P20
P21
P22
P23
P24
P25
P26
P27

ADLC
EROM

RES
XT1
XT2

VSS

CF1
CF2

125

130

140

150

155

P50

1

P51

P52

P53

115

P54

P55

P56

P57

P17

P16

P15

P14

P13

P12

P11

110

100

LC868116-QIC160

10

20

P10

P73

P72

P71

P70

P47

P46

30

P44

90

P43

P42

P41

P40

35

VSS

85

CUP1

CUP2

VOUT

75

70

60

50

45

VLCD

V5
V4
V3
V2
V1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36

S35

S2S3S1

VDD

S4S5S6S7S8

S9

S11

S10

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

No.6724-27/28

LC868116/12/08A

• Layout of evaluation sample (Package type) : QIC160

No.6724-28/28

PS