Page 1
Ordering number : ENN*6723
LC868016/12/08A
8-Bit Single Chip Microcontroller with
16/12/08K-Byte ROM and 640-Byte RAM On Chip
Preliminary
Overview
The LC868016A/12A/08A microcontrollers are 8-bit single chip microcontrollers with the following on-chip functional
blocks :
- CPU : Operable at a minimum bus cycle time of 0.5µs (microseconds)
- On-chip ROM maximum capacity : 16K bytes
- On-chip RAM capacity : 640 bytes
- Dot-matrix liquid crystal display (LCD) automatic display controller / driver
- Externa l memory
- 16-bit timer / counter (or two 8-bit timers)
- 16-bit timer / PWM (or two 8-bit timers)
- Two 8-bit synchronous serial -interface circuits
- 13-source 9-vectored interrupt system
All of the above functions are fabricated on a single chip.
CMOS IC
Ver.1.12
61298
91400 RM (IM) HO No.6723-1/28
Page 2
LC868016/12/08A
Features
(1) Read Only Memory (ROM) : LC868016A 16384 × 8 bits
: LC868012A 12288
: LC868008A 8192
8 bits
×
8 bits
×
(2) Random Access Memory (RAM) : 512 × 8 bits (calculation area)
128
8 bits (display area)
×
(3) Bus Cycle Time / Instruction Cycle Time
Bus cycle time Instruction cycle time System clock oscillation Oscillation frequency Voltage Note
12MHz OCR7=0 0.5µs 1µs Ceramic (CF)
6MHz
3MHz OCR7=0 2.0µs 4µs Ceramic (CF)
1.5MHz
7.5µs 15µs OCR7=0
3.8µs 7.5µs
183µs 366µs OCR7=0
91.5 183µs
Internal RC 800kHz 2.5-6.0V
Crystal (XTAL) 32.768kHz 2.5-6.0V
4.5-6.0V
OCR7=1
2.5-6.0V
OCR7=1
OCR7=1
OCR7=1
* Bus cycle time means ROM-read period.
OCR7 : Bit-7 of the oscillation control register.
(4) Ports
- Input / output ports : 6 ports (47 terminals)
Input/output port programmable in a nibble : 1 port (8 terminals)
Input/output port programmable every function unit : 1 port (7 terminals)
Input/output port programmable in a bit : 4 ports (32 terminals)
- Input port : 1 port (4 terminals)
- Ports at external memory mode
1. External Latch
Port 0 : Address output of lower 8-bit, input/output of data
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
2. No External Latch
Port 0 : Input/output of data
Port 3 : Address output of lower 8-bit
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
(Set whether the external latch is used or not by program.)
- LCD segment driver output ports : 48 terminals
(Function change available : segment/common)
- LCD common driver output ports : 16 terminals
(1/64 duty maximum : at using segment output ports as common output by mask option)
(5) External memory access
- Externa l progra m memor y acce ss function
External program memory capacity : 64K bytes
Programable switch internal program/external program
(At initial : Internal program)
Enable/disable control of external program --> internal program memory switch
No.6723-2/28
Page 3
LC868016/12/08A
Ports
Port 2 : Address output of upper 8-bit
Uses
EROE terminal (OE signal of the external ROM)
1. Using the external latch
Port 0 : Address output of lower 8-bit, data input port
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use the external latch
Port 0 : Input port of data
Port 3 : Address output of lowe r 8-bit
- External data memory access function
Using the LDC instruction
External memory capacity : 16M bytes
1. Internal prog ram memory
Switch the reference of internal ROM data/external ROM data by program.
2. External program memory
Reference external ROM data only.
Ports
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
Uses
EROE terminal (OE signal of the external ROM)
1. Using external latch
Port 0 : Address output of lower 8-bit, input port of data
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use external latch
Port 0 : Input port of data
Port 3 : Address output of lowe r 8-bit
- External RAM memory access function
Using the LDX, STX instruction
External memory capacity : 16M bytes
Ports
Port 2 : Address output of upper 8-bit
Port 5 : Bank address output
Uses the P46 terminal (
Uses the P47 terminal (
OE signal of external RAM) : the LDX instruction execution
WE signal of external RAM) : the STX instruction execution
1. Using the external latch circuit
Port 0 : Address output of lower 8-bit, input/output port of data
Uses the ADLC terminal (latch clock of the lower 8-bit address signal)
2. Not use the external latch circuit
Port 0 : Input/output port of data
Port 3 : Address output of lowe r 8-bit
(6) LCD automatic display controller
- Display duty : 1/1 - 1/64 duty
- Display bias : 1/4, 1/5, 1/7, 1/9 bias
- Programmable character display / graphic display
- Character display
1. On-chip char acter generator ROM
ROM capacity : 8960 bits
Character font : 5 × 7 dots
Number of Characters : 256
2. LCD instruction
Display : ON/OFF
Cursor : ON/OFF/BLINK
Character blink : ON/OFF
Character scroll : Control by specified starting address
No.6723-3/28
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LC868016/12/08A
- Graphic display
LC868000 series : 1024 dots Maximum
External segment driver : Enable to extend of LCD drive
- LCD contrast
LCD display contrast programmable
- LCD display power supply
Doubler/Tripler circuit programmable
Doubler voltage in the tripler mode must not be used for LCD display power supply
If doubler voltage is used for LCD display power supply, the doubler mode must be selected by user program.
- LCD driver
Following three kinds of combination can be selected by mask option
No. Segment output port Common output port
1 48 16
2 32 32
3 0 64
(7) Serial-interface
- Two 8-bit serial-interface circuits
LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two serial-interface circuits
(8) Timers
- Timer0 (T0L, T0H)
16-bit timer / counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
- Timer1 (T1L, T1H)
16-bit timer / PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock)
The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable ; 4KHz, 2KHz
(10) Remote control receiver circuit (using P73/INT3/T0IN terminal)
- Noise rejection available
- The interrupt polarity selectable
(11) Watchdog timer
- The watchdog timer is taken on RC outside. (using P70/INT0 terminal)
- Watchdog timer operation selectable : interrupt system, system reset
No.6723-4/28
Page 5
LC868016/12/08A
(12) Interrupts system
- 13-source 9-vectored interrupts :
1. External interrupt INT0 (includes watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, timer / counter T0L (timer 0 lower 8 bits)
4. External interrupt INT3, base timer
5. Timer / counter T0H (timer 0 upper 8-bit)
6. Timer T1L (timer 1 lower 8-bit) , Timer T1H (timer 1 upper 8-bit)
7. Serial interface SIO0
8. Serial interface SIO1
9. Port 0 or Port 3
- Interrupt priority contr ol availa b le
Microcomputer allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can
specify a low level or a high level interrupt priority from INT2/T0L through port 0 or port 3 ( the above interrupt
number from three through nine). It can also specify a low level or the highest level interrupt priority to INT0 and
INT1.
(13) Sub-routine stack levels
- 128 levels (Max.) : stack area included in RAM area
(14) Multiplication and division
- 16 bits × 8-bit (7 instruction cycle times)
- 16 bits / 8-bit (7 instruction cycle times)
(15) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock, for the LCD display and for the step-up circuit.
- On-chip CF oscillation circuit using for the system clock and for the LCD display.
- On-chip crystal oscillation circuit using for the system clock, for time-base clock and for the LCD display.
(16) Standby function
- HALT mode function
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This operation mode can be released by the interrupt request signals or setting to low level for the reset terminal
(
RES).
- HOLD mode function
The HOLD mode is used to freeze all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations:
• Reset terminal (
RES) set to low level.
• Set to assigned level to INT0/1 terminals.
• Set to assigned level to Port 0/3.
(17) Factory shipment
- Chip
QIC160 package shipping available for sample evaluation.
(18) Development support tools
- Evaluation (EVA) chip : LC868099
- Emulator : EVA86000 + ECB868000 (Evaluation chip board)
No.6723-5/28
Page 6
Pin Assignment
LC868016/12/08A
VDD
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
CF2
CF1
VSS
XT2
XT1
RES
EROE
ADLC
P27
P26
P25
P24
P23
P22
P21
P20
P07
P06
P05
1
S1
S2
S3
S4
S5
S6
S7
S8
S9
(X, Y) = (0, 0)
36
P04
P03
P02
P01
P00
P37
P36
P35
P34
P33
P32
P31
P30
VDD
106
P50
P51
P52
P53
P54
P55
P56
P57
P17/PWM
P16/BUZ
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P70/INT0
P47/WR
P46/RD
P44/FRM
P43/M
P42/DO
P41/CL2
P40/CL1
VSS
CUP1
CUP2
VOUT2
VOUT3
TEST
TEST
66
C7
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
C16
C15
C14
C13
C9C8C6C5C4C3C2C1V1V2V3V4V5
C12
C11
C10
VLCD
No.6723-6/28
Page 7
LC868016/12/08A
Pad Name and coordinates table
Pad
No.
10 S9 -2960 1205 56 C10 385 -3630 102 P53 2845 2115
11 S10 -2960 1045 57 C9 550 -3630 103 P52 2845 2295
12 S11 -2960 880 58 C8 710 -3630 104 P51 2845 2475
13 S12 -2960 720 59 C7 875 -3630 105 P50 2845 2650
14 S13 -2960 555 60 C6 1035 -3630 106 VDD 2965 3530
15 S14 -2960 395 61 C5 1200 -3630 107 P30 2800 3530
16 S15 -2960 230 62 C4 1360 -3630 108 P31 2620 3530
17 S16 -2960 70 63 C3 1525 -3630 109 P32 2445 3530
18 S17 -2960 -95 64 C2 1685 -3630 110 P33 2265 3530
19 S18 -2960 -255 65 C1 1850 -3630 111 P34 2085 3530
20 S19 -2960 -420 66 V1 2055 -3445 112 P35 1905 3530
21 S20 -2960 -580 67 V2 2220 -3445 113 P36 1730 3530
22 S21 -2960 -745 68 V3 2380 -3445 114 P37 1550 3530
23 S22 -2960 -905 69 V4 2545 -3445 115 P00 1370 3530
24 S23 -2960 -1070 70 V5 2705 -3445 116 P01 1190 3530
25 S24 -2960 -1230 71 VLCD 2870 -3445 117 P02 1015 3530
26 S25 -2960 -1395 72 TEST 2915 -3180 118 P03 835 3530
27 S26 -2960 -1555 73 TEST 2915 -2995 119 P04 655 3530
28 S27 -2960 -1720 74 VOUT3 2820 -2810 120 P05 475 3530
29 S28 -2960 -1880 75 VOUT2 2820 -2650 121 P06 300 3530
30 S29 -2960 -2045 76 CUP2 2820 -2485 122 P07 120 3530
31 S30 -2960 -2205 77 CUP1 2820 -2325 123 P20 -60 3530
32 S31 -2960 -2370 78 VSS 2845 -2120 124 P21 -240 3530
33 S32 -2960 -2530 79 P40 2845 -1945 125 P22 -415 3530
34 S33 -2960 -2695 80 P41 2845 -1765 126 P23 -595 3530
35 S34 -2960 -2855 81 P42 2845 -1585 127 P24 -775 3530
36 S35 -2865 -3630 82 P43 2845 -1410 128 P25 -955 3530
37 S36 -2700 -3630 83 P44 2845 -1230 129 P26 -1130 3530
38 S37 -2540 -3630 84 P46 2845 -1050 130 P27 -1310 3530
39 S38 -2375 -3630 85 P47 2845 -870 131 ADLC -1490 3530
40 S39 -2215 -3630 86 P70 2845 -690 132
41 S40 -2050 -3630 87 P71 2845 -525 133
42 S41 -1890 -3630 88 P72 2845 -365 134 XT1 -2025 3530
43 S42 -1725 -3630 89 P73 2845 -200 135 XT2 -2205 3530
44 S43 -1565 -3630 90 P10 2845 -40 136 VSS -2385 3530
45 S44 -1400 -3630 91 P11 2845 140 137 CF1 -2560 3530
46 S45 -1240 -3630 92 P12 2845 320 138 CF2 -2740 3530
Name
1 VDD -2960 2695 47 S46 -1075 -3630 93 P13 2845 500
2 S1 -2960 2505 48 S47 -915 -3630 94 P14 2845 675
3 S2 -2960 2345 49 S48 -750 -3630 95 P15 2845 855
4 S3 -2960 2180 50 C16 -590 -3630 96 P16 2845 1035
5 S4 -2960 2020 51 C15 -425 -3630 97 P17 2845 1215
6 S5 -2960 1855 52 C14 -265 -3630 98 P57 2845 1400
7 S6 -2960 1695 53 C13 -100 -3630 99 P56 2845 1580
8 S7 -2960 1530 54 C12 60 -3630 100 P55 2845 1760
9 S8 -2960 1370 55 C11 225 -3630 101 P54 2845 1935
Coordinates Coordinates Coordinates
Xµm Yµm
Pad
No.
Name
Xµm Yµm
Pad
No.
Name
EROE
RES
Xµm Yµm
-1670 3530
-1845 3530
Note ; Connect the substrate of chip to VDD (or open).
No.6723-7/28
Page 8
System Bl ock Diagram
LC868016/12/08A
Base Timer
SIO0
SIO1
Timer 0
Interrupt Control
Standby Control
CF
RC
Clock
X'tal
Generator
Bus Interface
Port 1
Port 7
IR PLA
ROM
PC
ACC
B Register
C Register
ALU
Timer 1
INT0-3
Noise Rejection Filter
XRAM
128 Bytes
CGROM
LCD Display
Controller
LCD Driver
Port 2
Port 3
Port 4
Port 5
EXT Register Watchdog Timer
PSW
RAR
RAM
Stack Pointer
Port 0
No.6723-8/28
Page 9
LC868016/12/08A
Pin Description
Name No. I/O Function description Option
VSS 78,136 - Power terminal (-) VDD 1,106 - Power terminal (+) VLCD 71 - Power terminal (-) for LCD driver V1 to 5 66-70 - Voltage supply terminals to LCD drivers VOUT2,3 75,74 - Output terminals for doubler, tripler CUP1,2 77,76 - Capacitor connecting terminals for doubler, tripler Port0
P00 to P07
Port1
P10 to P17 90-97
Port2
P20 to P27 123-130
Port3
P30 to P37 107-114
115-122
I/O •8-bit input/output port
•Input/output can be specified in 4-bit
•External memory mod e
1. EXT resistor bit 2=0
Address output of lower 8-bit, input/output
of data
2. EXT resistor bit 2=1
•Input/output of data
•Input for key interrupt (P30INT=0)*
•8-bit input/output port
I/O
•Input/output can be specified in a bit
•Another functions
P10
I/O •8-bit input/output port
•Input/output can be specified in a bit
•External memory mod e
Address output of upper 8-bit
I/O •8-bit input/output port
•Input/output in a bit
•External memory mod e
1. EXT resistor bit 2=0 : input/output port
2. EXT resistor bit 2=1 : address output of lower
8-bit for external memory
•Input for key interrupt (P30INT=L)*
SIO0 data output
P11
SIO0 data input, bus input/output
P12
SIO0 clock input/output
P13
SIO1 data output
P14
SIO1 data input, bus input/output
P15
SIO1 clock input/output
P16
Buzzer output
P17
Timer 1 output (PWM output)
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/ N-ch open drain
•Output form :
CMOS/ N-ch open drain
•Output form :
CMOS/ N-ch open drain
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/ N-ch open drain
*P30INT : Bit 0 of Port 3 interrupt control register.
No.6723-9/28
Page 10
LC868016/12/08A
Name No. I/O Function description Option
Port4
P40 to P44
P46, P47
Port5
P50 to P57 105-98
Port7
P70 to P73
79-83
84,85
86-89
•7-bit input/output port
I/O
•Input/output can be specified each upper
2 bits and lower 5 bits
•Another functions
P40
(P40-P44 : LCD display extend signal,
P46, P47 : External RAM access signal)
I/O •8-bit input/output port
•Input/output in bit unit
•External memory mod e
1. EXT resistor bit 3=0 : input/output
2. EXT resistor bit 3=1 : bank address output for
external memory
•4-bit input port
I
•Another functions
P70
•Interrupt recei ved form, vector address
INT0
INT1
INT2
INT3
CL1 Latch clock
P41
CL2 Shift clock
P42
DO Output data
P43
M Alternate signal
P44
FRM Frame signal
RD
P46
P47
P71
P72
P73
leading trailing leading
Read signal
WR
Write signal
INT0 input/HOLD release/N-ch Tr.
output for watchdog timer
INT1 input/HOLD release
INT2 input/timer 0 event input
INT3 input with noise filter/timer 0
event input
&
trailing
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
high
level
enable
enable
disable
disable
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/ N-ch open drain
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/ N-ch open drain
•Pull-up resistor :
Provided/Not provided
low
vector
level
enable
enable
disable
disable
03H
0BH
13H
1BH
No.6723-10/28
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LC868016/12/08A
Name No. I/O Function description Option
C1 to C16 65-50 O LCD output terminals for common S1 to S48 2-49 O LCD output terminals for segment LCD output terminals :
segment/common
RES
133 I Reset -
ADLC 131 O Address control signal for external memory -
EROE
132 O Enable signal of external ROM output -
XT1 134 I Input for 32.768kHz crystal oscillation
In case of non use, connect to VDD
XT2 135 O Output for 32.768kHz crystal oscillation
In case of non use, should be left unconnected
CF1 137 I Input for ceramic resonator oscillation
In case of non use, connect to VDD
CF2 138 O Output for ceramic resonator oscillation
In case of non use, should be left unconnected
-
-
-
-
* Port options can be specified in a bit.
* A state of port at initial
Pin name Input/output mode A state of pull-up resistor specified at pull-up option
Port 0, 7 Input Fixed pull-up resistor exist
Ports 1, 2
Ports 3, 5
Port 4 Input Programmable pull-up resistor ON
Input Programmable pull-up resistor OFF
Name Output level
C1 to C16 VDD (Display OFF)
S1 to S48 VDD (Display OFF)
No.6723-11/28
Page 12
LC868016/12/08A
V
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Parameter Symbol Pins Conditions
Supply voltage VDDMAX VDD -0.3 +7.0
Input voltage
Output voltage
Input/output
voltage
High
level
output
current
Low
level
output
current
Operating
temperature
range
Storage
temperature
range
Peak
output
current
Total
output
current
Peak
output
current
Total
output
current
VI(1) •Ports 71,72,73
•
RES
VI(2) VLCD VDD-21 VDD+0.3
VO(1) •C1 to C16
•S1 to S48
VO(2) •VOUT2,VOUT3
•CUP1,CUP2
VO(3) ADLC,
VIO(1) •Ports 0,1,2,3,4,5
•Port 70
IOPH(1) •Ports 0,1,2,3,4,5
•ADLC,
IOAH(1) •Ports 0,2,3
Σ
•C1-C16,S1-S48
•ADLC,
IOAH(2) Ports 1, 4, 5 Total all pins -25
Σ
IOPL(1) •Ports 0,1,2,3,4,5
•ADLC,
IOPL(2) Port 70 At each pin 15
IOAL(1) Port 0 Total all pins 40
Σ
IOAL(2) •Port 2
Σ
•ADLC,
IOAL(3) Port 3 Total all pins 40
Σ
IOAL(4) Ports 1, 5 Total all pins 40
Σ
IOAL(5) Port 4 Total all pins 40
Σ
IOAL(6) Port 70 Total all pins 15
Σ
IOAL(7) C1-C16,S1-S48 Total all pins 30
Σ
Topr -30 +70
Tstg -55 +125
EROE
EROE
EROE
EROE
EROE
-0.3 VDD+0.3
VLCD-0.3 VDD+0.3
VDD-21 VDD+0.3
-0.3 VDD+0.3
-0.3 VDD+0.3
•
CMOS output
•
At each pin
Total all pins -25
At each pin 20
Total all pins 40
Ratings
[V]
DD
min. typ. max.
-4
unit
V
mA
C
°
Notes :
The specifications above are for a die mounted in a QIC160 type package.
However, we ship this product as a die only, not a package chip.
Therefore, the operational characteristics may vary depending on the user’s packaging techniques.
No.6723-12/28
Page 13
LC868016/12/08A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Operating
supply voltage
range
Hold voltage VHD VDD RAMs and the
voltage
Input high
voltage
Input low
voltage
cycle time
Oscillation
frequency
range
(Note 1)
VDD(1) 0.98µs ≤ tCYC ≤
VDD(2) 1.9µs ≤ tCYC ≤
VDD(3)
VLCD VLCD
VIH(1) Port 0 (Schmitt) Output disable 2.5-6.0 0.4VDD
VIH(2) •Ports 1,2,4,5
VIH(3) •Port 70 for
VIH(4) Port 70 for watchdog
VIH(5) Port 3 Output disable 2.5-6.0 0.75VDD VDD
VIL(1) Port 0 (Schmitt) Output disable 2.5-6.0 VSS 0.2VDD
VIL(2) •Ports 1,2,4,5
VIL(3) •Port 70
VIL(4) Port 70 for watchdog
VIL(5) Port 3 Output disable 2.5-6.0 VSS 0.25VDD
CYC
t
FmCF(1) CF1, CF2 •12MHz
FmCF(2) CF1, CF2 •6MHz
FmCF(3) CF1, CF2 •3MHz
FmRC
FsXtal XT1, XT2 •32.768kHz
VDD
400µs
400µs
3.9µs ≤ tCYC ≤
400µs
registers hold
voltage at HOLD
mode.
Output disable 2.5-6.0 0.75VDD VDD
•Ports 72,73
(Schmitt)
Output N-channel
Port input/interrupt
•Port 71
RES
•
(Schmitt)
timer
•Ports 72,73 (Schmitt)
Port input/interrupt
•Port 71
RES
•
timer
Tr. OFF
Output N-channel
Tr. OFF
Output disable 2.5-6.0 VSS 0.25VDD
Output N-channel
Tr. OFF
Output N-channel
Tr. OFF
(ceramic resonator
oscillation)
•Refer to figure 1
(ceramic resonator
oscillation)
•Refer to figure 1
(ceramic resonator
oscillation)
•Refer to figure 1
oscillation Mask
option is ‘High’
•Internal RC
oscillation Mask
option is ‘Low’
(crysta l os cillation)
•Refer to figure 2
VDD[V] min. typ. max.
4.5-6.0 -2VDD VDD-4.5 LCD display
2.5-4.5 -VDD VDD-4.5
2.5-6.0 0.75VDD VDD
2.5-6.0 0.9VDD VDD
2.5-6.0 VSS 0.25VDD
2.5-6.0 VSS 0.8VDD
4.5-6.0 0.98 400 Operation
2.5-6.0 3.9 400
4.5-6.0 11.76 12 12.24
4.5-6.0 5.88 6 6.12
2.5-6.0 2.94 3 3.06
2.5-4.5 1.0 1.4 2.0 •Internal RC
4.5-6.0 0.8 1.3 1.8
2.5-4.5 0.5 0.9 1.2
4.5-6.0 0.4 0.75 1.0
2.5-6.0 32.768 kHz
Ratings
4.5 6.0
4.5 6.0
2.5 6.0
2.0 6.0
VDD
+0.9
unit
V
-1.0
µ
MHz
s
Continue.
No.6723-13/28
Page 14
LC868016/12/08A
Parameter Symbol Pins Conditions
Oscillation
stabilizing
time period
(Note 1)
tmsCF(1) CF1, CF2 •12MHz
(ceramic resonator
oscillation)
•Refer to figure 3
tmsCF(2) CF1, CF2 •6MHz
(ceramic resonator
oscillation)
•Refer to figure 3
(ceramic resonator
oscillation)
•Refer to figure 3
tssXtal XT1, XT2 •32.768kHz
(crysta l os cillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
Ratings
VDD[V] min. typ. max.
4.5-6.0 0.02 0.3
4.5-6.0 0.02 0.3
4.5-6.0 0.1 1 tmsCF(3) CF1, CF2 •3MHz
2.5-6.0 0.1 3
4.5-6.0 1 1.5
2.5-6.0 1 3
unit
ms
s
No.6723-14/28
Page 15
LC868016/12/08A
3. Electrical Characteristics at Ta=- 30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Input high
current
Input low
current
Output high
voltage
Output low
voltage
Tr. resistor
Hysteresis
voltage
Pin
capacitance
IIH(1) •Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr.
IIH(2) Port 7 without
pull-up MOS Tr.
RES
IIH(3)
IIL(1) •Ports 1,2,3,4,5
IIL(2) Port 7 without
IIL(3)
VOH(1) IOH=-10mA 4.5-6.0 VDD-1.5
VOH(2)
VOH(3) IOH=-1.0mA 4.5-6.0 VDD-1
VOH(4)
VOL(1) IOL=10mA 4.5-6.0 1.5
VOL(2) IOL=1.6mA 4.5-6.0 0.4
VOL(3)
VOL(4) IOL=1mA 4.5-6.0 0.4
VOL(5)
Rpu •Ports 0,1,2,3,4,5
VHIS •Ports 0,1,2,3,4,5
CP All pins •f=1MHz
VIN=VDD 2.5-6.0 1
•Port 0 without
pull-up MOS Tr.
pull-up MOS Tr.
RES
VIN=VSS 2.5-6.0 -1
Port 0 of
CMOS output
•Ports 1,2,3,4,5 of
CMOS output
•ADLC,
•Ports 0,1,2,3,4,5
•ADLC,
Port 70
•Port 7
•Port 7
RES
•
EROE
EROE
•Output disable
•Pull-up MOS Tr. OFF
•VIN=VDD
(including the off leak current of the
output Tr.)
•Output Nch Tr. OFF
•VIN=VDD
(including the off leak current of the
output Tr.)
•Output disable
•Pull-up MOS Tr. OFF
•VIN=VSS
(including the off leak current of the
output Tr.)
•Output Nch Tr. OFF
•VIN=VSS
(including the off leak current of the
output Tr.)
IOH=-1mA 2.5-6.0 VDD-0.4
IOH=-0.1mA 2.5-6.0 VDD-0.5
•IOL=1.0mA
•The current of any
measurement pin is
not over 1mA.
IOL=0.5mA 2.5-6.0 0.4
VOH=0.9VDD
Output disable 2.5-6.0 0.1VDD V
•Unmeasurement
terminals for the
input are set to
VSS level.
•Ta=25°C
Ratings
VDD[V] min. typ. max.
2.5-6.0 1
2.5-6.0 1
2.5-6.0 -1
2.5-6.0 -1
2.5-6.0 0.4
4.5-6.0 15 40 70 Pull-up MOS
2.5-4.5 25 60 120
2.5-6.0 10 pF
unit
A
µ
V
kΩ
No.6723-15/28
Page 16
LC868016/12/08A
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Cycle t
Low Level
CKCY
CKL
t
SCK0,
(1) 2
SCK1
(1) 1
Refer to figure 5. 2.5-6.0
pulse width
High Level
Input clock
CKH
t
(1)
pulse width
Cycle t
Serial clock
Low Level
pulse width
High Level
Output clock
pulse width
Data set up ti me
Data hold time
Serial input
Output delay time
(Serial clock is
external clock)
CKCY
CKL
t
CKH
t
ICK
t
CKI
t
CKO(1)
t
SCK0,
(2) 2
SCK1
(2) 1/2
•Use pull-up
resistor (1kΩ)
when Nch open-
(2)
drain output.
•Refer to figure 5.
•SI0,SI1
•SB0,SB1
•Data set-up to
SCK0,1
•Data hold from
SCK0,1
•Refer to figure 5.
•SO0,SO1
•SB0,SB1
•Data set-up to
SCK0,1
•Use pull-up
resistor (1kΩ)
when Nch open drain output.
•Refer to figure 5.
Output delay time
(Serial clock is
Serial output
internal clock)
CKO(2)
t
•SO0,SO1
•SB0,SB1
•Data hold from
SCK0,1
•Use pull-up
resistor (1kΩ)
when Nch open drain output.
•Refer to figure 5.
VDD[V] min. typ. max.
2.5-6.0
4.5-6.0 0.1
2.5-6.0 0.4
4.5-6.0 0.1
2.5-6.0 0.4
4.5-6.0 7/12
2.5-6.0 7/12
4.5-6.0 1/3
2.5-6.0 1/3
Ratings
unit
CYC
t
1
CKCY
t
1/2
CKCY
t
CYC
t
+0.2
CYC
t
+1
CYC
t
+0.2
CYC
t
+1
s
µ
No.6723-16/28
Page 17
LC868016/12/08A
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
pulse width
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5) •
•INT0, INT1
•INT2/T0IN
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/1.)
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/16.)
•Refer to figure 6
•INT3/T0IN
(The noise rejection
clock is selected to
1/64.)
•Refer to figure 6
RES
•Refer to figure 6
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
•Interrupt accept able
•Timer0-countable
Reset acceptable 2.5-6.0 200
Ratings
VDD[V] min. typ. max.
2.5-6.0 1
2.5-6.0 2
2.5-6.0 32
2.5-6.0 128
unit
CYC
t
High/low level
s
µ
No.6723-17/28
Page 18
LC868016/12/08A
6. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins Conditions
Current
dissipation
during basic
operation
(Note 2)
IDDOP(1) •FmCF=12MHz
IDDOP(2) •FmCF=6MHz
IDDOP(3) 0 3 9
IDDOP(4) 1
IDDOP(5)
VDD
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
12MHz
•Internal RC
oscillation stops
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
6MHz
•Internal RC
oscillation stops
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
3MHz
•Internal RC
oscillation stops
OCR7 VDD[V] min. typ. max.
0 4.5-6.0 10 25
1 4.5-6.0 10 25
0 2.5-4.5 1.5 5
Ratings
4.5-6.0
6 15
unit
mA
IDDOP(6) 0 1.2 5.8
IDDOP(7) 1
IDDOP(8) 0 0.7 4.8
IDDOP(9)
IDDOP(10) 0 0.7 3.4
IDDOP(11) 1
IDDOP(12) 0 0.4 2.8
IDDOP(13)
IDDOP(14) 0 38 150
IDDOP(15) 1
IDDOP(16) 0 15 70
IDDOP(17)
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
*OSCR : Bit 7 of the oscillation control register.
Mask option
is “High”
Mask option
is “Low”
Continue.
4.5-6.0
2.0 7.8
2.5-4.5
1
4.5-6.0
2.5-4.5
1
4.5-6.0
2.5-4.5
1
1.4 6.2
1.2 4.5
0.8 3.6
µ
60 300
25 120
A
No.6723-18/28
Page 19
LC868016/12/08A
Parameter Symbol Pins Conditions
Current
dissipation
in HALT
mode
(Note 2)
dissipation
in HOLD
mode
(Note 2)
IDDHALT(1) •HALT mode
IDDHALT(2) •HALT mode
IDDHALT(3) 0 2.3 7
IDDHALT(4) 1
IDDHALT(5)
IDDHALT(6) 0 650 2700
IDDHALT(7) 1
IDDHALT(8) 0 340 2200
IDDHALT(9)
IDDHALT(10) 0 400 1600
IDDHALT(11) 1
IDDHALT(12) 0 200 1300
IDDHALT(13)
IDDHALT(14) 0 25 100
IDDHALT(15) 1
IDDHALT(16) 0 8 55
IDDHALT(17)
IDDHOLD(1) 4.5-6.0 0.05 30 Current
IDDHOLD(2)
VDD
•FmCF=12MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
12MHz
•Internal RC
oscillation stops
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
6MHz
•Internal RC
oscillation stops
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
3MHz
•Internal RC
oscillation stops
•HALT mode
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•HALT mode
•FmCF=0Hz
(when oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
VDD HOLD mode
Mask option
is “High”
Mask option
is “Low”
Ratings
OCR7 VDD[V] min. typ. max.
0 4.5-6.0 5.0 14
1 4.5-6.0 5.0 14
4.5-6.0
4.5 15
0 2.5-4.5 0.8 4
4.5-6.0
1000 4200
2.5-4.5
1
4.5-6.0
2.5-4.5
1
4.5-6.0
2.5-4.5
1
2.5-4.5 0.02 20
600 2500
600 2400
350 1500
36 140
12 85
(Note 2) The currents of the output transistors, pull-up transistors and the LCD bleeder resistors are ignored.
Refer to figure 7.
unit
mA
A
µ
No.6723-19/28
Page 20
LC868016/12/08A
7. LCD Voltage and LCD Driver Characteristics at Ta=-30°C to +70°C, VSS=0V
Parameter Symbol Pins, Conditions
voltage (i : 1 to 16 )
voltage (X : 1 to 4)
(i : 1 to 16)
voltage (X : 1 to 5)
(i : 1 to 16)
voltage (i : 1 to 48 )
voltage (X : 1 to 4)
(i : 1 to 48)
voltage (i : 1 to 5)
(i : 1 to 48)
LCD display
current
Step up voltage
Contrast current
(VLCD terminal)
|VD1|
|VD2|
|VD3| •Only a Ci terminal for +15µA
|VD4|
|VD5|
|VD6| •Only a Ci terminal for +15µA
ILCD2
VOUT2 •V1-V5 resistor=20kΩ
VOUT3 •V1-V5 resistor=20kΩ
ILC1 VCCR=1 5 5 10 20
ILC2 VCCR=2 5 2.5 5 10
ILC3 VCCR=4 5 1.25 2.5 5
ILC4 VCCR=8 5 0.6 1.25 2.5
ILC5
•Only a Ci terminal for –15µA
•LCD display ON
•1/5 bias
•V5=0V
•LCD display ON
•1/5 bias
•V5=0V
•Only a Si terminal for -1 5µA
•LCD display ON
•1/5 bias
•V5=0V
•LCD display ON
•1/5 bias
•V5=0V
•LCD c lock freque nc y=0Hz
•LCD display ON
•1/5 bias
•V5=0V
•Refer to figure 9
•LCD display ON
•1/5 bias
•VLCD=0V
•V1-V5 are opened
•Refer to figure 8
•LCD display ON
•LVCR0=1 (doubler)
•VOUT2
•C5=C6=0.1µF
•Internal RC oscillation
start
•Refer to figure 10
•LCD display ON
•LVCR0=0 (tripler )
•VOUT3
•C5=C6=0.1µF
•Internal RC oscillation
start
•Refer to figure 11
•LCD display ON
•V5=0V
•VLCD=-3V
•Refer to figure 12
mode
4kΩ
mode
IL=100µA
IL=500µA
IL=100µA 5 -10 -9.4 -9.0
IL=500µA 5 -10 -8.5 -7.5
VCCR=10H 5 0.3 0.6 1.25
Ratings
VDD[V] min. typ. max.
2.9 120 VDD-Ci drop
5.0 200
2.9 120 VX-Ci drop
5.0 200
2.9 -120 VX-Ci drop
5.0 -200
2.9 120 VDD-Si drop
5.0 200
2.9 120 VX-Si drop
5.0 200
2.9 -120 VX-Si drop
5.0 -200
2.9 V1 output voltage VV1
0.75VDD 0.80VDD 0.85VDD
5.0
2.9 V2 output voltage VV2
0.55VDD 0.60VDD 0.65VDD
5.0
2.9 V3 output voltage VV3
0.35VDD 0.40VDD 0.45VDD
5.0
2.9 V4 output voltage VV4
0.15VDD 0.20VDD 0.25VDD
5.0
5 25 50 100 ILCD1 20kΩ
2.9 15 29 60
5 125 250 500
2.9 75 150 300
2.7 -2.7 -1.9 -1.7
3 -3 -2.8 -2.6
5 -5 -4.8 -4.5
2.7 -2.7 -1.8 -1.5
3 -3 -2.6 -2.2
5 -5 -4.6 4.2
VCCR : The LCD contrast control register
LVCR0 : Bit 0 of the LCD bias control register
unit
mV
V
A
µ
V
mA
A
µ
No.6723-20/28
Page 21
LC868016/12/08A
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type Maker Oscillator C1 C2
12MHz ceramic resonato r
oscillation
Kyocera KBR-12.0M 33pF 33pF
6MHz ceramic resonator
oscillation
Kyocera
3MHz ceramic resonator
oscillation
Kyocera KBR-3.0MS 47pF 47pF
CSA12.0MT 33pF 33pF Murata
CST12.00MTW on chip
CSA6.00MG 33pF 33pF Murata
CST6.00MGW on chip
KBR-6.0MSA 33pF 33pF
KBR-6.0MKS on chip
CSA3.0MG 33pF 33pF Murata
CST3.0MGW on chip
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type Maker Oscillator C3 C4
CITIZEN CFS-308 18pF 18pF 32.768kHz crystal oscillation
SII DT-VT-200 18pF 18pF
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation
pins as possible with the shortest possible pattern length.
•For other oscillators, please request an evaluation of microcomputer and oscillator matching to the oscillator
manufacturer.
CF1 CF2 XT1 XT2
CF
C2 C1
X’tal
C4 C3
Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit
No.6723-21/28
Page 22
LC868016/12/08A
Power supply
RES
Reset time
VDD
VDD limit
0V
Internal RC oscillation
CF1, CF2
XT1, XT2
tmsCF
tssXtal
Operation mode
Unstable
Execution of instructions Reset
Reset time and oscillation stable time
HOLD release signal
Valid
Internal RC oscillation
CF1, CF2
tmsCF
tssXtal
XT1, XT2
Operation mode
HOLD
Execution of instructions
HOLD release signal and oscillation stable time
Figure 3 Oscillation stable time
No.6723-22/28
Page 23
LC868016/12/08A
VDD
RES
R
RES
RES
C
(Note) Fix the value of C
sure to reset until 200µs, after Power
supply has be en over inferior limit o f
supply voltage.
RES
, R
RES
that is
Figure 4 Reset circuit
0.5VDD
<AC Timing Point>
tCKCY
tCKH tCKL
VDD
SCK0
SCK1
SI0
SI1
tCKO
SO0, SO1
SB0, SB1
tCKI tICK
<Timing>
1kΩ
50pF
<Test Load>
Figure 5 Serial input / output test condition
tPIH tPIL
Figure 6 Pulse input timing condition
No.6723-23/28
Page 24
LC868016/12/08A
VDD
A
VDD
Open
VDD
CUP1
CUP2
VOUT2
VOUT3
CF1 XT2CF2 XT1
VSS
VSS
V1
V5
VLCD
Open
VDD
CUP1
CUP2
VOUT2
VOUT3
CF1 XT2CF2 XT1
VSS
VSS
V1
V5
VLCD
Figure 7 Current dissipation measurement Figure 8 LCD display current measurement
Open
VDD
VDD
CUP1
CUP2
VOUT2
VOUT3
VLCD
CF1 XT2CF2 XT1
VSS
V1
V4
V5
IL Open
VDD
VDD
CUP1
CUP2
VOUT2
VOUT3
CF1 XT2CF2 XT1
VSS
V1
V5
VLCD
Open
A
VSS
V
V
VSS
*VOUT3 FOpen
Figure 9 Output voltage of V1-V4 measurement Figure 10 Step up output voltage measurement (1)
VDD
VDD
C5
CUP1
CUP2
C6
C7
IL
VOUT2
VOUT3
CF1 XT2CF2 XT1
V A
VSS
VSS
V1
V5
VLCD
Open
VDD
VDD
CUP1
CUP2
VOUT2
VOUT3
CF1 XT2CF2 XT1
VSS
VSS
V1
V4
V5
VLCD
Figure 11 Step up output voltage measurement (2) Figure 8 Contrast current measurement
-3V
Open
No.6723-24/28
Page 25
LC868016/12/08A
8. AC Characteristics at Ta=-30°C to +70°C, VSS=0V
Load capacity : 100pF (Port 0, ADLC,
Load capacity : 80pF (Output terminals except above)
*tCLCL=1/12 tCYC
External program memory timing
Parameter Symbol Pads and Conditions
EROE
EROE
EROE
! address in tEHAV
EROE
Refer to figure 13.
1 tCYC
SCLK
tLHLL
ADLC
EROE
Port 0
tAVLL
A7-A0
tLLEL
tLLAX
tELEH
tELIV
tEHIX
EROE )
Ratings
VDD[V] min. max.
4.5 - 6.0 2tCLCL-40 ADLC pulse widt h tLHLL
2.5 - 6.0 2tCLCL-160
4.5 - 6.0 tCLCL-40 Address settling time tAVLL For ADLC
2.5 - 6.0 tCLCL-160
4.5 - 6.0 tCLCL-35 Address hold time tLLAX For ADLC
2.5 - 6.0 tCLCL-140
4.5 - 6.0 tCLCL-25 ADLC ! control signal tLLEL For
2.5 - 6.0 tCLCL-100
4.5 - 6.0 3tCLCL-35 EROE pulse width tELEH
2.5 - 6.0 3tCLCL-140
4.5 - 6.0 3tCLCL-125 Data delay time tELIV From
2.5 - 6.0 3tCLCL-400
4.5 - 6.0 0 Data hold time tEHIX For
2.5 - 6.0 0
4.5 - 6.0 tCLCL-8
2.5 - 6.0 tCLCL-32
tEHAV
IR A7-A0
unit
ns
tCLCL
Port 2
Port 3
EROE
Port 0
Port 2
Port 3
Port 5
A15-A8
A7-A0
A7-A0 DATA
A15-A8
A7-A0
Bank
A15-A8
A7-A0
Figure 13 Timing of the external Program Memory/Data Memory
No.6723-25/28
Page 26
Ext ernal data memory timing
Parameter Symbol Pads and Conditions
pulse width tRLRH
RD
WR
pulse width tWLWH
Data address hold time tLLAX
For ADLC (at STX)
tAVLL For ADLC
time
ADLC ! control signal
tLLWL For
WR
WR
=1 tQVWH
WR
Control signal ! ADLC
tWHLH For
RD
WR
Refer to figure 14.
tCLCL
RD
RD
WR
LC868016/12/08A
Ratings
VDD[V] min. max.
4.5 - 6.0 6tCLCL-80
2.5 - 6.0 6tCLCL-320
4.5 - 6.0 6tCLCL-80
2.5 - 6.0 6tCLCL-320
4.5 - 6.0 2tCLCL-35 For ADLC (at LDX)
2.5 - 6.0 2tCLCL-140
4.5 - 6.0 2tCLCL-35
2.5 - 6.0 2tCLCL-140
4.5 - 6.0 5tCLCL-125 Data delay time tRLD V From RD
2.5 - 6.0 5tCLCL-400
4.5 - 6.0 0 Data hold time tRHDX From
2.5 - 6.0 0
4.5 - 6.0 2tCLCL-70 2tCLCL+70 Data floating time tRHDZ From
2.5 - 6.0 2tCLCL-280 2tCLCL+280
4.5 - 6.0 tCLCL-40 Data address setting
2.5 - 6.0 tCLCL-160
4.5 - 6.0 3tCLCL-50 3tCLCL+50 tLLRL For RD
2.5 - 6.0 3tCLCL-200 3tCLCL+200
4.5 - 6.0 3tCLCL-50 3tCLCL+50
2.5 - 6.0 3tCLCL-200 3tCLCL+200
4.5 - 6.0 tCLCL-60 Data settling time tQVWL For
2.5 - 6.0 tCLCL-240
4.5 - 6.0 7tCLCL-140 Data in
2.5 - 6.0 7tCLCL-560
4.5 - 6.0 tCLCL-50 Data hold time tWHQX From
2.5 - 6.0 tCLCL-200
4.5 - 6.0 tCLCL-50 tCLCL+50 tRHLH For
2.5 - 6.0 tCLCL-200 tCLCL+200
4.5 - 6.0 tCLCL-50 tCLCL+50
2.5 - 6.0 tCLCL-200 tCLCL+200
1 tCYC
unit
ns
SCLK
ADLC
EROE
RD
tAVLL tLLAX
Port 0
WR
Port 0
Port 2
Port 5
Port 3
tLLRL
tRLDV
(at reading)
A7-A0
tLLWL
tLLAX
(at writing)
A7-A0 DATA
tQVWL tWHQX
tQVWH
A15-A8
Bank
A7-A0
tRLRH tRHLH
tRHDZ
tRHDX
DATA Z
tWLWH tWHLH
Figure 14 Timing of the external RAM
No.6723-26/28
Page 27
LC868016/12/08A
3
Evaluation Samp le (ES)
•
The factory shipment of this microcomputer is chip.
But there are two types of shipment of evaluation sample.
One type is chip and the other is package (QIC160).
If you selected package type, please refer to the following pin assignment and layout, and make the user target board.
• Pin Assignment of evaluation sample (Package type)
VDD
P30
P31
P32
P33
P34
P35
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
P20
P21
P22
P23
P24
P25
P26
P27
ADLC
EROM
RES
XT1
XT2
VSS
CF1
CF2
125
130
140
150
155
P50
1
P51
P52
P53
115
P54
P55
P56
P57
P17
P16
P15
P14
P13
P12
P11
110
100
LC868016-QIC160
10
20
P10
P73
P72
P71
P70
P47
P46
P44
P43
P42
P41
P40
VSS
CUP1
CUP2
VOUT2VOUT
90
30
85
35
VLCD
V5
V4
V3
75
V2
V1
C1
C2
C3
70
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
60
C14
C15
C16
S48
S47
S46
S45
S44
S43
S42
50
S41
S40
S39
S38
S37
45
S36
S35
S2S3S1
VDD
S4S5S6S7S8
S9
S11
S10
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
No.6723-27/28
Page 28
LC868016/12/08A
• Layout of evaluation sample (P ackage type) : QIC160
No.6723-28/28
PS
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