Datasheet LC75893M Datasheet (SANYO)

Page 1

Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

Overview

The LC75893M is a 1/3 duty LCD display driver that can directly drive up to 48 segments and can control up to four general-purpose output ports. This product also incorporates a key scan circuit that accepts input from up to 20 keys to reduce printed circuit board wiring.

Features

• Key input function for up to 20 keys (A key scan is performed only when a key is pressed.)

• 1/3 duty - 1/2 bias and 1/3 duty - 1/3 bias drive schemes can be controlled from serial data (up to 48 segments).

• Sleep mode and all segments off functions that are controlled from serial data

• Segment output port/general-purpose output port function switching that is controlled from serial data

• Serial data I/O supports CCB format communication with the system controller.

• Direct display of display data without the use of a decoder provides high generality.

• Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.

• RC oscillator circuit

Package Dimensions

unit: mm

3204-MFP36S

0.15

15.3

36 19

0.850.35 0.8

2.5max

2.15

0.1

7.9

9.2

10.5

0.65

CMOS IC

N2999RM (OT) No. 5971-1/23

SANYO: MFP36S

[LC75893M]

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

1/3 Duty LCD Display Driver with Key Input Function

LC75893M

Ordering number : ENN5971A

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO.

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Parameter Symbol Conditions

Ratings

Unit

min typ max

Supply voltage V

DDVDD

4.5 6.0 V

Input voltage

1VDD1 2/3 V

2VDD2 1/3 V

Input high level voltage

1 CE, CL, DI 0.8 V

6.0 V

2 KI1 to KI5 0.6 V

Input low level voltage V

CE, CL, DI, KI1 to KI5 0 0.2 V

Recommended external resistance R

OSC

OSC 68 kΩ

Recommended external capacitance C

OSC

OSC 820 pF

Guaranteed oscillation range

OSC

OSC 19 38 76 kHz

Data setup time t

CL, DI: Figure 2 160 ns

Data hold time t

CL, DI: Figure 2 160 ns

CE wait time t

CE, CL: Figure 2 160 ns

CE setup time t

CE, CL: Figure 2 160 ns

CE hold time t

CE, CL: Figure 2 160 ns

High level clock pulse width t

H CL: Figure 2 160 ns

Low level clock pulse width t

L CL:Figure 2 160 ns

Rise time t

CE, CL, DI: Figure 2 160 ns

Fall time t

CE, CL, DI: Figure 2 160 ns

DO output delay time t

DO: RPU= 4.7 kΩ, CL= 10 pF*1: Figure 2 1.5 µs

DO rise time t

DO: RPU= 4.7 kΩ, CL= 10 pF*1: Figure 2 1.5 µs

Allowable Operating Ranges at Ta = –40 to +85°C, VSS= 0 V

Note *1: Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPUand the load capacitance CL.

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage V

max V

–0.3 to +7.0 V

Input voltage

1 CE, CL, DI –0.3 to +7.0 V

2 OSC, KI1 to KI5, TEST, VDD1, VDD2 –0.3 to VDD+0.3 V

OUT

1 DO –0.3 to +7.0 V

Output voltage

OUT

2 OSC, S1 to S16, COM1 to COM3, KS1 to KS4, P1 to P4 –0.3 to VDD+0.3 V

OUT

1 S1 to S16 300 µA

Output current

OUT

2 COM1 to COM3 3 mA

OUT

3 KS1 to KS4 1 mA

OUT

4 P1 to P4 5 mA Allowable power dissipation Pd max Ta = 85°C 100 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS= 0V

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Note *2: Excluding the bias voltage generation divider resistor built into VDD1 and VDD2. (See Figure 1.)

Parameter Symbol Conditions

Ratings

Unit

min typ max

Hysteresis V

CE, CL, DI, KI1 to KI5 0.1 V

Power-down detection voltage V

DET

2.7 3.0 3.3 V

Input high level current I

CE, CL, DI: VI= 6.0 V 5.0 µA

Input low level current I

CE, CL, DI: VI= 0 V –5.0 µA

Input floating voltage V

KI1 to KI5 0.05 V

Pull-down resistance R

KI1 to KI5: VDD= 5.0 V 50 100 250 kΩ

Output off leakage current I

OFFH

DO: VO= 6.0 V 6.0 µA

1 KS1 to KS4: IO= –500 µA VDD– 1.2 VDD– 0.5 VDD– 0.2 V

Output high level voltage

2 P1 to P4: IO= –1 mA VDD– 1.0 V

3 S1 to S16: IO= –20 µA VDD– 1.0 V

4 COM1 to COM3: IO= –100 µA VDD– 1.0 V

1 KS1 to KS4: IO= 25 µA 0.2 0.5 1.5 V

2 P1 to P4: IO= 1 mA 1.0 V

Output low level voltage V

3 S1 to S16: IO= 20 µA 1.0 V

4 COM1 to COM3: IO= 100 µA 1.0 V

5 DO: IO= 1 mA 0.1 0.5 V

MID

1 COM1 to COM3: 1/2 bias, IO= ±100 µA 1

/2 VDD– 1.0 1/2 VDD+ 1.0

MID

2 S1 to S16: 1/3 bias, IO= ±20 µA

2/3 VDD– 1.0 2/3 VDD+ 1.0

Output middle level voltage*

MID

3 S1 to S16: 1/3 bias, IO= ±20 µA

1/3 VDD– 1.0 1/3 VDD+ 1.0

MID

4 COM1 to COM3: 1/3 bias, IO= ±100 µA

2/3 VDD– 1.0 2/3 VDD+ 1.0

MID

5 COM1 to COM3: 1/3 bias, IO= ±100 µA

1/3 VDD– 1.0 1/3 VDD+ 1.0

Oscillator frequency f

OSC

OSC: R

OSC

= 68 kΩ, C

OSC

= 820 pF 30.4 38 45.6 kHz

1 Sleep mode 100 µA

Current drain I

2VDD= 6.0 V, output open, 1/2 bias, f

OSC

= 38 kHz 200 400 µA

3VDD= 6.0 V, output open, 1/3 bias, f

OSC

= 38 kHz 170 340 µA

Electrical Characteristics for the Allowable Operating Ranges

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• When CL is stopped at the low level

• When CL is stopped at the high level

Figure 1

Figure 2

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To the common segment driver

Excluding these resistors.

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Pin Assignment

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Block Diagram

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Pin Functions

Pin Pin No. Function Active I/O

Handling

when unused

S1/P1 to S4/P4

S5 to S14

COM1 COM2 COM3

KS1/S15 KS2/S16

KS3 KS4

KI1 to KI5

OSC

TEST

1 to 4

5 to 14

15 16 17

18 19 20 21

22 to 26

34 35 36 33 27

28 31

Segment outputs for displaying the display data transferred by serial data input.

The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial data control.

Common driver outputs The frame frequency f

is given by: fO= (f

OSC

/384) Hz.

Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S15 and KS2/S16 pins can be used as segment outputs when so specified by the control data.

Key scan inputs These pins have built-in pull-down resistors.

Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor at this pin.

Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor.

CE: Chip enable CL: Synchronization clock DI: Transfer data DO: Output data

This pin must be connected to ground.

Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to V

2 when a 1/2 bias drive scheme is used.

Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to V

1 when a 1/2 bias drive scheme is used.

Power supply connection. Provide a voltage of between 4.5 and 6.0 V. Power supply connection. Connect to ground.

—

— — —

—

— —

I/O

I I I

— —

Open

GND

Open

—

Open

— —

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Serial Data Input

1. When CL is stopped at the low level

Note: B0 to B3 and A0 to A3 ··········· CCB address

DD ········································· Direction data

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2. When CL is stopped at the high level

Note: B0 to B3 and A0 to A3 ···········CCB address

DD ·········································Direction data

• CCB address ····42H

• D1 to D48··········Display data

• S0, S1···············Sleep control data

• K0, K1···············Key scan output/segment output selection data

• P0 to P2············Segment output port/general-purpose output port selection data

• SC·····················Segment on/off control data

• DR·····················1/2 bias or 1/3 bias drive selection data

Display data

Control data

Fixed data

Display data

Control data

Fixed data

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Control Data Functions

1. S0, S1: Sleep control data These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS4 key scan outputs during key scan standby.

Note: This assumes that the KS1/S15 and KS2/S16 output pins are selected for key scan output.

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Control data

Mode OSC oscillator

Segment outputs Output pin states during key scan standby

S0 S1 Common outputs KS1 KS2 KS3 KS4

0 0 Normal Operating Operating H H H H 0 1 Sleep Stopped L L L L H 1 0 Sleep Stopped L L L H H 1 1 Sleep Stopped L H H H H

2. K0, K1: Key scan output/segment output selection data These control data bits switch the functions of the KS1/S15 and KS2/S16 output pins between key scan output and segment output.

X: don’t care

Note: KSn (n = 1, 2): Key scan output

Sn (n = 15, 16): Segment output

Note: Sn (n = 1 to 4): Segment output port

Pn (n = 1 to 4): General-purpose output port

However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins.

Control data Output pin state Maximum number

K0 K1 KS1/S15 KS2/S16 of input keys

0 0 KS1 KS2 20 0 1 S15 KS2 15 1 X S15 S16 10

3. P0 to P2: Segment output port/general-purpose output port selection data These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port.

The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports.

For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (VDD) when the display data D10 is 1, and will output a low level (VSS) when D10 is 0.

Control data Output pin state

P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4

0 0 0 S1S2S3S4 0 0 1 P1S2S3S4 0 1 0 P1P2S3S4 0 1 1 P1P2P3S4 1 0 0 P1P2P3P4

Output pin Corresponding display data

S1/P1 D1 S2/P2 D4 S3/P3 D7 S4/P4 D10

4. SC: Segment on/off control data This control data bit controls the on/off state of the segments.

SC Display state

0On 1 Off

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Display Data and Output Pin Correspondence

Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S15 and KS2/S16 are selected for use as segment outputs.

Output pin COM1 COM2 COM3

S1/P1 D1 D2 D3 S2/P2 D4 D5 D6 S3/P3 D7 D8 D9 S4/P4 D10 D11 D12

S5 D13 D14 D15 S6 D16 D17 D18 S7 D19 D20 D21 S8 D22 D23 D24

S9 D25 D26 D27 S10 D28 D29 D30 S11 D31 D32 D33 S12 D34 D35 D36 S13 D37 D38 D39 S14 D40 D41 D42

KS1/S15 D43 D44 D45 KS2/S16 D46 D47 D48

For example, the table below lists the segment output states for the S11 output pin.

Display data

Output pin state (S11)

D31 D32 D33

0 0 0 The LCD segments for COM1, COM2, and COM3 are off 0 0 1 The LCD segment for COM3 is on 0 1 0 The LCD segment for COM2 is on 0 1 1 The LCD segments for COM2 and COM3 are on 1 0 0 The LCD segment for COM1 is on 1 0 1 The LCD segments for COM1 and COM3 are on 1 1 0 The LCD segments for COM1 and COM2 are on 1 1 1 The LCD segments for COM1, COM2, and COM3 are on

5. DR: 1/2 bias or 1/3 bias drive selection data This control data bit switches between LCD 1/2 bias or 1/3 bias drive.

DR Drive scheme

0 1/3 bias drive 1 1/2 bias drive

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Serial Data Output

1. When CL is stopped at the low level

Note: B0 to B3 and A0 to A3 ············ CCB address

2. When CL is stopped at the high level

• CCB address·········· 43H

• KD1 to KD20·········· Key data

• SA ·························· Sleep acknowledge data Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD20) and sleep

acknowledge data (SA) will be invalid.

Output Data

1.KD1 to KD20 : Key data

When a key matrix of up to 20 keys is formed from the KS1 to KS4 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits.

When the KS1/S15 and KS2/S16 output pins are selected to be segment outputs by control data bits K0 and K1 and a key matrix of up to 10 keys is formed using the KS3 and KS4 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0.

2.SA: Sleep acknowledge data

This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep mode and 0 in normal mode.

Sleep Mode Functions

Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data bits, even in sleep mode. (See the control data description for details.)

KI1 KI2 KI3 KI4 KI5 KS1/S15 KD1 KD2 KD3 KD4 KD5 KS2/S16 KD6 KD7 KD8 KD9 KD10

KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20

Note: B0 to B3 and A0 to A3 ··········· CCB address

Output data

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Key Scan Operation Functions

1. Key scan timing The key scan period is 192 T (s). To reliably determine the on/off state of the keys, the LC75893M scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 420 T (s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys again. Thus the LC75893M cannot detect a key press shorter than 420 T (s).

Note: *3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output

from pins that are set low.

2. In normal mode

• The pins KS1 to KS4 are set high.

• When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key

presses are recognized by determining whether multiple key data bits are set.

• If a key is pressed for longer than 420 T (s) (where T = ) the LC75893M output a key data read

request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high.

• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75893M

performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ).

OSC

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3. In sleep mode

• The pins KS1 to KS4 are set to high or low by the S0 and S1 bits in the control data. (See the control data

description for details.)

• If a key on one of the lines corresponding to a KS1 to KS4 pin which is set high is pressed, the oscillator on the

OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set.

• If a key is pressed for longer than 420 T (s) (where T = ) the LC75893M outputs a key data read

request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high.

• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75893M

performs another key scan. However, this does not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ).

• Sleep mode key scan example

OSC

Example: When S0 = 0, S1 = 1 (Sleep with only KS4 high)

Note: *4. These diodes are required to reliable recognize multiple key presses on the KS4 line when sleep mode state with only KS4 high, as in the

above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS4 key scan output signal when keys on the KS1 to KS3 lines are pressed at the same time.

Multiple Key Presses

Although the LC75893M is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS4 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data.

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When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned.

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1/3 Duty, 1/2 Bias Drive Technique

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1/3 Duty, 1/2 Bias Waveforms

COM1

COM2

COM3

LCD drive output when all LCD

segments corresponding to COM1,

COM2, and COM3 are turned off.

LCD drive output when only LCD segments corresponding to COM1 are on.

LCD drive output when only LCD segments corresponding to COM2 are on.

LCD drive output when LCD segments corresponding to COM1 and COM2 are on.

LCD drive output when only LCD segments corresponding to COM3 are on.

LCD drive output when LCD segments corresponding to COM1 and COM3 are on.

LCD drive output when LCD segments corresponding to COM2 and COM3 are on.

LCD drive output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

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1/3 Duty, 1/3 Bias Drive Technique

1/3 Duty, 1/3 Bias Waveforms

COM1

COM2

COM3

LCD drive output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off.

LCD drive output when only LCD segments corresponding to COM1 are on.

LCD drive output when only LCD segments corresponding to COM2 are on.

LCD drive output when LCD segments corresponding to COM1 and COM2 are on.

LCD drive output when only LCD segments corresponding to COM3 are on.

LCD drive output when LCD segments corresponding to COM1 and COM3 are on.

LCD drive output when LCD segments corresponding to COM2 and COM3 are on.

LCD drive output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

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Voltage Detection Type Reset Circuit (VDET)

This circuit generates an output signal and resets the system when power is first applied and when the voltage drops, i.e., when the power supply voltage is less than or equal to the power down detection voltage VDET, which is 3.0 V, typical. To assure that this function operates reliably, a capacitor must be added to the power supply line so that the power supply voltage VDDrise time when power is first applied and the power supply voltage VDDfall time when the voltage drops are both at least 1 ms. (See Figure 3.)

System Reset

The LC75893M supports the reset method described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible.

1. Reset method If at least 1 ms is assured as the supply voltage VDDrise time when power is applied, a system reset will be applied by the VDET output signal when the supply voltage is brought up. If at least 1 ms is assured as the supply voltage V

fall time when power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (the display data D1 to D48 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been transferred. (See Figure 3.)

2. LC75893M internal block states during the reset period

• CLOCK GENERATOR

Reset is applied and the base clock is stopped. However the OSC pin state (normal or sleep mode) is determined after the S0 and S1 control data bits are transferred.

• COMMON DRIVER, SEGMENT DRIVER & LATCH

Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.

• KEY SCAN

Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.

• KEY BUFFER

Reset is applied and all the key data is set to low.

• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER

Since serial data transfer is possible, these circuits are not reset.

Figure 3

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3. Output pin states during the reset period

X: Don’t care Note: *5. These output pins are forcibly set to the segment output function and held low.

*6. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred. *7. Since this output pin is an-open drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period

even if a key data read operation is performed.

Output pin State during reset

S1/P1 to S4/P4 L *

S5 to S14 L

COM1 to COM3 L

KS1/S15, KS2/S16 L *

KS3 X *

KS4 H

DO H *

Blocks that are reset

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Sample Application Circuit 1

1/2 bias (for use with normal panels)

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Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDDrise time when power is applied and the power supply voltage VDDfall

time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.

*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the

external wiring so that signal waveforms are not degraded.

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Sample Application Circuit 2

1/2 bias (for use with large panels)

Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDDrise time when power is applied and the power supply voltage VDDfall

time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.

*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the

external wiring so that signal waveforms are not degraded.

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Sample Application Circuit 3

1/3 bias (for use with normal panels)

Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDDrise time when power is applied and the power supply voltage VDDfall

time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.

*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the

external wiring so that signal waveforms are not degraded.

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Sample Application Circuit 4

1/3 bias (for use with large panels)

Note: *8.Add a capacitor to the power supply line so that the power supply voltage VDDrise time when power is applied and the power supply voltage VDDfall

time when power drops are both at least 1 ms, as the LC75893M is reset by the VDET.

*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the

external wiring so that signal waveforms are not degraded.

Notes on transferring display data from the controller

The display data (D1 to D48) is transferred to the LC75893M in two operations. All of the display data should be transferred within 30 ms to maintain the quality of the displayed image.

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Notes on the controller key data read techniques

1. Timer based key data acquisition

• Flowchart

• Timing chart

• Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t7 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t7 in this technique must satisfy the following condition.

t7 > (t5 + t6 + t4)

If a key data read operation is executed when DO is high, the read key data (KD1 to KD20) and sleep acknowledge data (SA) will be invalid.

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t3·······Key scan execution time when the key data agreed for two key scans (420T[s]). t4·······Key scan execution time when the key data did not agree for two key scans and the key scan was executed again (840T[s]). t5·······Key address (43H) transfer time t6·······Key data read time

T = ——

fosc

CE = [L]

DO = [L]

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2. Interrupt based key data acquisition

• Flowchart

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LC75893M

• Timing chart

• Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t8 has elapsed by checking the DO state when CE is low and reading the key data. The period t8 in this technique must satisfy the following condition.

t8 > t4 If a key data read operation is executed when DO is high, the read key data (KD1 to KD20) and sleep acknowledge

data (SA) will be invalid.

T = ——

fosc

CE = [L]

DO = [L]

CE = [L]

DO = [H]

Page 23

PS No. 5971-23/23

LC75893M

This catalog provides information as of November, 1999. Specifications and information herein are subject to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment.

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Datasheet LC75893M Datasheet (SANYO)

Specifications and Main Features

Frequently Asked Questions

User Manual