Page 1
Ordering number : ENN7135
D2001TN (OT) No. 7135-1/24
Overview
The LC75863E and LC75863W are 1/3 duty LCD display
drivers that can directly drive up to 75 segments and can
control up to four general-purpose output ports. These
products also incorporate a key scan circuit that accepts
input from up to 30 keys to reduce printed circuit board
wiring.
Features
• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
• 1/3duty - 1/2bias and 1/3duty - 1/3bias drive schemes
can be controlled from serial data (up to 75 segments).
• Sleep mode and all segments off functions that are
controlled from serial data.
• Segment output port/general-purpose output port
function switching that is controlled from serial data.
• Serial data I/O supports CCB format communication
with the system controller.
• Direct display of display data without the use of a
decoder provides high generality.
• Independent V
LCD
for the LCD driver block (V
LCD
can
be set to in the range VDD-0.5 to 6.0 volts.)
• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
• RC oscillator circuit.
Package Dimensions
unit: mm
3156-QIP48E
unit: mm
3163A-SQFP48
14.0
17.2
1.5
1.5
1.6
0.15
0.35
0.1
15.6
0.8
1.0
3.0max
1
48
12
13
24
25
36
37
2.7
14.0
17.2
1.5
1.5
1.6
1.0
SANYO: QIP48E
[LC75863E]
0.5
7.0
9.0
0.15
0.180.75 0.5
0.75
0.75
0.5
0.75
0.5
0.1
112
13
24
25
36
37
48
7.0
9.0
1.7max
SANYO: SQFP48
[LC75863W]
LC75863E, 75863W
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
1/3 Duty LCD Display Drivers with Key Input Function
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Page 2
No. 7135-2/24
LC75863E, 75863W
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage
V
DD
max V
DD
–0.3 to +7.0
V
V
LCD
max V
LCD
–0.3 to +7.0
V
IN
1 CE, CL, DI –0.3 to +7.0
Input voltage V
IN
2 OSC,TEST –0.3 to VDD+0.3 V
V
IN
3 V
LCD
1, V
LCD
2, KI1 to KI5 –0.3 to V
LCD
+0.3
V
OUT
1 DO -0.3 to +7.0
Output voltage V
OUT
2 OSC –0.3 to VDD+0.3 V
V
OUT
3 S1 to S25, COM1 to COM3, KS1 to KS6, P1 to P4 –0.3 to V
LCD
+0.3
I
OUT
1 S1 to S25 300 µA
Output current
I
OUT
2 COM1 to COM3 3
I
OUT
3 KS1 to KS6 1 mA
I
OUT
4 P1 to P4 5
Allowable power dissipation Pd max Ta = 85°C 150 mW
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Specifications
Absolute Maximum Ratings at Ta=25°C, VSS=0V
Pin Assignment
KI3
KI4
VDD S23
COM1
KI5
S22
S21
S20
VLCD
VLCD1
VLCD2
VSS
LC75863E
(QIP48E)
LC75863W
(SQFP48)
TEST
OSC
DO
CE
CL
36
25
37 24
13
121
48 DI
KI1
KI2
KS4
KS5
KS6
COM3
KS1/S24
COM2
S11
S12
KS2/S25
KS3
S19
S18
S17
S16
S15
S14
S13
S7S8S9
S10
S5
S6
P3/S3
P4/S4
P1/S1
P2/S2
Top view
Parameter Symbol Conditions
Ratings
Unit
min typ max
Supply voltage
V
DD
V
DD
4.5 6.0
V
V
LCDVLCD
VDD– 0.5 6.0
Input voltage
V
LCD
1 V
LCD
1 2/3 V
LCD
V
LCD
V
V
LCD
2 V
LCD
2 1/3 V
LCD
V
LCD
Input high level voltage
V
IH
1 CE, CL, DI 0.8 V
DD
6.0
V
V
IH
2 KI1 to KI5 0.6 V
DD
V
LCD
Input low level voltage V
IL
CE, CL, DI, KI1 to KI5 0 0.2 V
DD
V
Allowable Operating Ranges at Ta = –40 to +85°C, VSS=0V
Continued on next page.
Page 3
No. 7135-3/24
LC75863E, 75863W
Parameter Symbol Conditions
Ratings
Unit
min typ max
Hysteresis V
H
CE, CL, DI, KI1 to KI5 0.1 V
DD
V
Power-down detection voltage V
DET
2.5 3.0 3.5 V
Input high level current I
IH
CE, CL, DI: VI= 6.0V 5.0 µA
Input low level current I
IL
CE, CL, DI: VI= 0V –5.0 µA
Input floating voltage V
IF
KI1 to KI5 0.05 V
DD
V
Pull-down resistance R
PD
KI1 to KI5: VDD= 5.0V 50 100 250 kΩ
Output off leakage current I
OFFH
DO: VO = 6.0V 6.0 µA
V
OH
1 KS1 to KS6: IO= –500µA V
LCD
– 1.0 V
LCD
– 0.5 V
LCD
– 0.2
Output high level voltage
V
OH
2 P1 to P4: IO= –1mA V
LCD
– 1.0
V
V
OH
3 S1 to S25: IO= –20µA V
LCD
– 1.0
V
OH
4 COM1 to COM3: IO= –100µA V
LCD
– 1.0
V
OL
1 KS1 to KS6: IO= 25µA 0.2 0.5 1.5
V
OL
2 P1 to P4: IO= 1mA 1.0
Output low level voltage V
OL
3 S1 to S25: IO= 20µA 1.0 V
V
OL
4 COM1 to COM3: IO= 100µA 1.0
V
OL
5 DO: IO= 1mA 0.1 0.5
V
MID
1 COM1 to COM3: 1/2bias, IO= ±100µA
1/2V
LCD
– 1.0 1/2V
LCD
+ 1.0
V
MID
2 S1 to S25: 1/3bias,IO= ±20µA
2/3V
LCD
– 1.0 2/3V
LCD
+ 1.0
Output middle level voltage *2 V
MID
3 S1 to S25: 1/3bias, IO= ±20µA
1/3V
LCD
– 1.0 1/3V
LCD
+ 1.0
V
V
MID
4 COM1 to COM3: 1/3bias,IO= ±100µA
2/3V
LCD
– 1.0 2/3V
LCD
+ 1.0
V
MID
5 COM1 to COM3: 1/3bias,IO= ±100µA
1/3V
LCD
– 1.0 1/3V
LCD
+ 1.0
Oscillator frequency fosc OSC: R
OSC
= 39kΩ, C
OSC
= 1000pF 30.4 38 45.6 kHz
I
DD
1 VDD:Sleep mode 100
I
DD
2 VDD: VDD= 6.0V, output open,fosc = 38kHz 270 540
Current drain
I
LCD
1 V
LCD
: Sleep mode 5
µA
I
LCD
2
V
LCD
: V
LCD
= 6.0V, output open, 1/2bias,
100 200
fosc = 38kHz
I
LCD
3
V
LCD
: V
LCD
= 6.0V, output open, 1/3bias,
60 120
fosc = 38kHz
Electrical Characteristics for the Allowable Operating Ranges
Note: *2. Excluding the bias voltage generation divider resistor built into V
LCD
1 and V
LCD
2. (See Figure 1.)
Parameter Symbol Conditions
Ratings
Unit
min typ max
Recommended external resistance R
OSC
OSC 39 kΩ
Recommended external capacitance C
OSC
OSC 1000 pF
Guaranteed oscillator range f
OSC
OSC 19 38 76 kHz
Data setup time t
ds
CL, DI :Figure 2 160 ns
Data hold time t
dh
CL, DI :Figure 2 160 ns
CE wait time t
cp
CE, CL :Figure 2 160 ns
CE setup time t
cs
CE, CL :Figure 2 160 ns
CE hold time t
ch
CE, CL :Figure 2 160 ns
High level clock pulse width tø
H
CL :Figure 2 160 ns
Low level clock pulse width tø
L
CL :Figure 2 160 ns
Rise time t
r
CE, CL, DI :Figure 2 160 ns
Fall time t
f
CE, CL, DI :Figure 2 160 ns
DO output delay time t
dc
DO RPU=4.7kΩ, CL=10pF *1 :Figure 2 1.5 µs
DO rise time t
dr
DO RPU=4.7kΩ, CL=10pF *1 :Figure 2 1.5 µs
Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPUand the load capacitance CL.
Continued from preceding page.
Page 4
1. When CL is stopped at the low level
Figure 2
No. 7135-4/24
LC75863E, 75863W
tdh
50%
VIH1
VIH1
VIL
VIL
VIH1
VIL
tdrtdc
tchtcstcp
tds
tr
CL
tøLtøH
tf
DO
DI
D1D0
CE
2. When CL is stopped at the high level
50%
VIH1
VIL
tdh
VIH1
VIL
VIH1
VIL
tdrtdc
tchtcstcp
tds
tf
CL
tøHtøL
tr
DO
DI
D1D0
CE
Figure 1
VLCD
To the common segment driver
Excluding these resistors.
V
LCD2
VLCD1
Page 5
Block Diagram
No. 7135-5/24
LC75863E, 75863W
VDET
CCB
INTERFACE
COM1
COM2
COM3
COMMON
DRIVER
CLOCK
GENERATOR
VSS
VLCD2
VLCD1
VLCD
CE
VDD
DI
TEST
CL
DO
OSC
KI5
KI4
KI3
KI2
KI1
KS6
KS5
KS4
KS3
S25/KS2
S24/KS1
KEY SCAN
KEY BUFFER
CONTROL
REGISTER
SHIFT REGISTER
SEGMENT DRIVER & LATCH
S1/P1
S3/P3
S2/P2
S4/P4
S5
S23
Page 6
No. 7135-6/24
LC75863E, 75863W
Pin Pin No. Function Active I/O
Handling
when unused
S1/P1 1
S2/P2 2
S3/P3 3 —
●● OPEN
S4/P4 4
S5 to S23 5 to 23
COM1 24
COM2 25 — ●● OPEN
COM3 26
KS1/S24 27
KS2/S25 28
— O OPEN
KS3 to KS6 29 to 32
KI1 to KI5 33 to 37 H I GND
OSC 44 — I/O V
DD
CE 46 H I
CL 47 I GND
DI 48 — I
DO 45 — O OPEN
TEST 43 This pin must be connected to ground. — I —
V
LCD
1 40 — I OPEN
V
LCD
2 41 — I OPEN
V
DD
38 — — —
V
LCD
39 — — —
V
SS
42 Power supply connection. Connect to ground. — — —
Pin Functions
Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial
data control.
Common driver outputs
The frame frequency fo is given by : fo = (f
OSC
/384)Hz.
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in the timing lines
to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs are used to form a key
matrix. The KS1/S24 and KS2/S25 pins can be used as segment outputs when so
specified by the control data.
Key scan inputs
These pins have built-in pull-down resistors.
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and capacitor at this
pin.
Serial data interface connections to the controller. Note that DO, being an open-drain
output, requires a pull-up resistor.
CE :Chip enable
CL :Synchronization clock
DI :Transfer data
DO :Output data
▲
Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to
VLCD2 when a 1/2 bias drive scheme is used.
Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to
VLCD1 when a 1/2 bias drive scheme is used.
Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V.
LCD driver block power supply connection. Provide a voltage of between VDD–0.5 and
6.0V.
Page 7
Serial Data Input
1. When CL is stopped at the low level
No. 7135-7/24
LC75863E, 75863W
B3B2B1B0
0DRSCP2P1P0K1K0S1S0D2D1010
Control Data
Display Data
DO
DI
CL
CE
00000
A3A2A1A0
0 000 1
D39D38D37D36D35D34
0 0
DD
B3B2B1B0
10000000000000000000
D75D74D73D41
D40010
Fixed Data
Display Data
A3A2A1A0
0 000 1
DD
A3B3B2B1B0
0DRSCP2P1P0K1K0S1S0
D2D1
Control Data
Display Data
DO
DI
CL
CE
000000
D39D38D37
A2A1 A0
01010 000
D34 D35 D36
0
DD
A3B3B2B1B0
1
D74D73 D75
Fixed Data
Display Data
0 0 0 00000
A2A1A0
D40 D41
000 00 1 01 0 0 0 0 0 0 0 0 0 0 0
DD
2. When CL is stopped at the high level
Note: B0 to B3, A0 to A3
......
CCB address
DD
................................
Direction data
Note: B0 to B3, A0 to A3
......
CCB address
DD
................................
Direction data
CCB address
........
42H
D1 to D75
..............
Display data
S0,S1
....................
Sleep control data
K0,K1
....................
Key scan output/segment output selection data
P0 to P2
................
Segment output port/general-purpose output port selection data
SC
........................
Segment on/off control data
DR
........................
1/2 bias or 1/3 bias drive selection data
Page 8
Control Data Functions
1. S0, S1 : Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan
outputs during key scan standby.
Note: This assumes that the KS1/S24 and KS2/S25 output pins are selected for key scan output.
No. 7135-8/24
LC75863E, 75863W
Control data
Mode OSC oscillator
Segment outputs
Output pin states during key scan standby
S0 S1
Common outputs
KS1 KS2 KS3 KS4 KS5 KS6
0 0 Normal Operating Operating H H H H H H
0 1 Sleep Stopped L L L L L L H
1 0 Sleep Stopped L L L L L H H
1 1 Sleep Stopped L H H H H H H
2. K0, K1 : Key scan output /segment output selection data
These control data bits switch the functions of the KS1/S24 and KS2/S25 output pins between key scan output and
segment output.
X: don’t care
Note: KSn(n=1 or 2) : Key scan output
Sn (n=24 or 25): Segment output
Control data Output pin state
Maximum number of
K0 K1 KS1/S24 KS2/S25
input keys
0 0 KS1 KS2 30
0 1 S24 KS2 25
1 X S24 S25 20
3. P0 to P2 : Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Note: Sn(n=1 to 4): Segment output port
Pn(n=1 to 4): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports.
For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (V
LCD
) when the display data
D10 is 1, and will output a low level (Vss) when D10 is 0.
Control data Output pin state
P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4
0 0 0 S1 S2 S3 S4
0 0 1 P1 S2 S3 S4
0 1 0 P1 P2 S3 S4
0 1 1 P1 P2 P3 S4
1 0 0 P1 P2 P3 P4
Output pin Corresponding display data
S1/P1 D1
S2/P2 D4
S3/P3 D7
S4/P4 D10
Page 9
No. 7135-9/24
LC75863E, 75863W
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment
output pins.
SC Display state
0 on
1 off
4. SC : Segment on/off control data
This control data bit controls the on/off state of the segments.
DR Drive scheme
0 1/3 bias drive
1 1/2 bias drive
5. DR : 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
Display Data and Output Pin Correspondence
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S24 and KS2/S25 are selected for use as segment outputs.
Output pin COM1 COM2 COM3
S1/P1 D1 D2 D3
S2/P2 D4 D5 D6
S3/P3 D7 D8 D9
S4/P4 D10 D11 D12
S5 D13 D14 D15
S6 D16 D17 D18
S7 D19 D20 D21
S8 D22 D23 D24
S9 D25 D26 D27
S10 D28 D29 D30
S11 D31 D32 D33
S12 D34 D35 D36
S13 D37 D38 D39
Output pin COM1 COM2 COM3
S14 D40 D41 D42
S15 D43 D44 D45
S16 D46 D47 D48
S17 D49 D50 D51
S18 D52 D53 D54
S19 D55 D56 D57
S20 D58 D59 D60
S21 D61 D62 D63
S22 D64 D65 D66
S23 D67 D68 D69
KS1/S24 D70 D71 D72
KS2/S25 D73 D74 D75
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31 D32 D33
0 0 0 The LCD segments for COM1, COM2 and COM3 are off.
0 0 1 The LCD segment for COM3 is on.
0 1 0 The LCD segment for COM2 is on.
0 1 1 The LCD segments for COM2 and COM3 are on.
1 0 0 The LCD segment for COM1 is on.
1 0 1 The LCD segments for COM1 and COM3 are on.
1 1 0 The LCD segments for COM1 and COM2 are on.
1 1 1 The LCD segments for COM1, COM2 and COM3 are on.
Page 10
CE
B1B0
111
DO
DI
CL
Output data
X: don’t care
00
SA
KD28KD27KD2KD1
X
0 00
B3B2 A1A0 A3A2
KD30KD29
CE
B1B0
111
DO
DI
CL
Output data
X: don’t care
0 00
SA
KD29KD28KD3KD2KD1
XX
00
B3B2 A1A0 A3A2
KD30
No. 7135-10/24
LC75863E, 75863W
Serial Data Output
1. When CL is stopped at the low level
Note: B0 to B3, A0 to A3······CCB address
2. When CL is stopped at the high level
Note: B0 to B3, A0 to A3······CCB address
CCB address
......
43H
KD1 to KD30
........
Key data
SA
........................
Sleep acknowledge data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
Page 11
Output Data
1. KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
When the KS1/S24 and KS2/S25 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
No. 7135-11/24
LC75863E, 75863W
KI1 KI2 KI3 KI4 KI5
KS1/S24 KD1 KD2 KD3 KD4 KD5
KS2/S25 KD6 KD7 KD8 KD9 KD10
KS3 KD11 KD12 KD13 KD14 KD15
KS4 KD16 KD17 KD18 KD19 KD20
KS5 KD21 KD22 KD23 KD24 KD25
KS6 KD26 KD27 KD28 KD29 KD30
Page 12
2. In normal mode
• The pins KS1 to KS6 are set high.
• When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
• If a key is pressed for longer than 615T(s) (Where T= ) the LC75863E/W outputs a key data read request (a
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75863E/W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10 kΩ).
No. 7135-12/24
LC75863E, 75863W
Key on
576T[s]
*3
*3 *3
*3 *3
*3 *3
*3 *3
11
22
33
44
55
66
KS4
KS5
KS6
KS3
KS2
*3KS1
T=
1
fosc
Key data read request Key data read request Key data read request
Key data read Key data read Key data read
DO
DI
Key address
(43H)
Key address
Key address
Serial data
transfer
Serial data
transfer
Serial data
transfer
CE
615T[s] 615T[s] 615T[s]
Key scan
Key input 2
Key input 1
T=
1
fosc
Note: *3.In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from
pins that are set low.
1
——
fosc
Key Scan Operation Functions
1. Key scan timing
The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75863E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75863E/W cannot detect a key press shorter than 615T(s).
Page 13
No. 7135-13/24
LC75863E, 75863W
3. In sleep mode
• The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
• If a key is pressed for longer than 615T(s)(Where T= ) the LC75863E/W outputs a key data read request (a
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75863E/W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 kΩ).
• Sleep mode key scan example
Example: S0=0, S1=1 (sleep with only KS6 high)
Multiple Key Presses
Although the LC75863E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
KI1
KI2
KI3
KI4
KI5
*4
When any one of these keys is pressed,
the oscillatior on the OSC pin is started
and the keys are scanned.
Serial data
transfer
Key data read request
Key data read Key data read
DO
DI
Serial data
transfer
Key address
(43H)
Key address
Serial data
transfer
CE
Key scan
Key input
(KS6 line)
615T[s] 615T[s]
Key data read request
T=
1
fosc
1
——
fosc
Note: *4.These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5
lines are pressed at the same time.
Page 14
1/3 Duty, 1/2 Bias Drive Technique
1/3 Duty, 1/2 Bias Waveforms
No. 7135-14/24
LC75863E, 75863W
COM3
COM2
COM1
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are on.
LCD driver output when LCD
segments corresponding to COM2
and COM3 are on.
LCD driver output when LCD
segments corresponding to COM1
and COM3 are on.
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are turned off.
LCD driver output when only LCD
segments corresponding to COM1
are on
LCD driver output when only LCD
segments corresponding to COM2
are on.
LCD driver output when only LCD
segments corresponding to COM3
are on.
LCD driver output when LCD
segments corresponding to COM1
and COM2 are on.
VLCD1, VLCD2
VLCD
0V
[Hz]
fosc
384
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
VLCD1, VLCD2
VLCD
0V
Page 15
No. 7135-15/24
LC75863E, 75863W
1/3 Duty, 1/3 Bias Drive Technique
1/3 Duty, 1/3 Bias Waveforms
COM3
COM2
COM1
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are on.
LCD driver output when LCD
segments corresponding to COM2
and COM3 are on.
LCD driver output when LCD
segments corresponding to COM1
and COM3 are on.
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are turned off.
LCD driver output when only LCD
segments corresponding to COM1
are on
LCD driver output when only LCD
segments corresponding to COM2
are on.
LCD driver output when only LCD
segments corresponding to COM3
are on.
LCD driver output when LCD
segments corresponding to COM1
and COM2 are on.
[Hz]
fosc
384
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
VLCD2
VLCD1
VLCD
0V
Page 16
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage VDDrise time when the logic block power is first applied and the
logic block power supply voltage VDDfall time when the voltage drops are both at least 1 ms. (See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3.)
• Power on :Logic block power supply(VDD) on → LCD driver block power supply(V
LCD
) on
• Power off:LCD driver block power supply(V
LCD
) off → Logic block power supply(VDD) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75863E/W supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset methods
• Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage VDDrise time when logic block power is applied, a system
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is
assured as the logic block supply voltage VDDfall time when logic block power drops, a system reset will be applied in
the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the
point when all the serial data (the display data D1 to D75 and the control data) has been transferred, i.e., on the fall of the
CE signal on the transfer of the last direction data, after all the direction data has been transferred (see Figure 3).
No. 7135-16/24
LC75863E, 75863W
Display and control data transfer
D1 to D39
Internal data
Internal data
S0, S1, K0, K1
P0 to P2, SC, DR
(D40 to D75)
VDD
CE
VLCD
Undefined
Undefined
Undefined
Undefined
System reset period
Defined
Defined
VIL
t3t2 t4t1
VDET
VDET
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDDrise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage V
DD
fall time)
Figure 3
Page 17
2. LC75863E/W internal block states during the reset period
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
No. 7135-17/24
LC75863E, 75863W
CCB
INTERFACE
COM1
COM2
COM3
COMMON
DRIVER
CLOCK
GENERATOR
VSS
VLCD2
VLCD1
VLCD
CE
VDD
DI
TEST
CL
DO
OSC
KI5
KI4
KI3
KI2
KI1
KS6
KS5
KS4
KS3
S25/KS2
S24/KS1
KEY SCAN
KEY BUFFER
CONTROL
REGISTER
SHIFT REGISTER
SEGMENT DRIVER & LATCH
S1/P1
S3/P3
S2/P2
S4/P4
S5
S23
VDET
Blocks that are reset
Page 18
No. 7135-18/24
LC75863E, 75863W
3. Output pin states during the reset period
X: don’t care
Note: *5.These output pins are forcibly set to the segment output function and held low.
*6.When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*7.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
Output pin State during reset
S1/P1 to S4/P4 L *5
S5 to S23 L
COM1 to COM3 L
KS1/S24, KS2/S25 L *5
KS3 to KS5 X *6
KS6 H
DO H *7
Sample Application Circuit 1
1/2 bias (for use with normal panels)
C ≥ 0.047 µF
To the controller
power supply
To the controller
From the
controller
+5.5 V
+5 V VDD
S23
S5
P4/S4
P3/S3
P2/S2
P1/S1
COM3
(general-purpose
output ports)
(P1)
(P2)
(P3)
(S24)
(S25)
(P4)
COM1
OSC
COM2
DO
DI
CL
*8
C
*9
Key matrix
(up to 30 keys)
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
2
5
/
K
S
2
S
2
4
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
LCD panel (up to 75 segments)
K
S
5
K
S
6
Used with the
backlight controller
or other circuit.
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 19
No. 7135-19/24
LC75863E, 75863W
Sample Application Circuit 2
1/2 bias (for use with large panels)
To the controller
power supply
To the controller
From the
controller
Used with the
backlight controller
or other circuit.
(general-purpose
output ports)
Key matrix
(up to 30 keys)
LCD panel (up to 75 segments)
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
+5.5 V
+5 V VDD
S23
S5
P4/S4
P3/S3
P2/S2
P1/S1
COM3
(P1)
(P2)
(P3)
(S24)
(S25)
(P4)
COM1
OSC
COM2
DO
DI
CL
*8
R
RC
*9
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
2
5
/
K
S
2
S
2
4
/
K
S
1
K
S
3
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
5
K
S
6
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 20
No. 7135-20/24
LC75863E, 75863W
Sample Application Circuit 3
1/3 bias (for use with normal panels)
To the controller
power supply
To the controller
From the
controller
(general-purpose
output ports)
Key matrix
(up to 30 keys)
LCD panel (up to 75 segments)
C ≥ 0.047 µF
+5.5 V
+5 V VDD
S23
S5
P4/S4
P3/S3
P2/S2
P1/S1
COM3
(P1)
(P2)
(P3)
(S24)
(S25)
(P4)
COM1
OSC
COM2
DO
DI
CL
*8
C C
*9
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
2
5
/
K
S
2
S
2
4
/
K
S
1
K
S
3
K
S
5
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
6
Used with the
backlight controller
or other circuit.
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 21
No. 7135-21/24
LC75863E, 75863W
Sample Application Circuit 4
1/3 bias (for use with large panels)
To the controller
power supply
To the controller
From the
controller
(general-purpose
output ports)
Key matrix
(up to 30 keys)
LCD panel (up to 75 segments)
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
+5.5 V
+5 V VDD
S23
S5
P4/S4
P3/S3
P2/S2
P1/S1
COM3
(P1)
(P2)
(P3)
(S24)
(S25)
(P4)
COM1
OSC
COM2
DO
DI
CL
*8
C C
R
R
R
*9
CE
VLCD1
VLCD2
VLCD
TEST
VSS
S
2
5
/
K
S
2
S
2
4
/
K
S
1
K
S
3
K
S
5
K
S
4
K
I
1
K
I
2
K
I
3
K
I
4
K
I
5
K
S
6
Used with the
backlight controller
or other circuit.
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDDrise time when power is applied and the
logic block power supply voltage V
DD
fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
The display data (D1 to 75) is transferred to the LC75863E/W in two operations. All of the display data should be
transferred within 30 ms to maintain the quality of the displayed image.
Page 22
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
(2) Timing chart
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(1230T(s))
t7: Key address (43H) transfer time
t8: Key data read time
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
1
T = ———
fosc
No. 7135-22/24
LC75863E, 75863W
Key data read
processing
YES
NO
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key off)
Key data read request
Key data read
DO
DI
CE
Key onKey on
Key
address
Key scan
Key input
t6
t9t9t9t9
t5
t8 t8
t7 t7
t5
t7
t8
t5
Page 23
No. 7135-23/24
LC75863E, 75863W
2. Interrupt based key data acquisition
(1) Flowchart
(2) Timing chart
t5: Key scan execution time when the key data agreed for two key scans. (615T(S))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(1230T(S))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ———
fosc
Key data read
processing
YES
YES
NO
Wait for at
least t10
Key OFF
NO
t7
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Key data read request
Key data read
DO
DI
CE
Key onKey on
Key
address
Key scan
Key input
t10t10 t10t10
t5 t6
t8 t8
t7
t5
t7
t8
t5
t7
t8
Page 24
PS No. 7135-24/24
LC75863E, 75863W
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10 has
elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must
satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
This catalog provides information as of December, 2001. Specifications and information herein are
subject to change without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
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