Page 1
INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
■
Quad low-side switch
■
2 x 5A designed as conventional switch
■
2 x 2.5A designed as switched current-regulator
■
Low ON-resistance 2 x 0.2Ω, 2 x 0.35Ω (typ.)
■
Power SO-36 - package with integrated
cooling area
■
Integrated free-wheeling and clamping Z-diodes
■
Output slope control
■
Short circuit protection
■
Selective overtemperature shutdown
■
Open load detection
■
Ground and supply loss detection
■
External clock control
■
Recirculation control
■
Regulator drift detection
■
Regulator error control
■
Regulator resolution 5mA
■
Status monitoring
■
Status push-pull stages
■
Electrostatic discharge (ESD) protection
L9347
PowerSO-36 BARE DIE
ORDERING NUMB ERS :
L9347PD L9347DIE1
DESCRIPTION
The L9347 is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current
regulators with current range from 250mA to 2.25A
and an accuracy of 10%.
All channels are protected against fail functions.
They are monitored by a status output.
Figure 1. Pin Connection
99AT0060
June 2002
GND 1
PGND3
PGND3
Q3
Q3
D3
D3
Q1
Q1
Q2
Q2
D4
D4
Q4
Q4
PGND4
PGND4
N.C.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
CLK
ST3
IN1
IN3
ST1
PGND1
PGND1
VS
PGND2
PGND2
TEST
EN
ST2
IN4
IN2
ST4
VDD
VCC
1/21
Page 2
L9347
Figure 2. Block Diagram
EN
VS VCC VDD
Internal Supply
CLK
IN1
ST1
IN4
ST4
IN2
Overtemperature
Channel 4
Overtemperature
Channel 3
LOGIC
LOGIC
&
DA
LOGIC
Overtemperature
Channel 1
Open Load
Overload
GND-det.
Open Load
Overload
GND-det.
Overtemperature
Channel 2
Open Load
Overload
Q1
IPD
D4
Q4
IPD
Q2
2/21
ST2
IN3
ST3
TEST
99AT0059
drift-det.
LOGIC
&
DA
GND-det.
Open Load
Overload
GND-det.
IPD
D3
Q3
IPD
GND
Page 3
PIN DESCRIPTION
N° Pin Function
1 GND Logic Ground
2, 3 PGND 3 Power Ground Channel 3
4, 5 Q 3 Power Output Channel 3
6, 7 D 3 Free-Wheeling Diode Channel 3
8, 9 Q 1 Power Output Channel 1
10, 11 Q 2 Power Output Channel 2
12, 13 D 4 Free-Wheeling Diode Channel 4
14, 15 Q 4 Power Output Channel 4
16, 17 PGND 4 Power Ground Channel 4
18 NC Not Connected
19 VCC 5V Supply
20 VDD 5V Supply
L9347
21 ST 4 Status Output Channel 4
22 IN 2 Control Input Channel 2
23 IN 4 Control Input Channel 4
24 ST 2 Status Output Channel 2
25 EN Enable Input for all four Channels
26 TEST Enable Input for Drift detection
27, 28 PGND 2 Power Ground Channel 2
29 VS Supply Voltage
30, 31 PGND 1 Power Ground Channel 1
32 ST 1 Status Output Channel 1
33 IN 3 Control Input Channel 3
34 IN 1 Control Input Channel 1
35 ST 3 Status Output Channel 3
36 CLK Clock Input
3/21
Page 4
L9347
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is subjected to conditions which are beyond these values.
Symbol Parameter Test Conditions Min Typ Max Unit
E
Q
Voltages
V
S
V
, V
CC
V
Q
V
Q
V
, V
IN
V
CLK
V
ST
V
D
V
DRmax
Currents
I
Q1/2
I
Q3/4
I
Q1/2
I
PGND1/2
I
Q3/4
I
PGND3/4
I
ST
ESD Protection
ESD Elec trost atical Disch argin g MIL883C ±2kV
ESD Output Pins (Qx, Dx) vs. Common GND
Switch off energy for inductive loads 50 mJ
Supply voltage -0.3 40 V
Supply voltage -0.3 6 V
DD
Output voltage static 40 V
Output voltage during clamping t < 1ms 60 V
Input voltage IN1 to IN4, EN II < |10|mA -1.5 6 V
EN
Input Voltage CLK -1.5 6 V
Output voltage status -0.3 6 V
Recirculation circuits D3, D4 40 V
max. reverse breakdown voltage of free
wheeling diodes D3, D4
Output current for Q1 and Q2 >5
Output current for Q3 and Q4 >3
,
Output current at reversal supply for Q1
-4 A
and Q2
,
Output current at reversal supply for
-2 A
Q3 and Q4
Output current status pin -5 5 mA
±4kV
(PGND1-4 + GND)
55 V
internal
limited
internal
limited
A
A
THERMAL DATA
Symbol Parameter Test Conditions Min Typ Max Unit
T
j
T
jc
Junction temperature T
Junction temperature during clamping
(life time)
T
stg
T
th
T
hy
R
thJC
(1) This parameter will not be tested but assured by design.
Storage temperature T
Overtemperature shutdown threshold
Overtemperature shutdown hysteresis
Thermal resistance junction to case R
4/21
j
t = 30min
Σ
t = 15min
Σ
stg
(1)
(1)
thJC
-40 150 °C
175
190
-55 150 °C
175 200 °C
10 °C
2 K/W
°C
Page 5
L9347
OPERATING RANGE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
, V
V
CC
dV
S
V
V
V
ST
I
ST
T
T
jc
.
ELECTRICAL CHARACTERISTCS
(Vs = 4.8 to 18V; T
Symbol Parameter Test Condition Min. Typ. Max. Unit
Supply voltage 4.8 18 V
S
Supply voltage 4.5 5.5 V
DD
/dt Supply voltage transient time -1 1
Output voltage static -0.3 40 V
Q
Output voltage induced by inductive switching Voltage will be
Q
limited by internal
Z-diode clamping
Output voltage status -0.3 6 V
Output current status -1 1 mA
Junction temperature -40 150 °C
j
Junction temperature during clamping
= 30min
Σ
= 15min
Σ
:
= -40 to 150°C unless otherwise specified)
j
60 V
175
190
V/
°C
s
µ
Power Supply
I
SON
I
SOFF
Supply current
Quiescent current
I
Supply current VCC (analog supply) VCC =5V 5 mA
cc
I
Supply current VDD (digital supply) VDD =5V f
dd
I
Supply current VDD (digital supply) VDD =5V f
dd
General Diagnostic Functions
V
V
thGND
V
thPGL
f
CLK,min
DC
DC
high
Open load voltage
QU
Signal-GND-loss threshold VCC= 5V 0.1 1 V
Power-GND-loss thresh old VCC = 5V 1.5 2.5 3.5 V
Clock frequency error 10 100 kHz
Clock duty cycle error detection low f
CLKe_l
ow
Clock duty cycle error detection high f
CLKe_
V
S
≤ 18V
5mA
(outputs ON)
V
S
≤ 18V
5mA
(outputs OFF)
=0Hz 5 uA
CLK
=250kHz 5 mA
CLK
V
S
≥ 6.5V
0.3 0.33 0.36 x V
(outputs OFF)
= 250 kHz 33,3 45 %
CLK
= 250 kHz 55 66,6 %
CLK
Q
VS
Supply detection VCC = VDD = 5V 2 4.5 V
loss
Additional Diagnostic Functions channel 1 and channel 2 (non regulated channels)
I
QU1,2
I
QO1,2
Open-load current channel 1, 2
Over-load current channel 1, 2
V
S
V
S
≥ 6.5V
≥ 6.5V
50 140 mA
57.59 A
5/21
Page 6
L9347
ELECTRICAL CHARACTERISTCS
:
(continued)
(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Additional Diagnostic Functions channel 3 and channel 4 (regulated channels)
DC
I
QO3,4
V
PWM
Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
V
V
Digital Outputs (ST1 to ST4)
V
Output duty cycle range filtered with 10ms 10 90 %
OUT
Overload current
V
S
≥ 6.5V
2.5 5 8 A
channel 3,4
Recirculation error shutdown
rerr
Iout > 50mA 45 50 60 V
threshold (open D3/D4)
Output PWM ratio during drift
dOU
T
comparison
Input low voltage -0.3 1 V
V
IL
Input high voltage 2 6 V
IH
IHy
Input voltage hysteresis
I
Input pull down current
I
STL
Status output voltage in low state
(1)
(2)
V
= V
IN3
V
V
IN4
= H
TEST
= 5V, VS ≥ 6.5V
IN
IST ≤ 40µA
= PWM
IN
-14.3 +14.3 %
20 500 mV
82040
0 0.4 V
A
µ
V
STH
Status output voltage in high state
R
DIAGLROUT
R
DIAGHROUT
+ R
+ R
DSON
DSON
Power Outputs (Q1 to Q4)
R
DSON1,2
Static drain-source ON-resistance
Q1 and Q2
(non-reg. channels)
R
DSON3,4
Static drain-source ON-resistance
Q3 and Q4
(reg. channels)
V
F_250mA
Forward voltage of free wheeling path
D3, D4 @250mA
V
F_2.25A
Forward voltage of free wheeling path
D3, D4 @2.25A
R
Sense resistor = (V
sens
2A
2)
IST ≥ -40µA
I
≥ -120µA
ST
2.5 3.45 V
23.45V
in low state 0.3 0.64 1.5
in high state 1.5 3.2 7.0
= 1A; VS ≥ 9.5V
I
Q
0.2
0.5
0.5
0.35
0.75
0.75
1
F_2.25A-VF_250mA
= 25°C
T
j
Tj = 125°C
Tj = 150°C
= 1A; VS ≥ 9.5V
I
Q
= 25°C
T
j
= 125°C
T
j
Tj = 150°C
I
D3/4
I
D3/4
)/
(3)
(4)
3)
4)
= -250mA 0.5 1.5 V
= -2.25A 2.0 4.5 V
k
Ω
k
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
6/21
Page 7
L9347
ELECTRICAL CHARACTERISTCS
:
(continued)
(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
Z-diode clamping voltage
Z
I
Output pull down current VEN = H, VIN = L 10 150
PD
I
Output leakage current VEN = L; VQ = 20V 5
Qlk
Timing
t
t
t
OFFREG
t
Output ON delay time
ON
Output OFF delay time channel
OFF
Output OFF delay time regulator
Output rise time
t
r
Output fall time
t
f
t
sf
Short error detection filter time f
t
lf
Long error detection filter time f
Short circuit switch-OFF delay time
SCP
t
Status delay time
D
t
Regulation error status delay time
RE
≥ 100mA
I
Q
= 1A
I
Q
IQ = 1A
(5)
IQ = 1A
= 1A
I
Q
= 250kHz DC = 50%
CLK
= 250kHz DC = 50%
CLK
(5)
(5)
(5)
(reg. channels only)
(5)
(5)
45 60 V
0520
01030
528
0.5 1.5 8
0.5 1.5 8
48
16 32
430
896 1024 us
10 ms
A
µ
A
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
t
Dreg
Output off status delay time
(5)
(reg. channels only
528
Reg. Current Accuracy (reg. channels only)
I
Q3/Q4
I
Q3/Q4
I
I
∆
REG
Minimum current DC = 10% 200 250 300 mA
Maximum current DC = 90% 2 2.25 2.5 A
Max. regulation deviation @
DC 10% - 90%
Min. quant. step 5 mA
Q3/Q4
250mA < I
400mA ≤ I
800mA < I
Q3/Q4
Q3/Q4
Q3/Q4
< 400mA
≤ 800mA
< 2.25A
Frequencies
CLK frequency crystal-controlled 250 kHz
Input PWM frequency (reg. channels only) 2 kHz
(1) This parameter will not be tested but assured by design
(2) Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
(3) Measured chip, bond wires not i ncluded
(4) Measured on Power SO-36 devices
(5) Digital filtered with external clock, only functional test
±10
±6
±10
s
µ
%
%
%
7/21
Page 8
L9347
1.0 Functional Description
1.1 Overv iew
The L9347 is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. Integrated active Zener-clamp (for channel1 and 2) or free wheeling diodes (for channel 3 and 4) allow the recirculation of the inductive loads. All four channels are monitored with a status output. All wiring to the loads and
supply pins of the device are controlled. The device is self-protected against shor t circuit at the outputs and overtemperature. For each channel one independent push-pull status output is used for a parallel diagnostic function.
Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target output current. The
output current is controlled through the output PWM of the power stage. The regulator limits of 10% or 90% are
detected and monitored with the status signal. The current is measured during recirculation phase of the load.
A test mode compares the differences between the two regulators. This “drift” test compares the output PWM
of the regulators. By this feature a drift of the load during lifetime can be detected.
1.2 In put Ci rc ui ts
The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with hysteresis. All inputs
are connected to pull-down current sources.
1.3 O utput Stages (not regulated) C hannel 1 and 2
The two power outputs (5A) consist of DMOS-power transistors with open drain output. The output stages are
protected against short circuit. Via integrated Zener-clamp-diodes the overvoltage of the inductive loads due to
recirculation are clamped to typ. 52V for fast shut off of the valves. Parallel to the DMOS transistors there are
internal pull-down current sources. They are provided to assure an open load condition in the OFF-state. With
EN=low this current source is switched off, but the open load comparator is still active.
1.4 Current-Regulator-Stages Channel 3 and 4
The current-regulator channel s ar e des igned to drive i nductive loads. The target val ue of the current is given by
the duty cycle (DC) of the 2kHz PWM input signal. The following figure shows the relation between the input
PWM and the output current and the specified
accuracy
.
Figure 3. Input PWM to output current range
2250
ion
s
t preci
n
Curre
90
400
250
800
OUTPUT Current [mA]
+- 6%
±10%
10
+-10%
INPUT PWM[%]
8/21
Page 9
L9347
The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock.
For requested precision of the output current the ratio between the frequencies of the input signal and the external 250kHz clock has to be fixed according to the graph shown in Fig.
Figure 4. Current accuracy according to the input and clock frequency ratio
current accuracy
5.6%
112.5
125
132
0%
-10%
Regulator
switched off
f
CLK
/ f
IN
The theoretical error is zero for f
/ fIN = 125.
CLK
If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For
a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision applications the clock frequency and the input frequency have to be correlated.
The output current is measu red during the recir culati on of the load. The c urrent sense resistor is in series to the
free wheeling diode. If this recircul ation path is inter rupted the regulator stops immed iately and the status output
remains low for the rest of the input cycle.
The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is
3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output
and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of
the power is 256µs after the first negative edge of the input signal.
As regulator a digital PI-regulator with the Transfer function for:
KI: and KP: 0.96
0.126
-------------- -
z1–
for a sampling time of 256us is realised.
To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current
value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90%
during the regulation. The status output gets low if the target current value is not reached within the regulation
t
error delay time of
=10ms. The output PWM is than out of the regulation range from 10% to 90%.
RE
1.5 Protective Circuits
The outputs are protected against cur rent over lo ad, overtemperatur e, and power -GND-loss. The ex ternal cloc k
is monitored by a clock watchdog. This clock watchdog detects a minimal frequency
f
and wrong clock
CLK,min
duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected
9/21
Page 10
L9347
against recirculation er rors, w hen D3 or D4 is not connecte d. All these er ror conditions shut off the power stage
and invert the status output information.
1.6 Error Detection
The status outputs indicat e the switching state under normal conditions ( status LOW = OFF; stat us HIGH = ON).
If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All external errors, for example open load, are filtered internally. The following table shows the detected errors, the
filter times and the detection mode (on/off).
Short circuit of the load
Open load
(under voltage detection)
Open load
(under current detection)
Overtemperature
Power-GND-loss
Signal-GND-loss
Supply-VS-loss
Clock control
Output voltage clamp active
ON State
EN &IN = HIGH
Xt
Xt
Xt
XXt
XXt
XXt
X X no in on: EN & IN = “LOW”
X
(regulated
channels)
OFF State
EN &IN = LOW
Xt
Filter time Reset done by
sf
lf
sf
sf
lf
lf
lf
no in on: EN & IN = “LOW”
EN & IN = “LOW”
for
or
T
T
D
Dreg
timer
T
D
timer
T
D
EN & IN = “LOW”
for
or
T
T
D
Dreg
in on: EN & IN = “LOW”
for
or
T
T
D
Dreg
in off: timer
timer
timer
or
for
T
D
in off: timer
or
for
T
D
in off: timer
T
T
T
T
D
D
Dreg
Dreg
T
D
T
D
T
D
EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input
PWM. For the regulator input period l onger than T
A detected error is stored in an error register. The reset of this register is made with a timer T
proach all errors are present at the status output at least for the time T
and for the standard channel input perio d longer thanTD.
Dreg
. With this ap-
D
.
D
All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON
condition are stored into an internal “fail” register. The output is then shut off. The register must be reset with a
low signal at the input. A “low signal” means that the input is low for a time longer than T
or T
D
DReg
for the re-
ulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode.
Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail r egis ter. This type
t
of error is only delayed with the standard timer
function.
lf
Open load is detected for all four channels in on- and off-state.
Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error reg-
ister is set and delayed with T
. A sink current stage pull the output down to ground, with EN high. With EN low
D
the output is floating in case of openload and the detection is not assured. In the ON state the load current is
monitored by the non-regulated channels. If it drops below the specified threshold value I
detected and the error register is set and delayed with T
. A regulated channel detects the open load in the on
D
state with the current regulator error detection. If the output PWM reaches 90% for a time longer than t
an open load is
QU
RE
than
an error occurs. This c ould happen when no load is c onnected, the resistivi ty of the l oad is too high or the suppl y
voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time
, so the output PWM falls below 10%.
t
RE
A clock failure (clock loss) is detected when the frequency becomes lower than
f
. All status outputs are
CLK,min
10/21
Page 11
L9347
set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is
present again. A clock failure during power on of VCC is detected only on the regulated channels. The status
outputs of the channel 1 and 2 are low in this case.
1.7 Drift Detection (regulated channels only)
The drift detection is used to compare the two regulated channels during regulation. This “Drift” test compares
the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated formula for the output current below shows the depen dency of the load resi stor to the output PWM. In this formula
the energy reduction dur ing the recirculati on is not taken into account. The real output PWM i s high er. The testmode is enabled with IN,EN and TEST high. With an identical 2kH z PWM-Si gnal c onnected to the I N-inputs the
output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than ±14.3% of
the expected value an error is detected and monitored by the status outputs, in the same way as described
above, but a drift error will not be registered and also not delayed with T
IOUT
----------------------------
RL RON+
PWM⋅=
VBAT
Drift Definition:
Drift = PWM(1+E) - PWM (1-E) = 2PWM E
Drift * 4 < PWM (1+E)
with E >14.3% a drift is detected
as other errors
D
E.. not correlated Error of the channels
%PWM ... Corresponding ideal output PWM to a given input PWM
A 7bit output-PWM-register is used for the comparison. The register with the lower val ue is subtracted from the
higher one. This result is multiplied by four and compared with the higher value.
1.8 Other Test modes
The test pin is also used to test the regulated channels in the production. With a special sequence on this pin
the power stages of the regulated channels can be controlled direct from the input. No status feedback of the
regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indication of a proper logic functionality. The following table shows the functionality of this special test mode
EN IN TEST OUT STATUS Note
1
1
0
0
0
0
0
X X X X disable test mode
1 1 on 1 Drift mode
X off test pattern test condition one
X off test pattern test condition two
X off test pattern test condition three
0 off test pattern test condition four
1 on test pattern test condition four
For more details about the test condition four see timing diagram.
11/21
Page 12
L9347
Diagnostic Table
The status follows the input signal in normal operating conditions.
If any error is detected the status is inverted.
Operating Condition Test
Input
TEST
Normal function L
L
L
L
Open load or short to ground L
L
L
L
Overload or short to supply
Latched overload
Reset latch
Reset latch
Overtemperature
Latched overtemperature
Reset latch
Reset latch
Recirculation error (reg.chn.)
Latched error
Reset latch
Reset latch
Clock failure (clock loss)
Drift
Failure
No failure
(1)
(2)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
Enable
Input
ENA
L
L
H
H
L
L
H
H
H
H
H –> L
H
H
H
H –> L
H
H
H
H –> L
H
L
L
H
H
L
L
H
H
Control Input
non-reg./reg.
IN
L
H/PWM
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
X
H/PWM –> L
H/PWM
H/PWM
X
H/PWM –> L
PWM
PWM
X
PWM –> L
L
H/PWM
L
H/PWM
L
H/PWM
H/PWM
H/PWM
Powe r Outp u t/
Current reg.
Q
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
Status
Output
ST
L
L
L
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
X
X
L
H
(1) during power on sequence only detected on channel 3 and 4 (see description).
(2) This in put combina tion is also us ed for an internal chip- test and mus t not be used.
12/21
Page 13
2.0 Timing Diagrams
2.1 Non Re gu lated Chan nel s
Figure 5. Out put S lo pe, Re s is tive Load
V
I
V
IH
V
IL
t
ONtf
85% V
15% V
V
Q
V
S
S
S
t
OFFtr
L9347
t
99AT0061
Figure 6. Overload Switch-OFF Delay
I
Q
I
QO
I
QU
V
ST
t
t
t
D
t
SCP
t
sf
00RS0001
t
13/21
Page 14
L9347
Figure 7. Normal Condition, Resistive Load, Pulsed Input Signal
V
IN
V
Q
I
Q
t
D
V
ST
99A T0063
Figure 8. Current Overload
V
IN
V
Q
Set Fail
register
I
QU
t
D
t
D
Reset Fail
register
14/21
I
Q
V
ST
99A T0064
I
QO
t
D
Page 15
Figure 9. Diagnostic Status Output at Different OPEN Load Current Conditions
Under current condition followed by normal operation
t
D
V
IN
V
Q
L9347
I
Q
t
D
V
ST
99AT0065
Open load condition in the case of pulsed input signal followed by normal operation
V
IN
V
Q
I
QU
t
D
I
Q
V
ST
99AT0066
I
QU
t
D
15/21
Page 16
L9347
Figure 10. Pulsed Open Load Conditions (regulated and non-regulated channels)
V
IN
V
Q
I
Q
V
ST
99AT0067
t
lf
t
D
0.33 x V
S
t
lf
2.2 Regulated Channels (timing diagrams of diagnostic with 2kHz PWM input signal)
Figure 11. Normal Condi t io n, In ductive Load
500µs
t
DREG
16/21
V
IN
V
Q
I
Q
V
ST
99AT0068
Target Current
256µs
256µs
Page 17
Figure 12. Current Overload
L9347
500µs
V
IN
V
Q
I
QO
I
Q
V
ST
99AT0069
Figure 13. Recirculation Error
t
DREG
Reset Fail
register
Set fail
registor
t
sf
V
IN
V
Q
I
Q
V
ST
99AT0070
500µs
target current
t
DREG
Set Fail
register
Reset Fail
register
17/21
Page 18
L9347
Figure 14. Current Regulation Error (e.g. as a result of voltage reduction)
500µs
V
IN
V
Q
target current
I
Q
V
ST
99AT0071
Figure 15. Overtemperature
500µs
V
IN
Overtemperature
Condition
t
DREG
t
RE
PWM
= 90%
ratio
Reset Fail
register
18/21
V
Q
I
Q
V
ST
99AT0072
Set Fail
register
target current
Page 19
Figure 16.
Test mode 4 VEN low
V
TEST
V
IN3/4
V
Q3/4
99A T0073
L9347
19/21
Page 20
L9347
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A 3.60 0.141
a1 0.10 0.30 0.004 0.012
a2 3.30 0.130
a3 0 0.10 0 0.004
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D (1) 15.80 16.00 0.622 0.630
D1 9.40 9.80 0.370 0.385
E 13.90 14.50 0.547 0.570
e 0.65 0.0256
e3 11.05 0.435
E1 (1) 10.90 11.10 0.429 0.437
E2 2.90 0.114
E3 5.80 6.20 0.228 0.244
E4 2.90 3.20 0.114 0.126
G 0 0.10 0 0.004
H 15.50 15.90 0.610 0.626
h 1.10 0.043
L 0.80 1.10 0.031 0.043
N10°(max.)
S8°(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
OUTLINE AND
MECHANICAL DATA
PowerSO36
E2
h x 45˚
NN
a2
A
1936
0.12 AB
⊕
e
a3
B
E1
Gage Plane
M
PSO36MEC
DETAIL A
118
A
e3
H
D
b
DETAIL B
lead
BOTTOM VIEW
DETAIL B
0.35
S
DETAIL A
L
a1
E
slug
D1
SEATING PLANE
(COPLANARITY)
c
- C -
GC
E3
20/21
Page 21
L9347
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or o th erwise un der any pat ent or patent right s of STMi croelectr oni cs. Specifications menti oned in th i s publication are s ubj ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as c ritical components in li fe support devices or syst em s without express wri t ten approval of STMic roelectronics.
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21/21
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