Datasheet L9341 Datasheet (SGS Thomson Microelectronics)

L9341

QUAD LOW SIDE DRIVER

AVANCE DATA

DU/DTAND DI/DTCONTROL
PWM CONTROLLEDOUTPUT CURRENT
SHORT CURRENT PROTECTION AND DI-

AGNOSTIC
INTEGRATEDFLYBACKDIODE
UNDERVOLTAGESHUTDOWN
OVERVOLTAGE AND UNDERVOLTAGE DI-

AGNOSTIC
OVERTEMPERATUREDIAGNOSTIC

DESCRIPTION

The L9341 is a monolithic integrated circuit real­ized in Multipower BCD-II mixed technology. The
driver is intended for inductive loads in synchro­nous PWM applications, especially for valve driv-

BLOCK & APPLICATION DIAGRAM

VCC

10nF

Vcc

10uF

R

12.4k

4

I

cc

REXT

12

ext

Ω

RES1

9

RES2

10

CS

3

SCLK

11

SDI

5

SDO

13

OSC

6

C

OSC

BIAS

GND

UNDERVOLTAGE

SHUTDOWN

THERMAL
FLAG

SERIAL

INTERFACE

&

PWM

CONTROLL

8

I

GND

MULTIPOWERBCD TECHNOLOGY

Multiwatt 15

ORDERING NUMBERS: L9341V

L9341H

ers. The output voltage and current rise and fall
slopesdu/dt and di/dt are controlled.

V

s

I

CHANNEL 1

DIAGNOSTIC

DRIVER

COMP1

COMP2

di / dt & du / dt

CONTROL

SHORT

CURRENT

PROTECTION

CHANNEL 2

CHANNEL 3

CHANNEL 4

s

VS

7

V

flyth

V

offth

I

220nF

C

BATDBAT

OUT1

2

I

OUT1

10nF

C

outs

O1

OUT2

1

I

OUT2

C

O2

10nF

OUT3

15

I

OUT3

C

O3

10nF

OUT4

14

I

OUT4

C

O4

10nF

March 1994

1/10

This is advanced information on a new productnow in development or undergoing evaluation. Details aresubject to change withoutnotice.

L9341

PIN CONNECTION (Top view)

ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

V

CC

V

S

V

spmax

V

st

Vin InputVoltage Range for SDI; SCLK;CS;RES1;RES2 -0.3to V

V

out

I

out

VCCVoltageRange -0.3 to 6 V
VSVoltage Range -0.3 to 24 V
VS Voltage Range for t ≤ 400ms -2 to 40 V
Schaffner Transient Pulses on V

S

see note1 V

+0.3

CC

Output Voltage Range for all Outputs:
Negative
Positive

intern. clamped to V

– 0.3

S

Output Current for all Outputs:
Negative
Positive

–2
+2

for Transient witht < 10ms
Negative
Positive

–5

5

Schaffner Transient Pulses on Output see note2

V

ESD

ESD Voltage Capability (MIL 883 C) 1500 V

THERMAL DATA

Symbol Parameter Value Unit

R

th j-case

R

th j-amb

T

sdh

T

sd

Notes:

1. Schaffner transient specification: DIN 40839 testwaveforms of the following type: 1, 2, 3a, 3b, 5 and 6.

The pulses are applied to the application circuit according to fig. 3.

2. The maximum output current results from theSchaffner pulses specified in note 1.

Thermal Resistance Junction to Case 3 °C/W
Thermal Resistance Junction to Ambient mountedon PC Board 35 °C/W
Thermal Hysteresis 20 °C
Thermal Diagnostic Tj> 150 °C

V
V

A
A

A
A

2/10

L9341

ELECTRICAL CHARACTERISTICS (Unless otherwise specified: 8V ≤ VS≤ 24V; 4.7V ≤ VCC≤ 5.3V; –

40 °C ≤ Tj ≤ 150°C;I
R

=12.4KΩ ± 1%).

ext

≤ 1A(note 3); IO≤ 1.5A;Vsp=VSfor t ≤ 400ms; V

O

OUTP=VOUT

Symbol Parameter Test Condition Min. Typ. Max. Unit

I

ccq

I

sq

V

ccu

V

ccr

VccQuiescent Current All Outputs Off 1 3 mA
VsQuiescent Current All Outputs Off 14 25 mA
VccUndervoltage Threshold See Note 4 3 4 4.7 V
VccRange for RES1 and RES2

3V

Operation

R

on

I

o off

V

outf

I

gndf

I

outr

V

inH

On Resistance Io=1A Tj= 125°C

T

=25°C

j

Off State Output Current Outputs Off

1.4V ≤ V
V

outp=Vsp

≤ V

o

s

= 40V

1
1

Output Voltage During Flyback Io= 1A Output Off

T

=25°C

j

T

= 125°C

j

Current to GND during Flyback
(see note 5)

Io= 1A Output Off
V

= 24V

s

V

= 40V

sp

Reverse Leakage Current Vsp-Vo= 40V 500 µA
High Input Level of SCLK,

0.7*V

cc

SDI, CS, RES1, RES2

V

inL

Low Input Level of SCLK,

– 0.3 0.3*Vcc V

SDI, CS, RES1, RES2

V

REShys

Hysteresis of Reset Inputs

0.3 1 V

RES1, RES2

I

inRESH

I

V

SDOH

V

SDOL

I

SDOZ

PWM

K

V

V

in

f

flyth

offth

Input Current on RES1,RES2 RESi= H; -2V ≤ Vsp≤ 8V

RES

=H;8V≤Vsp≤ 40V

i

–10

5
Input Current on SCLK,SDI,CS – 2V ≤ Vsp ≤ 40V – 10 10 µA
High Level SDO Output Voltage I
Low Level SDO Output Voltage I
SDO TristateHigh-Z Leakage

Current
PWM Duty Cycle 1/16 15/16

duty

= -1mA -2V≤ Vsp≤ 40V 0.9*V

SDO

= 1mA -2V≤ Vsp≤ 40V 0 0.4 V

SDO

0 ≤ V

SDO

≤ V

cc

cc

–10 10 µA

–2V≤Vsp≤ 40V

Frequency Accuracy Constant See Note 6 0.93*KfnK
Flyback Diagnostic Comparator

Threshold
Off State Diagnostic

40 ≥ Vsp≥ 8V
V

≤ 8V

s

–1

V

s

1.5

1.5 2 V

Comparator Threshold

I

outl

t

dpo

S

ov

OutputCurrentLimitationThreshold see Note 7 1.5 2.5 A
Delay Time PWM Signal to Out. 5 15 µs
Output Voltage Rise andFall

(from 10 to 90% of Vo) Fig. 2 1.0 10 V/µs

Slope | du/dt |

S

oc

Notes:

3. The mean value is Io=

4. The outputs are switced off for Vcc ≤ Vccu. The logic is notreseted. Fora reset,RES1 or RES2 must be used.

5. This currentismeasured in the GND - terminal when one single output is in flybackand consistsof the supply current added to the value

ofthe output current source and the leakage currentof the flyback diode. This leakage current is less than 1% of the nominal flyback current.

6. The PWMfrequency isdefined by an external capacitor.The PWMoscillator frequency is: f
therange is: 300Hz ≤ f

7. For I

out

Output Current Rise and Fall
Slope |di/dt|

T

1

Io(t) dt

∫

0

T

≤ 3000Hz. The OSC Pin can be alternatively driven by an external TTL / CMOS signal.

≥ I

an internal comparator switches the corresponding output off for the currentPWM cycle.

outl

pwm

;

0.1 ≤ Io ≤ 1.5A
(from 10 to 90% of I

)

o

pwm

25 125 mA/µs

f

osc

withf

=

32

osc

for t ≤ 400ms;

750
450

2.5 4

V

s

V

s

17
20

Vcc+0.3 V

1.07*K

fn

Vs– 0.4 V

K

f

=

⋅1A/V and kin=15⋅10-6;

C

osc

10

+1.3
+1.1VV

44
52

10
10

V

cc

fn

mΩ
mΩ

mA
mA

mA
mA

µA
µA

V

V

3/10

L9341

Figure1: LogicDiagramof PWMGeneration.

INTERNAL
CLOCK

CLK

15

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PWM1

PWM2

PWM3

PWM4

Figure2: Output Switching Diagram.

+12V

220 nF

f

OUT

5

20 mH

I

10 nF

out

V

out

Internal PWM Signal

Output Voltage V

Current through
Low Side Switch

Current through
Flyback Diode

DMOS

GND

I

s

V

s

D
I

f

I

D

I

s

Figure3: Test Circuit for SchaffnerPulses.

+12V

220 nF

Vs

OUT1

out

I

D

I

f

D1

-2V to 40 V

12V

t

dpo

t

dpo

di/dt

5%

di/dt

5%

du/dtdu/dt

0
1A

di/dt

0
1A

di/dt

0

Schaffner
Generator

4/10

+5V

10 uF

VCC

GND

OUT2

OUT3

OUT4

4x1nF

4 x 10 nF

Figure4: SynchronousSerial Interface Protocol.

CS

SCLK

L9341

f

clock

t
t
t

t

chch

t

t

t

SDI

SDO

MSB 14 13 12 11 3 2 1 LSB

MSB 14 13 12 11 3 2 1 LSB

CS

t

t

clcl

chcl t

ch

t

cl

t

clch

SCLK

t

suth

SDI

SDO

t

t

clz

d

t

oh

15 14 0

015

Clock Frequency min. DC max. 2MHz
Width of Clock Input High Puls min. 200ns

t

ch

Widh of Clock Input Low Puls min. 200ns

t

cl

Clock Low Before CS Low min. 200ns

cicl

Clock High After CS Low min. 200ns

chcl

Clock Low Before CS High min. 200ns

clch

Clock High After CS High min. 200ns
SDO Low-Z CS Low min. 0ns max.400ns

ciz

SDO High-Z CS High max. 400ns

zch

SDI Input Setup Time min. 80ns

t

su

SDI Input Hold Time min. 80ns

t

h

SDO Output Delay Time (CL= 50pF) max. 100ns

t

d

SDO Output Hold Time min. 0ns

oh

t

chch

t

zch

5/10

L9341

Figure5: PWM GenerationFunction Table.

Bit 3 - 0 PWM1 PWM2 PWM3 PWM4 OUTPUT

0000 15/16 15/16 15/16 15/16 OFF
0001 1/16 15/16 1/16 15/16 ON
0010 2/16 14/16 2/16 14/16 ON
0011 3/16 13/16 3/16 13/16 ON
0100 4/16 12/16 4/16 12/16 ON
0101 5/16 11/16 5/16 11/16 ON
0110 6/16 10/16 6/16 10/16 ON
0111 7/16 9/16 7/16 9/16 ON
1000 8/16 8/16 8/16 8/16 ON
1001 9/16 7/16 9/16 7/16 ON
1010 10/16 6/16 10/16 6/16 ON
1011 11/16 5/16 11/16 5/16 ON
1100 12/16 4/16 12/16 4/16 ON
1101 13/16 3/16 13/16 3/16 ON
1110 14/16 2/16 14/16 2/16 ON
1111 15/16 1/16 15/16 1/16 ON

Figure6: PWM Information From Microcontrollerto QLSD.

Bit. Nr. Name Contents

0 P10 PWM Duty Cycle for Channel 1 / Bit 0: LSB
1 P11 PWM Duty Cycle for Channel 1 / Bit 1
2 P12 PWM Duty Cycle for Channel 1 / Bit 2
3 P13 PWM Duty Cycle for Channel 1 / Bit 3 : MSB
4 P20 PWM Duty Cycle for Channel 2 / Bit 0 : LSB
5 P21 PWM Duty Cycle for Channel 2 / Bit 1 :
6 P22 PWM Duty Cycle for Channel 2 / Bit 2 :
7 P23 PWM Duty Cycle for Channel 2 / Bit 3 : MSB
8 P30 PWM Duty Cycle for Channel 3 / Bit 0 : LSB

9 P31 PWM Duty Cycle for Channel 3 / Bit 1 :
10 P32 PWM Duty Cycle for Channel 3 / Bit 2 :
11 P33 PWM Duty Cycle for Channel 3 / Bit 3 : MSB
12 P40 PWM Duty Cycle for Channel 4 / Bit 0 : LSB
13 P41 PWM Duty Cycle for Channel 4 / Bit 1:
14 P42 PWM Duty Cycle for Channel 4 / Bit 2 :
15 P43 PWM Duty Cycle for Channel 4 / Bit 3 : MSB

6/10

Figure7: DiagnosticInformationfrom QLSD to Microcontroller.

Bit Nr. Name Contents

0 F11 COMP1 State at Positive Edge of PWM1 (0: V
1 F12 COMP2 State at Negative Edge of PWM1 (1: V
2 F21 COMP1 State at Positive Edge of PWM2 (0: V
3 F22 COMP2 State at Negative Edge of PWM2 (1: V
4 F31 COMP1 State at Positive Edge of PWM3 (0: V
5 F32 COMP2 State at Negative Edge of PWM3 (1: V
6 F41 COMP1 State at Positive Edge of PWM4 (0: V
7 F42 COMP2 State at Negative Edge of PWM4 (1: V
8 RES1 Logic State of RES1 Input (0: RES1 = L ; 1: RES1 = H)

9 RES2 Logic State of RES2 Input (0: RES2 = L ; 1: RES2 = H)
10 TSDF Thermal Diagnostic Flag ( 0: Overtemperature; 1:Normal )
11 C1 Current at Negative Edge of PWM1 ( 0: I
12 C2 Current at Negative Edge of PWM2 ( 0: I
13 C3 Current at Negative Edge of PWM3 ( 0: I
14 C4 Current at Negative Edge of PWM4 ( 0: I
15 1 Framing Information (always 1)

out1>Vflyth

out2>Vflyth

out3>Vflyth

out4>Vflyth

out>Ioutl
out>Ioutl
out>Ioutl
out>Ioutl

out1>Voffth

out2>Vofth

out3>Voffth

out4 > Voffth

;1:I

out<Ioutl

;1:I

out<Ioutl

;1:I

out<Ioutl

;1:I

out<Ioutl

;1:V

;0:V

;1:V

;0:V

;1:V

;0:V
;1:V
;0:V

out1<Vflyth

out1<Vofth

out2<Vflyth

out2<Vofth

out3<Vflyth

out3<Vofth

out4<Vflyth

out4<Vofth

)
)
)
)

L9341

)

)

)

)

)

)

)

)

Figure8.

PWM

I

D

V

OUT

PWM

t

C

t

dPO

t

V

t

PWMON

min

Sample point COMP2

Sample point COMP1

Fig.1 Fig.2

Fig. A Fig. B

V

OUT

t

t

dPO

PWMOFF

min

Sample point COMP2

t

V

Sample point COMP1

Note:

For safty diagnostic take notice of the following conditions:

t

PWMON

t

PWMOFF

≥ t

dPOMAX+tC+tV

≥ t

dPOMAX+tV

(see Fig. A) tC=

(see Fig. B)

S

I

D

OCMIN

tV=

V

outfmax

S

OVMIN

7/10

L9341

FUNCTIONAL DESCRIPTION

The U511 is a PWM quad low side driver for in­ductive loads. The duty cycle of the internal gen­erated PWM signal is set by a microcontrollervia
a serial interface for each output. An output slope
limitation for both dv/dt and di /dt is implemented
to reduce RFI. The PWM generation is realized
avoiding a simultaneous output switching. As a
result, di/dt becomes smaller. Integrated flyback
diodes clamp the output voltage during the fly­back phase of thelow side switches.

The driver is protected against short circuit. An
undervoltageshutdown circuit switchesoff all out­puts if V

is less then V

cc

. Below the shutdown

ccu

voltage all outputs remain in off state regardless
of the input state. After each malfunction which
resets the driver,only the serial link interface can
reactivatethe normal function.In case of overcur­rent (I

out=Iout1

), an internal comparator switches
the output off. The overcurrent informationcan be
read via the serial link for each driver separately
at the negative edge of the corresponding PWM
signal.

The interface to the microcontroller is realized
with a 16 bit synchronous serial peripheral inter­face (SPI). If CS is switched low, the serial link
becomesactive and SDO goes to lowimpedance.
At the rising edge of the SCLK signal, one of the
16 bit of data stored in a shift register appear se­quencely at SDO. These data contain the 8 error
flags, the statusof thermaldiagnostic flag and the
external reset sourcesRES1, RES2 and the over­current flgs c1...c4. The last bit is framing infor­mation (see fig. 7). At each falling edge of SCLK,
one of the 16 bits of data sent by the microcon­trolleris transferredvia the SDI input to the driver.
These data contain the duty-cycle information for
the internal PWM generation (4 times 4 bit).

On the rising edge of CS the previouslystored in­formation is transferred to the circuits. SDO be­come now high impedance and SDI is inactive.
The serial interface of the QLSD is cascadable
with the serial link interface of another QLSD,
thus obtaininga 32 bit serial link information wich
can control eight inductive loads. For a safety
data transfer the takeoverof data bits is only real­ized when the number of SCLK - clocks is n x 16
(n ≥ 1).

The PWM duty cycle is set by 4 bit for each out­put independentlyvia the serial link. If all four bits
for an output are zero, theoutput is turned off, but
the error diagnosis will work correctly (see fig. 5
and 6). The PWM frequencyis defined by an ex­ternal capacitor on the OSC pin. Rext defines
through the reference current the output current
slope, the diagnostic current sink and the internal
oscillatorfrequency(togetherwith C

osc

).

For error diagnosis the voltage on the output is
measured during the on and off state of the par­ticular output driver. Upon the rising edge of the
PWM signal (at this moment the power output is
off and will be switched on) the status of COMP1
is stored into an internal latch. On the fallingedge
of the PWM signal ( the power output is on and
will be switched off) the status of COMP2 is
stored into another internal latch. This information
can be read via the serial link for each output
driverseparately(see fig. 7).

The thermal diagnostic switch the thermal flag to
0 in case of overtemperature T ≥ T
switched to 1 with the hysteresis T
T<T

sd-Tsdh

.

.Itwillbe

sd

in case of

sdth

To avoid male functions due to extensivenoise or
spikes at the supply pins V

CC,VS

and R

ext

must

be blocked externally via capacitors.

8/10

MULTIWATT15 PACKAGE MECHANICAL DATA

L9341

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 5 0.197

B 2.65 0.104
C 1.6 0.063
D 1 0.039

E 0.49 0.55 0.019 0.022

F 0.66 0.75 0.026 0.030
G 1.02 1.27 1.52 0.040 0.050 0.060

G1 17.53 17.78 18.03 0.690 0.700 0.710
H1 19.6 0.772
H2 20.2 0.795

L 21.9 22.2 22.5 0.862 0.874 0.886

L1 21.7 22.1 22.5 0.854 0.870 0.886
L2 17.65 18.1 0.695 0.713
L3 17.25 17.5 17.75 0.679 0.689 0.699
L4 10.3 10.7 10.9 0.406 0.421 0.429
L7 2.65 2.9 0.104 0.114

M 4.25 4.55 4.85 0.167 0.179 0.191

M1 4.63 5.08 5.53 0.182 0.200 0.218

S 1.9 2.6 0.075 0.102

S1 1.9 2.6 0.075 0.102

Dia1 3.65 3.85 0.144 0.152

mm inch

9/10

L9341

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement ofpatents or other rights ofthird parties whichmay result from itsuse. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men­tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex­press writtenapproval of SGS-THOMSON Microelectronics.

 1994 SGS-THOMSON Microelectronics - All RightsReserved

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10/10