Datasheet L9230 Datasheet (SGS Thomson Microelectronics)

■ OPERATING SU PPLY VOLTAGE 5V TO 28V

■ TYPICAL R

= 150 mΩ FOR EACH

DSon

OUTPUT TRANSISTOR (AT 25°C)

■ CONTINOUS DC LOAD CURRENT 5A

(T

< 100 °C)

case

■

OUTPUT CURRENT LIMITATION AT TYP. 6A

■ SHORT CIRCUIT SHUT DOWN FOR OUTPUT

CURRENTS OVER 8A

■ LOGIC- INPUTS TTL/CMOS-COMPATIBLE

■ OPERATING-FREQUENCY UP TO 30 kHz

■ OVER TEMPERATURE PROTECTION

■ SHORT CIRCUIT PROTECTION

■ UNDERVOLTAGE DISABLE FUNCTION

■ DIAGNOSTIC BY SPI OR STATUS-FLAG

(CONFIGURABLE)

■ ENABLE AND DISABLE INPUT

■ SO20 POWER PACKAGE

DESCRIPTION

The L9230 is an SPI controlled H-Bridge, designed
for the control of DC and stepper motors in safety crit­ical applications and under extreme environmental
conditions.

L9230

SPI CONTROLLED H-BRIDGE

PRELIMINARY DATA

PowerSO20 BARE-DIE

ORDERING NUMBERS:

L9230 L9230-DIE1

The H-Bridge is protected against over temperature
and short circuits and has an under voltage lockout
for all the supply voltages ”V
ply). All malfunc tions cause the output stages to go
tristate.

The H-Bridge contains integrated free-wheel diodes.
In case of free-wheeling conditi on, the lowside t ran­sistor is switched on in parallel of its diode to reduce
the current injected into the substrate.

Switching in parallel is only all owed, if the voltage­level of the according output-stage is below the
ground-level.In this case it must be ensured, that the
upper transistor is switched off.

” (Main DC power sup-

S

BLOCK DIAGRAM

V

S

1

2

OVER

INTERNAL 5V

SUPPLY

OVERCURRENT

HIGH-SIDE

OVERCURRENT

LOW-SIDE

GND

OUT1

OUT2

D01AT470A

UNDERVOLTAGE

V

S

IN1
IN2

DI

EN

LOGIC

DMS

SF/SCK

SS

SI

SO

GATE CONTROL

GATE CONTROL

TEMPERATURE

MAXIMUM
CURRENT

LIMITATION

March 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1/25

L9230

PIN FUNCTION

N° Pin Description

1 GND Ground
2 SCK/SF SPI-Clock/Status-flag
3 IN1 Input 1
4V
5 V
6 OU1 Output 1
7 OU1 Output 1
8 SO serial out
9 SI serial in

10 GND Ground

11 GND Ground
12 DMS Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface)
13 EN Enable
14 OU2 Output 2
15 OU2 Output 2
16 V
17 SS Slave select
18 DI Disable
19 IN2 Input 2
20 GND Ground

Supply voltage

S

Supply voltage

S

Supply voltage

S

PIN CONNECTION

(Top view)

GND

SCK

IN1

V

V
OU1
OU1

SO

GND 10

SI

1
2
3

S
S

4
5
6
7
8
9

D01AT471

20
19
18
17
16
15
14
13
12
11

GND
IN2
DI
SS
V

S

OU2
OU2
EN
DMS
GND

2/25

L9230

ABSOLUTE MAXIMUM RATINGS

The integrated circuit must not be destroyed by use at the limit values.
Each limit value can be used, as long as no other limit is violated.
Voltage reference point: All values are, if not otherwise stated, relative to ground.
Direction of current flow: Current flow into a pin is positive.
Rise-, fall- and delaytimes: If not otherwise stated, all rise times are between 10% and 90%, fall times

between 90% and 10% and delay times at 50% of the relevant steps.

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

V

V

THERMAL DATA

Symbol Parameter Test Condition Min. Typ. Max. Unit

T

T

R

th j-case

T

Supply voltage static destruction proof -1 40 V

S

dynamic destruction proof t <0.5s

-2 40 V

(single pulse, Tj < 85°C)

LI

Logic inputs

-0.5 7 V

IN1, IN2, DI, EN, SS, SI, SCK,DMS

I

Logic inputs

LI

IN1, IN2, DI, EN, SS, SI, SCK,DMS
Logic outputs SF, SO R ≥ 10kΩ -0.5 7 V

LO

Junction temperature

T

j

-40 +150

dynamic t < 1 s

Storage temperature -55 +125 °C

stg

Ambient temperature -40 +125 °C

amb

Thermal resistance junction to

(2)

case
Thermal Shutdown Junction

j_sd

165 175 °C

Temperature Threshold

-20 mA

+175

3 °C/W

°C
°C

ELECTRICAL CHARACTERISTCS

( Tj = -40 to +150°C; VS = 5 to 28V)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Power Supply

V

Supply Voltage Static Condition 5 28 V

S

Dynamic Condition (t < 500ms) 40 V

Undervoltage Shutdow n

(at least down to 2.5V)

(1)

4.7 5 V

Switch OFF voltage 4.5 5 V
Switch ON voltage 4.7 5 V
Hysteresis 200 mV

I

Supply current f = 0 kHz, IO = 0 A

S

f = 20kHz, IO = 0 A

Note: 1. For supply volt ag es d own to 2.5 V t he ou tp ut s tage s ar e in trist ate cond itio n and t he st atus flag is set to lo w. B e low 2 .5V the

device op erates in unde fined condition

2. Guaranteed by d esign and package characterization

13
30

mA
mA

3/25

L9230

ELECTRICAL CHARACTERISTCS

( Tj = -40 to +150°C; VS = 5 to 28V)

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Logic inputs

V

Logic Input Voltage

I

1 1.5 2 V

IN1, IN2, DI, EN
Logic Input Current

I

I

VI ≤ 1V -200 -125 µA

IN1, IN2, DI

I

Input Current EN V

EN

Detection Time EN, DI 3 4 µs

t

dt

≥ 2V 75 100 µA

IEN

Power Outputs (OUT1, OUT2)

R

Switch on Resistance LS R

S

Switch on Resistance HS R

, VS > 5 V 150 250 mΩ

OUT-Vs

OUT-GND, VS

> 5 V 150 250 mΩ

Current Limitation Peak value controlled

inductive load L = 0,8 to 5 mH
resistive load R = 0,8 to 1.8 Ω

|I

OU|max

|IOU|

t

a/tb

Switch-off Current -40 °C < Tj < 165 °C

max

t

a

t

b

Switch-off time
Blanking time
Tracking

(2)

(2)

(2)

Tj < 175 °C

5.5 6

7.7 A

2.5

12 17 22 µs

811.515µs

1.4 1.5 1.6

A

|

|I

OUK

∆|I

Short circuit detection curren t

|

OUK

Short Circuit Current Trecking

t Reactivation time after internal

(2)

(2)

(3 )

I

L

V

FD

t

rr

V

SFHigh

|I

ou| max

I

SF

I

SF

shut down

Leakage Current Output stage switched off 1 mA
Free-wheel diode forward voltage IO = 3A, VS = 0V 2 V
Free-wheel diode reverse

recovery time
Output„high“ (SF not set)

Switch OFF Current Tj = -40 to 165°C 6 A

Output„high“ (SF not set)
Output„low“ (SF set)

(*)

(2)

(1)

see figure 1 5.5 11 A

(1)

1600 mA

Overcurrent- or overtemperature
shut down to reactivation of the
output stage

VS = 5V, R

= 27KΩ 4.1 V

Pull_up

Tj = < 175°C 2.5 A
V

= 5V 20 µA

SF

V

= 1V 300 µA

SF

V

= 0.5V 100 µA

SF

V

= 0.8V 500 µA

SF

1ms

100 ns

4/25

L9230

ELECTRICAL CHARACTERISTCS

( Tj = -40 to +150°C; VS = 5 to 28V)

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Timing

f PWM Frequency min. operating time 10µs 2 30 kHz

f

Switching Frequency during

S

5 30 kHz

current limitation

t

don

t

doff

t

Output ON-delay

IN1 --> OUT1 or IN2 --> OUT2

35µs

Output OFF-delay 3 5 µs

, t

Output rise-, fall Time

r

f

OUT1H--> OUT1L, OUT2H--> OUT2L,

0.2 0.4 1 µs
IOUT = 3 A
OUT1L--> OUT1H, OUT2L--> OUT2H

t

ddis

t

Disable Delay Time DIn --> OUTn, En --> OUTn 3 4 µs
Power on Delay Time VS = on --> output stage active 15 ms

dp

Delay time for fault detection 5 15 µs

|∆I| Effect of reverse current at power

supply

(*) For low er pull up resis tances than 27kΩ the specified value of xxxV (minimum) is guaranteed by design
Note: 1. In case of SC OUTx to Vs the switch off current is always higher than the start value of current regulation (∆|I

2. Guaranteed by design

3. Value is tested down to 6V. For supply voltage below 6V on i ncreased current can be fed bac k in the device via a pro tection path

4,5V < V

- IVs < 3A

∆

I for ISI, ISO, ISS, I

DMS

< 5,5V

SCK

, I

, I

, IEN,I

IN1

IN2

DI

100 µA

| = |I

OUK

OUK

| - |I

OUmax

|

5/25

L9230

Figure 1. Out put del a y t ime

IN

n

OUT

n

Figure 2. Dis abl e del a y tim e

DI

n

OUT

n

50%

t

don

50%

t

ddis

10%

90%

Z

D01AT473

50%

t

doff

10%

D01AT472

Figure 3. Out put sw i tchi ng time

OUT

n

6/25

90% 90%

10%

t

f

t

r

D01AT474

Figure 4.

L9230

LOAD

CURRENT

>8A

typ 6.6A

CONTROL

SIGNAL

STATUS

FLAG

DETAIL A

6.6A

CURRENT LIMITATION

A

t

a

OVERCURRENT

DETECTION

t

b

OVERCURRENT

ta = SWITCH_OFF TIME IN CURRENT LIMITATION
tb = CURRENT LIMITATION BLANKING TIME

D01AT475

Figure 5.

Temperature-depending current-limitation

Maximum rating for junction temperature for < 1s 175°C
Overtemperature switch-off > 175°C
Switch-off current in case of current limitation 6,6A ± 1,1A Tj < 165°C
For 165°C < Tj < 175°C the maximum current decreases from Imax. = 6,6A ± 1,1A to Imax. = 2,5A ± 1,1A.

Tolerance-range

Imax

6.6A

2.5A

of temperat u re -depen de nt
current - reduc tion

165°C

175°C

Range of
Overtemperatur e
switch-off

Tj

7/25

L9230

ELECTRICAL CHARACTERISTICS

(continued)

SPI INTERFACE

The timing of L9230 is defined as follows:

- The change at output (SO) is forced by the rising edge of the SCK signal.

- The input signal (SI) is taken over on the falling edge of the SCK signal.
= active without any clocks at SCK is not allowed

- SS

- The data received during a writing access is taken over into the internal registers on the rising edge of the SS

signal, if exactly 16 SPI clocks have been counted duri ng SS

= active.

Figure 6.

910

SS

SCK

2

11

1

4

3

8

12

7

SO

SI

5

MSB IN

tristate

6

Bit (n-3)

Bit (n-3)Bit (n-2)

Bit (n-4)...1

Bit (n-4)...1

Bit 0; LSB

LSB IN

n = 16

ELECTRICAL CHARACTERISTCS

( continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Input SCK

V

SCKL

V

SCKH

∆V

C

SCK

(SPI clock input 4.5V < DMS < 5.5V)

Low Level 1 V
High Level 2 V

Hysteresis 0.1 0.4 V

SCK

Input Capacity 10 pF

8/25

L9230

ELECTRICAL CHARACTERISTICS

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

-I

SCK

Input Current Pull up current source connected

to V

S

20 50 µA

Input SS (Slave select signal)

V

V

∆V

C

SSL

SSH

-I

Low Level L9230 is selected 1 V
High Level 2 V
Hysteresis 0.1 0.4 V

SS

Input Capacity 10 pF

SS

Input Current Pull up current source connected

SS

20 50 µA

to VDD

Input SI (SPI data input)

V
V

∆V

C

Low Level 1 V

SIL

High Level 2 V

SIH

Hysteresis 0.1 0.4 V

SI

Input Capacity 10 pF

SI

-I

Input Current Pull up current source connected

SI

20 50 µA

to VDD

Output SO (Tristate output of the L9230 (SPI output); On active reset (DI) output SO is in tristate.)

V
V

SOL

SOH

Low Level ISO = 2mA 0.4 V
High Level ISO = -2mA V

VDD

- 0.75

C

I

SO

Capacity Capacity of the pin in tristate 10 pF

SO

Leakage Current In tristate -10 10 µA

Input DMS (Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode)

Input Voltage SPI-Mode

V

i

3.5

Status-Flag-Mode

Input Current SPI-Mo de 10 mA

I

c

Timing

t

cyc

Cycle-Time

200 ns

(referred to master)

t

lead

Enable Lead Time

100 ns

(referred to master)

t

Enable Lag Time

lag

150 ns

(referred to master)

0.8

V

V
V

9/25

L9230

Symbol Parameter Test Condition Min. Typ. Max. Unit

t

Data Valid CL = 40pF

v

Data Valid CL = 200pF
(referred to L9230)

40

150

ns
ns

t

Data Setup Time

su

(referred to master)

t

Data Hold Time

h

(referred to master)

t

dis

Disable Time
(referred to L9230)

dt

Transfer Delay

t

(referred to master)

t

SCKH

Serial clock high time
(referred to master)

t

SCKL

Access time
(referred to master)

Clock inactive before
chipselect becomes valid

Clock inactive after
chipselect becomes valid

t

rise-, fall time Load on SO 50pF 20 ns

rs

DIAGNOSTIC

Diagnostic Threshold

V

OUT1

V

OUT2

(Open Load Detection DMS > 4,5V, EN < 0,8V)

Load is available 0.8

50 ns

20 ns

100 ns

150 ns

50 µs

8.35 ns

200 ns

200 ns

0.8

V
V

V
V

I

OUT2

-I

10/25

OUT1
OUT2

OUT1

t

D

Load is missing 1 V

Diagnostic Current DMS > 4.5V, EN < 0.8V

DMS > 4.5V, EN < 0.8V

Tracking Diagnostic Current I

OUT1

/ I

OUT2

700

1000

1000
1500

1300
2000

1.4 1.5 1.6

S

0.8

V
V

µA
µA

Delay Time 30 100 ms

TRUTH TABLE

Pos. DI EN IN1 IN2 OUT1 OUT 2

1. forward L H H L H L H

2. reverse L H L H L H H

3. Free-wheeling low L H L L L L H

4. Free-wheeling high L H H H H H H

5. Disable HXXXZZ L

6. Enable X L X X Z Z L

SF

3)

L9230

4)

SPI

DIA_REG

7. IN1 disconnected L H Z X H X H

8. IN2 disconnected L H X Z X H H

9. DI disconnected ZXXXZZ L

10. EN disconnected X Z X X Z Z L

11. Current limit. active L H X X Z Z H

12. Undervoltage

13. Overtemperature

14. Overcurrent

1.)

2.)

2.)

XXXXZZ L
XXXXZZ L
XXXXZZ L

See

Page

17

1.) In case of undervoltage tristate and status-flag are reset automatically.

2.) Whenever overcurrent or overtemperature is detected, the fault is stored (i.e. status-flag remains low).

3)

The tristate conditions and the status-flag

are reset via DI or EN.

L = Low
H = High
X = High or Low
Z = High impedance
(all output stage transistors are switched off in static state. For more inform. see next page )

Overcurrent: I
Overtemperature: T

Undervoltage: V

OUT1,2

j

Vs-GND

>8,0 A
>175°C

<5.0 V (at least down to 2 ,5 V)

3.) If Mode „Status-Flag“ is selected (see 1.5)

4.) If Mode „SPI-Diagnosis is selected (see 1.5)

11/25

L9230

Description of the state „Z“

The state „Z“ has, depending on the previous operating condition different meaning.

1. dynamical
I. e. the inductive load is current carrying and is switched off according to Pos. 5, 6, 9, 10, 11, 12, 13, or

14 of the truth table

a.) All output stage transistors are switched off.
b.) The current flow is continued via the free wheeling diodes.
c.) Free wheeling is detected by a negative voltage-level at OUn.
d.) Switch on of the parallel-transistor of the current carrying diode.
f.) Free wheeling is finshed, if the voltage-level on OUn is positive again.

2. statical
g.) all output-stages switched off.

Figure 7.

I

V

I

VS

-I

GND

LOAD

V

OUn

-VD

S

VS-

-V

S

S

CURRENT

CARRYNG

FREE WHEELING HIGH IMPEDANCE

Zº

Z

D01AT478

12/25

L9230

DIAGNOSTIC

The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag Diagnosis.
The choise of the Diagnosis-Mode is selected by the voltage-level on pin 12 (D M S D
DMS = G ND Status-Flag
DMS = Vcc SPI-Diagnostic
For the connection of pins SI, SO, SS and SCK/SF see Fig. 10 respectively Fig. 11.

Status-Flag

The Status-Flag showes the condition „tristate“.
At the following fault-cases the output-stages switches in tristate and set the status-flag from high to low.

- Short circuit of OUT1 or OUT2 against V

or GND

S

- Short circuit between OUT1 and OUT2

- Overcurrent

- Overtemperature

- Undervoltage on V

S

In cause of short circuit or overcurrent, the fault will be stored.
The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value
is exceeded.
If the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again
and the status-flag is reset to high-level.

In cause of overtemperature the fault will be stored.
The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value
is exceeded.
the voltage level changes from high to low on D I or from low to high on EN, the output stage switches on again
and the status-flag is reset to high-level.

In cause of undervoltage on V

the output stage switches in tristate and the status-flag is set from high level

Batt

to low-level if the specified value is fall en. If the voltage has ris en about the specified value again, the output
stage switches on again and the status-flag is reset to high-level.

The maximum current which can flow under normal operating conditions is limited to typical I
When the maximum current value is reached, the output stages are switched tristate for a fixed time.
According to the time-constant the current decreases exponentially until the next switch-on occurs.
At the end if the fixed time the output stage switches on again and the status-flag is reset to high-level.

iagnosis Mode Selection).

= 6,6A .

max.

13/25

L9230

SPI-INTERFACE

General Discription

The serial SPI interfac e establishes a c ommunication link between L9230 and the systems microcontroller.
L9230 always operates in slave mode whereas the controller provides the master function.

The maximum baud rate is 2 MBaud (200pF).
Applying an active slave select signal at SS

SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master.
In case of inactive slave select signal (High) the data output SO goes into tristate.

Figure 8.

L9230 is selected by the SPI master. SI is the data input (Slave In),

DMS

SS

SI

Shift Register

SPI Power Supply

SPI Control:

State Machine
Clock Counter
Control Bits
Parity Generator

DIA_REG

Depending on the application the first two bits of an instruction may be used to estabish an extended
device-addressing. This gives the opportunity to operate up to 4 Slave-devices s haring on e common SS
from the Master-Unit

signal

Power Supply of the SPI-Interface

SPI-Logic and I/O-Pins are alternativ supplied from DMS or Vcc internal, depending on which voltage is higher.
That is why diagnosis of the EN-/DI-Pins is always possible, even in case of missing H-Bridge-power supply e.g.

during „Vorlauf/Nauchlauf“.

14/25

L9230

Characteristics of the SPI Interface

1) When DMS is > 3,5V, the SPI is active, independent of the state of EN or DI and the voltage on VS.

During active reset conditions (DMS < 3,5V) the SPI is driven into its default state.
When reset becomes inactive, the state machine enters into a waitstate for the next instruction.

2) If the slave select signal at SS

is inactive (high), the state machine is forced to enter the

waitstate, i.e. the state machine waits for the following instruction.

3) During active (low) state of the select signal SS

the fallin g edge of the serial clock signal
SCK will be used to latch the input data at SI. Output data at SO are driven with the rising
edge of SCK. Further processing of the data according to the instruction ( i.e. modification
of internal registers) will be triggered by the rising edge of the SS

signal. (-> See Note)

3 ) Chipaddress:
In order to establish the option of extended addressing the uppermost two bits of the

instruction-byte ( i.e the first two SI-bits of a Frame ) are reserved to send a chipaddress.

To avoid a busconflict the output SO must stay high impedant during the addressing

phase of a frame (i.e. until the addressbits are recognised as valid chipaddress).
This tristate behavior should be realised in any case, regardless wether the extended

address option is used or not.

If the chipaddress does not match, the according access will be ignored and SO remains high

impedant for the complete frame regardless which frametype is applied.

5) Check byte:
Simultaneously to the receipt of an SPI instruction L9230 transmitts a check byte via the
output SO to the controller. This byte indicates regular or irregular operation of the SPI.

It contains an initial bitpattern and a flag indicating an invalid instruction of the previous access.

6) On the read access the databits at the SPI input SI are rejected.

7) Invalid instruction/access:
An instruction is invalid, if one of the following conditions is fulfilled:

- an unused instruction code is detected (see tables with SPI instructions).

- in case the previous transmission is not completed in terms of internal data processing.
( Violation of the minimum Access-Time. )
If an invalid instruction is detected, any modifications on registers of L9230 are not allowed.
In case an unused instruction code occured the databyte “ff

” will be transmitted after

hex

having sent the check byte.

In addition any access is invalid if the number of SPI clock pulses (falling edge) counted
during active SS

differs from exactly 16 clock pulses (-> See Note).

15/25

L9230

SPI Communication
Figure 9. Reading access / 8 bit

SS

SI

SO

SPI INSTRUCTION

MSB

VERIFICATION BYTE

MSB

XXXX XXXX

DATA/8 BIT

MSB

D01AT480

SPI Instruction

The uppermost 2 bit of the instruction byte contains the chipadress. The individual chipadress is a mask-option
and must be defined in accordance to the SPI-Members sharing on SS line.

SPI Instruction-Format

MSB

76543210
0 0 INSTR4 INSTR3 INSTR2 INSTR1 INSR0 INSW

Bit Name Description

7,6 CPAD1,0 Chip Adress (has to be ‘0’, ‘0’)

5-1

INSTR (4-0) SPI instruction (encoding)

0 INSW Don‘t care

SPI Instruction-Bytes

Encoding

SPI Instruction

RD_IDENT 00 00000 0 read identifier
RD_VERSION 00 00001 1 read version

RD_DIA 00 00100 1 read DIA_REG

16/25

bit 7,6

CPAD1,0

bit 5,4,3,2,1

Bit 0

INSTR(4...0)

all others no function

Description

Reset of the Diagnostic Register DIA_REG

On the following conditions DIA_REG is reset:

- DI high

- EN low

- With the rising edge of the SS-signal after the SPI-Instruction RD_DIA.

- When the voltage on DMS exceeds the threshold for detecting SPI-Mode.

(after undervoltage condition)

- Undervoltage on V

(< 5,0V) sets Bit 0 .... Bit 3 of DIA_REG to 0000.

S

- If UB rises over about the undervoltage level, the Bits of DIA_REG are restored

(when V

internal or DMS > 3,5V)

S

L9230

Verification byte:

MSB

76543210
ZZ10101TRANS_F

Bit Name Description

0 TRANS_F Bit = 1: error detected during previous transfer

1 Fixed to High
2 Fixed to Low
3 Fixed to High
4 Fixed to Low
5 Fixed to High
6 send as high impedance
7 send as high impedance

Bit = 0: previous transfer was recognised as valid

17/25

L9230

Diagnostics/Encoding of Failures

Description of the SPI Registers (SPI Instructions: RD_DIA)

Register: DIA_REG

76543210

DI OT CurrRed CurrLim DIA21 DIA20 Dia11 DIA10

State of Reset: FFH

Access by Controller: Read only

Bit Name Description

0 DIA 10 Diagnosis-Bit1 of OUT1
1 DIA 11 Diagnosis-Bit2 of OUT1
2 DIA 20 Diagnosis-Bit1 of OUT2
3 DIA 21 Diagnosis-Bit2 of OUT2
4 CurrLim is set to „0“ in case of current limitation
5 CurrRed is set to „0“ in case of temperature dependet current limitation
6 OT is set to „0“ in case of overtemperature
7 DI shows the wired-or state of the Pins EN and DI

Encoding of the Diagnostic Bits of the Output-Stages OUT1 and OUT2

DIA21 DIA20 DIA11 DIA10

- - 0 0 Short circuit over load (SCOL)

- - 0 1 Short circuit to battery on OUT1 (SCB1)

- - 1 0 Short circuit to ground on OUT1 (SCG1)

- - 1 1 No error detected on OUT1
0 0 - - Open load (OL)
0 1 - - Short circuit to battery on OUT2 (SCB2)
1 0 - - Short circuit to ground on OUT2 (SCG2)
1 1 - - No error detected on OUT2

0 0 0 0 Undervoltage on Pin UB

Description of DIA_REG Bit7

EN DI DIA_REG Bit7

00 0
01 0
10 1
11 0

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L9230

Device Identifier

The IC‘s identifier is used for production test purposes and features plug & play functionality depending on the
systems software release. It is made up on a device-number and a revision number each one read-only acces­sible via standardised instructions.
The Device number is defines once to allow indentification of different IC-Types by software.

The R ev is ion nu mb er ma y be u tilis e d to dis tinguish differen t s ta tes of h ar dw are . Th e c o nte nt s is div ided into an
upper 4 bit field reserved to define revisions correspondending to specific software releases.

The lower 4 bit field is utilised to indentify the actual maskset.
Both (SWR and MSR) will start with 0000

hardware is introduced.

Reading the IC Identifier (SPI Instruction: RD_IDENT):

IC Identifier1 (Device ID)

76543210

ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

Bit Name Description

7...0 ID(7...0) ID-No.: 10100001 L9230

and are increased by 1 every time an according modification of the

b

Reading the IC revision number (SPI Instruction: RD_VERSION):

IC’s revision number

76543210

SWR3 SWR2 SWR1 SWR0 MSR3 MSR2 MSR1 MSR0

Bit Name Description

7...4 SWR(3...0) Revision corresponding to Software release: 0Hex

3...0

MSR(3...0) Revision corresponding to Maskset: 0Hex

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L9230

Figure 10. Application example with SPI-Interface

V

V

BATT

VOLTAGE

REGULATOR

POWER-ON

RESET

CC

RESET

I.E. WATCH

DOG µP

µC

Figure 11. Application example with Status-Flag

IN1

IN2

SCK

SS

SO

EN

DMS

DI

SI

UB

GND

OUT1

M

OUT2

D01AT481

20/25

V

BATT

VOLTAGE

REGULATOR

POWER-ON

RESET

V

CC

RESET

47K

µC

I.E. WATCH

DOG µP

SF

IN1

IN2

SS
SO

EN

DMS

DI

SI

UB

GND

OUT1

M

OUT2

D01AT482

Figure 12. Application examples for Overvoltage - and Reverse -Vo ltage Protecti on

Version 1 REVERSE POLARITY PROTECTION VIA MAIN RELAIS

L9230

H-BRIDGE

Version 2 REVERSE POLARITY PROTECTION VIA ACTIVE DIODE

H-BRIDGE

D01AT483

V

S

V

S

V

S

< 40V

VS < 40V

MAIN

RELAIS

IGNITION

SWITCH

BATTERY

BATTERY

ESD-SOLIDITY

The connection pins of the IC have to be protected against Electrostatic Discharge ESD) by suitable integrated
protection structures.

The integrated circuit has to meet the demand of the „Human-Body-Model“ with V
C = 100pF and R2 = 1,5k

Ω

(330Ω for OUT1 and OUT2).

= ± 4kV

C

Thereby any defect or destruction of the integrated circuit must not occur.
The protection structures realized to reach the ESD-strength have to be coordinated.
The ESD-strength has to be verified by the test circuit given as below.

Figure 13.

S2

R1 R2

=

S

DC-

V

VOLTMETER

(1)

(2)

S1

C OUTU

For the Pins 4, 5, 6, 7, 14 and 15

= + 4kV

U

C

R

= 100k

1

R2 = 330

Ω

Ω

C = 100pF
Number of pulses each pin: 18
Frequency: 1Hz
Arrangement and performance:
The requirements of MIL883D Methode 3015 have to be fulfilled.

S3

D01AT484

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L9230

ISO-PULSES

In the main-power-supply-system di sturbance transients according to ISO 7637-1 First Edition 1990-06-01
may occur.

By means of external componen ts (see Fig. 12) the following maximum ratings of the IC will not be exceeded.

statical -1V ...... +40V

dynamical for t < 500 ms -2V ...... +40V

APPENDIX A

OUT1 OUT2

Load available 1 1
Open Load
SC -> GND on OUT1 with Load 0 0 SC detected on normal operation
SC -> GND on OUT2 with Load 0 0 SC detected on normal operation
SC -> UB on OUT1 with Load 1 1 SC detected on normal operation
SC -> UB on OUT2 with Load 1 1 SC detected on normal operation
SC -> GND on OUT1 Open Load 0 0 OL not detected Double Fault
SC -> GND on OUT2 Open Load 1 0 OL detected
SC -> UB on OUT1 Open Load 1 0 OL detected
SC -> UB on OUT2 Open Load 1 1 OL not detected Double Fault

1 0

Figure 14.

VBatt

int 5V

1.5 mA

IN2IN1

22/25

OUT1

OUT2

1 mA

APPENDIX B
Figure 15. Voltage Supply of SPI-Logic and EN/DI-Logic

L9230

VBatt

EN
DI

DMS

SO
SI
SCK

SS

EN/DI­Logic

SPI­Logic

Output­Stage

internal
Vcc

DMS = GND EN/DI-Logic is supplied from internal VCC
DMS = VCC EN/DI-Logic is supplied from DMS (OR int. VCC)

Status
EN/DI

Undervoltage

on VBatt

Failure and Status
Output Stage

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L9230

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A 3.6 0.142
a1 0.1 0.3 0.004 0.012
a2 3.3 0.130
a3 0 0.1 0.000 0.004

b 0.4 0.53 0.016 0.021
c 0.23 0.32 0.009 0.013

D (1) 15.8 16 0.622 0.630

D1 9.4 9.8 0.370 0.386

E 13.9 14.5 0.547 0.570

e 1.27 0.050

e3 11.43 0.450

E1 (1) 10.9 11.1 0.429 0.437

E2 2.9 0.114
E3 5.8 6.2 0.228 0.244

G 0 0.1 0.000 0.004

H 15.5 15.9 0.610 0.626

h 1.1 0.043

L 0.8 1.1 0.031 0.043
N 8˚ (typ.)
S 8˚ (max.)
T 1 0 0.394

(1) “D and E1” do not include mold flash or protusions.

- Mold flash or protusions shall not ex ceed 0.15mm (0. 006”)

- Critical dimensions: “E”, “G” and “a3”.

OUTLINE AND

MECH ANICAL DATA

Weight:

1.9gr

JEDEC MO-166

PowerSO20

24/25

E2

h x 45

NN

a2

A

b

DETAIL A

e3

H

D

T

110

e

1120

E1

PSO20MEC

R

DETAIL B

BOTTOM VIEW

lead

a3

Gage Plane

E

DETAIL B

0.35

S

D1

L

c

a1

DETAIL A

slug

- C -

SEATING PLANE

GC

(COPLANARITY)

E3

0056635

L9230

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or oth erwise unde r any patent or patent r i ghts of STMi croelectroni cs. Speci fications me ntioned in this publicat ion are subj ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as crit i cal components in life support devices or sy st em s without express writt en approval of STMi croelectronics.

The ST logo is a registered trademark of STMicroelectronics

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