Page 1
查询L6919E供应商
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
■ 2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL
■ ULTRA FAST LOAD TRANSIENT RESPONSE
■ INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT
■ TTL-C O MPAT I BLE 5 BIT P R O GRAM MABL E
OUTPUT FROM 0.800V TO 1.550V WITH
25mV STEPS
■ DYNAMIC VID MANAGEMENT
■ 0.6% OUTPUT VOLTAGE ACCURACY
■
10% ACTIVE CURREN T SHARING ACCURACY
■ DIGITAL 2048 STEP SOFT-START
■ OVERVOLTAGE PROT ECTION
■ OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET'S R
SENSE RESISTOR
■ OSCILLATOR EXTERNALLY ADJUSTABLE
AND INTERNALLY FIXED AT 200kHz
■ POWER GOOD OUTPUT AND INHIBIT
FUNCTI ON
■ REMOTE SENSE BUFFER
■ PACKAGE: SO- 28
APPLICATIONS
■ POWER SUPPLY FOR SERVERS AND
WORKSTATIONS
■ POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS
■ DISTRI BUTED POWER SUPPLY
dsON
L6919E
WITH DYNAMIC VID MANAGEMENT
SO-28
ORDERING NUMBERS:L6919E
L6919ETR
DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC
conversion for high current microprocessors. The
device implements a dual-phase s tep-down con-
OR A
troller with a 180° phase-shift between each
phase. A precise 5-bit digital to analog con verter
(DAC) allows adjusting the output voltage from
0.800V to 1.550V with 25mV binary steps managing On-The-Fly VID code changes.
The high precision internal reference assures the
selected output voltage to be within ± 0.6%. The
high peak current gate drive affords to have fast
switching to the external power mos providing low
switching losses .
The device assures a fast protecti on against load
over current and load over/under voltage. An internal crowbar is provided turning on the low side
mosfet if an over-voltage is detected. In case of
over-current, the system works in Constant Current mode.
BLOCK DIAGRAM
PGOOD
PGOOD
September 2003
VID4
VID4
VID3
VID3
VID2
VID2
VID1
VID1
VID0
VID0
FBG
FBG
FBR
FBR
DIGITAL
DIGITAL
SOFT-STAR T
SOFT-STAR T
DAC
DAC
32k
32k
32k
32k
32k
32k
32k
32k
REMOTE
REMOTE
BUFFER
BUFFER
OSC /INH SGND VCCDR
OSC /INH SGND VCCDR
PWM1
TO TA L
TO TA L
CURRENT
CURRENT
CURRENT
CURRENT
PWM1
PWM2
PWM2
LOGIC PWM
LOGIC PWM
LOGIC PWM
ADAPTIVE ANTI
ADAPTIVE ANTI
CH1
CH1
OCP
OCP
CURRENT
CURRENT
CORR ECTION
CORR ECTION
AVG
AVG
CH2
CH2
OCP
OCP
CURRENT
CURRENT
CORRECTION
CORRECTION
ADAPTIVE ANTI
CRO SS COND UCT ION
CRO SS COND UCT ION
CRO SS COND UCT ION
CURRENT
CURRENT
CURRENT
READING
READING
READING
CURRENT
CURRENT
CURRENT
READING
READING
READING
LOGIC PW M
LOGIC PW M
LOGIC PW M
ADAPTIVE ANTI
ADAPTIVE ANTI
ADAPTIVE ANTI
CROSS CONDUCTION
CROSS CONDUCTION
CROSS CONDUCTION
Vcc
Vcc
VccCOM PFBVSEN
VccCOM PFBVSEN
I
I
FB
FB
2 PHASE
2 PHASE
LOGIC AND
LOGIC AND
CH1 OCP
CH1 OCP
OSCI LLATO R
OSCI LLATO R
PROTECTIONS
PROTECTIONS
CH2 OCP
CH2 OCP
VCC
VCC
VCCDR
VCCDR
ERR OR
ERR OR
AMPLIFIER
AMPLIFIER
BOO T1
BOO T1
HS
HS
LS
LS
LS
LS
HS
HS
U
U
GAT E1
GAT E1
PHASE1
PHASE1
LGATE1
LGATE1
ISEN1
ISEN1
PGNDS1
PGNDS1
PGND
PGND
PGNDS2
PGNDS2
ISEN2
ISEN2
LGATE2
LGATE2
PHASE2
PHASE2
UGATE2
UGATE2
BOO T2
BOO T2
1/33
Page 2
L6919E
R
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
Vcc, V
CCDR
V
BOOT-VPHASE
V
UGATE1-VPHASE1
V
UGATE2-VPHASE2
V
phase
UGATEx Pin Maximum Withstanding Voltage Range
OTHER PINS ±2000 V
THERMAL DATA
Symbol Parameter Value Unit
to PGND 15 V
Boot Voltage 15 V
15 V
LGATE1, PHASE1, LGATE2, PHASE2 to PGND -0.3 to Vcc+0.3 V
VID0 to VID4 -0.3 to 5 V
All other pins to PGND -0.3 to 7 V
Sustainable Peak Voltage t < 20ns @ 600kHz 26 V
±1000 V
Test Conditio n: CDF-AEC-Q100-002”Human Body Model
Acceptance Criteria: “Normal Performance”
”
R
th j-amb
T
T
storage
P
PIN CONNECTION
Thermal Resistance Junction to Ambient 60 °C/W
Maximum junction temperatu re 150 °C
max
Storage temperature range -40 to 150 °C
T
Junction Temperature Range 0 to 125 °C
j
Max power dissipation at T
MAX
= 25°C 2 W
amb
LGATE1
1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
SGND
COMP
FB
VSEN
FB
FBG
ISEN1
PGNDS1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
L6919E
23
22
21
20
19
18
17
16
15
PGND
LGATE2
PHASE2
UGATE2
BOOT2
PGOOD
VID4
VID3
VID2
VID1
VID0
OSC / INH / FAULT
ISEN2
PGNDS
2/33
Page 3
L6919E
ELECTRICAL CHARACTERISTICS
V
= 12V
CC
Symbol Parameter Test Condition Min Typ Max Unit
Vcc SUPPLY CURRENT
±15%
, TJ = 0 to 70°C unless otherwise specified
I
I
CCDR
I
BOOTx
Vcc supply current HGATEx and LGATEx open
CC
V
supply current LGATEx open; V
CCDR
Boot supply current HGATEx open; PHASEx to PGND
POWER-ON
Turn-On V
Turn-Off V
Turn-On V
threshold VCC Rising; V
CC
threshold VCC Falling; V
CC
CCDR
Threshold
Turn-Off V
CCDR
Threshold
OSCILLATOR/INHIBIT/FAULT
f
OSC
Initial Accuracy OSC = OPEN
INH Inhibit threshold I
d
MAX
Maximum duty cycle OSC = OPEN; IFB = 0 72 80 %
7.5 10 12.5 mA
V
CCDR=VBOOT
=12V
=12V 2 3 4 mA
CCDR
0.5 1 1.5 mA
V
CC=VBOOT
V
CCDR
V
=12V
CC
V
CCDR
=12V
Rising
Falling
=5V 8.2 9.2 10.2 V
CCDR
=5V 6.5 7.5 8.5 V
CCDR
4.2 4.4 4.6 V
4.0 4.2 4.4 V
VCC=12V
OSC = OPEN; Tj=0°C to 125°C
=5mA 0.5 V
SINK
OSC = OPEN; I
= 70µA3040 %
FB
127
135
150 165
178
kHz
kHz
∆Vosc Ramp Amplitude 3 V
FAULT Voltage at pin OSC OVP or UVP Active 4.75 5.0 5.25 V
REFERENCE AND DAC
I
DAC
Output Voltage
Accuracy
VID pull-up Current VIDx = GND 4 5 6 µA
VID0, VID1, VID2, VID3, VID4
see Table1;
FBR = V
; FBG = GND
OUT
-0.6 - 0.6 %
VID pull-up Voltage VIDx = OPEN 2.9 - 3.3 V
ERROR AMPLIFIER
DC Gain 80 dB
SR Slew-Rate COMP=10pF 15 V/µs
DIFFERENTIAL AMPLIFIER (REMOTE BUFFER)
DC Gain 1 V/V
CMRR Common Mode Rejection Ratio 40 dB
SR Slew Rate VSEN=10pF 15 V/µs
3/33
Page 4
L6919E
ELECTRICAL CHARACTERISTICS (continued)
V
= 12V
CC
Symbol Parameter Test Condition Min Typ Max Unit
DIFFERENTIAL CURRENT SENSING
I
ISEN1
I
ISEN2
±15%
, TJ = 0 to 70°C unless otherwise specified
,
Bias Current I
= 0 45 50 55 µA
LOAD
I
PGNDSx
I
ISEN1
I
ISEN2
I
Bias Current 45 50 55 µA
,
Bias Current at
Over Current Threshold
Active Droop Current I
FB
GATE DRIVERS
t
RISE
HGATE
I
HGATEx
High Side
Rise Time
High Side
Source Current
R
HGATEx
High Side
Sink Resistance
t
RISE
LGATE
I
LGATEx
Low Side
Rise Time
Low Side
Source Current
R
LGATEx
Low Side
Sink Resistance
PROTECTIONS
PGOOD Upper Threshold
(V
/DAC Output)
SEN
80 85 9 0 µA
≤ 0%
LOAD
I
= 100%
LOAD
V
BOOTx-VPHASEx
C
V
V
V
C
V
V
V
to PHASEx=3.3nF
HGATEx
BOOTx-VPHASEx
BOOTx-VPHASEx
=10V;
CCDR
to PGNDx=5.6nF
LGATEx
=10V 1.8 A
CCDR
=12V 0.7 1.1 1.5 Ω
CCDR
Rising 108 112 116 %
SEN
=10V;
=10V 2 A
=12V; 1.5 2 2.5 Ω
47.5
0
50
15 30 ns
30 55 ns
1
52.5
µA
µA
PGOOD Lower Threshold
(V
/DAC Output)
SEN
OVP Over Voltage Threshold
(V
)
SEN
UVP Under Voltage Trip
(V
/DAC Output)
SEN
V
PGOODL
I
PGOODH
PGOOD Voltage Low I
PGOOD Leakage V
4/33
V
Falling 84 88 92 %
SEN
V
Rising 1.915 2.05 V
SEN
V
Falling 55 60 65 %
SEN
= -4mA 0.4 V
PGOOD
= 5V 1 µA
PGOOD
Page 5
Table 1. Voltage Identification (VID) Codes
VID4 VID3 VID2 VID1 VID0
00000 1.575 10000 1.175
00001 1.550 10001 1.150
00010 1.525 10010 1.125
00011 1.500 10011 1.100
00100 1.475 10100 1.075
00101 1.450 10101 1.050
00110 1.425 10110 1.025
00111 1.400 10111 1.000
01000 1.375 11000 0.975
01001 1.350 11001 0.950
01010 1.325 11010 0.925
01011 1.300 11011 0.900
01100 1.275 11100 0.875
01101 1.250 11101 0.850
01110 1.225 11110 0.825
01111 1.200 11111Shutdown
The device automatically regulates 25m V higher than the Hammer specs avoid ing the use of any external offset resistor
Output
Voltage (V)
VID4 VID3 VID2 VID1 VID0
Voltage (V)
L6919E
Output
Reference Schematic
Vin
GNDin
L1
S4
S3
S2
S1
S0
HS1
LS1
C
IN
24
25
26
27
16
15
28
23
10
VCC
6
BOOT2
UGATE2
PHASE2
LGATE2
ISEN2
Rg
PGNDS2
PGND
Rg
PGOOD
VSEN
FB
9
COMP
8
HS2
L2
LS2
C
OUT
LOAD
PGOOD
R
FB
R
F
C
F
VCCDR
2
BOOT1
5
UGATE1
PHASE1
LGATE1
ISEN1
PGNDS1
VID4
VID3
VID2
VID1
VID0
OSC / INH
SGND
4
3
1
13
14
L6919E
22
21
20
19
18
17
7
11 12
FBR FBG
Rg
Rg
5/33
Page 6
L6919E
PIN FUNCTION
N Nam e Description
1 LGATE1 Channel 1 LS driver output.
A little series resistor helps in reducing device-dissipated power.
2 VCCDR LS drivers supply: it can be varied from 5V to 12V buses.
Filter locally with at least 1µF ceramic cap vs. PGND.
3 PHASE1 Channel 1 HS driver return path. It must be connected to the HS1 mosfet source and provides
4 UGATE1 Channel 1 HS driver output.
5 BOOT1 Channel 1 HS driver supply. This pin supplies the relative high side driver.
6 VCC Device supply voltage. The operative supply voltage is 12V ±10%.
7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
8 COMP This pin is connected to the error amplifier output and is used to compensate the control
9 FB This pin is connected to the error amplifier inverting input and is used to compensate the
10 VSEN Manages Over&Under-voltage conditions and the PGOOD signal. It is internally connected with
11 FBR Remote sense buffer non-inverting input. It has to be connected to the positive side of the load
12 FBG Remote sense buffer inverting input. It has to be connected to the negative side of the load to
13 ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or
14 PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be
15 PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be
16 ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or
the return path for the HS driver of channel 1.
A little series resistor helps in reducing device-dissipated power.
Connect through a capacitor (100nF typ.) to the PHASE1 pin and through a diode to VCC
(cathode vs. boot).
Filter with 1µF (Typ.) capacitor vs. GND.
feedback loop.
voltage control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50µA at full load, 70µA at the Constant Current threshold). Connecting a resistor between this
pin and VSEN pin allows programming the droop effect.
the output of the Remote Sense Buffer for Remote Sense of the regulated voltage.
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
manage OVP, UVP and PGOOD.
Connecting 1nF capacitor max vs. SGND can help in reducing noise injection.
to perform a remote sense.
If no remote sense is implemented, connect directly to the output voltage (in this case connect
also the VSEN pin directly to the output regulated voltage).
perform a remote sense.
Pull-down to ground if no remote sense is implemented.
across the low-side mosfet R
to the sense resistor through a resistor Rg.
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS net in order to couple in common mode any picked-up noise.
routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up
noise.
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up
noise.
across the low-side mosfet R
to the sense resistor through a resistor Rg.
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS net in order to couple in common mode any picked-up noise.
This pin has to be connected to the low-side mosfet drain or
dsON.
This pin has to be connected to the low-side mosfet drain or
dsON.
6/33
Page 7
L6919E
PIN FUNCTION
N Name Description
17 OSC/INH
18-22 VID4-0 Voltage IDentification pins.
23 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above
24 BOOT2 Channel 2 HS driver supply. This pin supplies the relative high side driver.
25 UGATE2 Channel 2 HS driver output.
26 PHASE2 Channel 2 HS driver return path. It must be connected to the HS2 mosfet source and provides
27 LGATE2 Channel 2 LS driver output.
28 PGND LS drivers return path.
(continued)
FAULT
Oscillator pin.
It allows programming the switching frequency of each channel: the equivalent switching
frequency at the load side results in being doubled.
Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from
(into) the pin with an internal gain of 6kHz/µA (See relevant section for details). If the pin is not
connected, the switching frequency is 150kHz for each channel (300kHz on the load).
The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this
condition, cycle VCC.
Forcing the pin to a voltage lower than 0.6V, the device stop operation and enter the inhibit
state.
Internally pulled-up, connect to GND to program a ‘0’ while leave floating to program a ‘1’.
They are used to program the output voltage as specified in Table 1 and to set the PGOOD,
OVP and UVP thresholds.
The device automatically regulates 25mV higher than the HAMMER DAC avoiding the use of
any external set-up resistor.
specified thresholds and during soft start. It cannot be pulled-up above 5V.
If not used may be left floating.
Connect through a capacitor (100nF typ.) to the PHASE2 pin and through a diode to VCC
(cathode vs. boot).
A little series resistor helps in reducing device-dissipated power.
the return path for the HS driver of channel 2.
A little series resistor helps in reducing device-dissipated power.
This pin is common to both sections and it must be connected through the closest path to the
LS mosfets source pins in order to reduce the noise injection into the device.
7/33
Page 8
L6919E
DEVICE DESCRIPTION
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for
a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg phase shift is
provided between the two phases allowing reduction in the input capacitor current ripple, reducing also the size and
the losses. The output vo ltage of the co nverte r can be precise ly regul ated, prog rammi ng the VID pins, from 0.825V to
1.575V with 25mV bina ry steps, with a maxim um tolerance of ±0.6 % over temperature and l ine voltage variat ions. The
device aut om ati cally regulates 25mV higher than the HAMMER DAC avoiding the use of any external set-up resistor.
The device manages On-Th e-Fly VID Code chang es stepp ing to the ne w confi guration f ollow ing the VID tabl e with no
need for external components. The device provides an average current-mode control with fast transient response. It
includes a 150kHz free-running oscillator. The error am pl if i er f eatures a 15V/
bandwidth for fast transient performances. Current information is read across the lower mosfets RdsON or across a
sense resist or i n fully differential mode. The current information corrects the PWM output i n order to equ alize the average cu rr ent carried by each phase. Current sharing between the two phases i s then limited at ±10% over static a nd
dynamic c ondi tions. The device protect s against Over- C urr ent , with an OC thr eshold for each phase, en tering in constant current mode. Since the current is read across the low side mosfets, the constant current keeps constant the
bottom of the inductors current triangular waveform. When an under voltage is detected the device latches and the
FAULT pin is dri ven high. The devi ce performs also Over-Volta ge protection t hat disables i mmediately the device turning ON the lower driver and driving high the FAULT pin.
OSCILLATOR
The switching frequency is internally fixed at 150kHz. Each phase works at the frequency fixed by the oscillator so
that the result ing switching frequency at the load side results in being doubled.
The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an in ter nal c apac itor . The curre nt deliv ere d to th e os cilla tor is typ icall y 25 A (F sw=150kHz) and may be varied
using an external resist or (ROSC) connected between OSC pin and GND or Vcc. Since the OSC pin is m ai ntained at
fixed voltage (Typ. 1.237V), th e fr equency is varied proportionally to the current sunk (f or ced) from (into) the pin considering the internal gain of 6KHz/
µ
A.
In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC
to Vcc=12V the freq uency is reduced (current is for ced i nto the pin), according to the fo llowing relationships :
vs. GND: fS150kHz
R
OSC
1.237
---------------
R
OSC
kHz
-----------
6
⋅+ 150kHz
µA
µ
s slew rate that per mits high converter
6
⋅
7.422 10
----------------------------- -+==
R
OSC
KΩ()
7
⋅
KΩ()
R
OSC
vs. 12V: f
S
150kHz
12 1.237–
---------------------------
R
OSC
kHz
-----------
6
⋅– 150kHz
µA
6.457 10
------------------------------–==
R
OSC
Note that forcing a 25µA into this pin, the device stops switching because no current is delivered to the oscillator.
Figure 1. R
8/33
vs. Switching Frequency
OSC
14000
12000
10000
8000
) vs. 12V
Ω
Ω
Ω
Ω
6000
4000
Rosc(K
2000
0
25 50 75 100 125 150
Frequency (KHz)
800
700
600
500
) vs. GND
400
Ω
Ω
Ω
Ω
300
200
Rosc(K
100
0
150 250 350 450 550 650
Frequency (KHz)
Page 9
L6919E
DIGITAL TO ANALOG CONVERTER
The built-in digital to analog converter allows the adjustment of the output voltage from 0.800V to 1.550V with
25mV as shown in the previous table 1. The internal reference is trimmed to ensure output voltage precision of
±0.6% and a zero temperature coefficient around 70°C. The internal reference voltage for the reg ulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is
realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code
drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an
amplifier obtaining the V
provided (realized with a 5
to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. Programming the
"11111" code, the device enters the NOCPU mode: all mosfets are turned OFF and protections are disabled.
The condition is latched.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over
/ Under Voltage protection (OVP/UVP) thresholds.
DYNAMIC VID TRANSITION
The device is able to manage On-The-Fly VID Code changes that allow Output Voltage modification during normal device operation. The device checks every clock cycle (synchronously with the PWM ramp) for VID code
modifications. Once the new code is stable for more than one clock cycle, the reference steps up or down in
25mV increments every c lock cycle until the new VID code is reached. D uring the transiti on, VID code c hanges
are ignored; the devi ce re- starts monit oring V ID after the transiti on has finis hed. P GOOD, signal is mask ed during the transition and it is re-activated after the transition has finished while OVP / UVP are still active.
voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are
PROG
µ
A current generator up to 3.0V Typ); in this way, to program a logic "1" it is enough
Figure 2. Dynamic VID transition
VID
Reference
25mV steps transition
V
OUT
1 Clock Cycle Blanking Time
DRIVER SECTION
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the
R
), maintaining fast switching transition.
dsON
The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for
the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VCCDRV pin is required to start operations of the device.
The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction
time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanoseconds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side
mosfet turns off, the voltage on its source begins to fall; when the voltage reach es 2V, the low-side mosfet gate
drive is applied with 30ns delay. When the low-side mo sfet turns off, the v oltage at LGATEx pin i s sensed. When
it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the
inductor is negative, the source of high-side mosfet will never drop.
t
t
t
9/33
Page 10
L6919E
Figure 3. Drivers peak current: High Side (left) and Low Side (right)
CH3 = HGATE1; CH4 = HGATE2 CH3 = LGATE1; CH4 = LGATE2
To allow the turning on of the low-side mosfet even in this case, a watchdog controller is enabled: if the source
of the high-side mosfet don't drop for more than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is
negative.
The BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND
pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply
for the diff erent drivers gives high flexibility in mosfet choice, allow ing the use of logic-lev el mosfet. S everal combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion
is also flexible; 5V or 12V bus can be chosen freely.
The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capacitive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with
V
BOOT -VPHASE
VCCDR = 1 2V.
= 12V; similar ly, for the lower driv ers, the sour ce c urrent is 2.4A while the sink cur rent is 2A w ith
CURRENT READING AND OVER CURRENT
The current flowing trough each phase is read using the voltage drop across the low side mosfets R
across a sense resistor (R
) and internally converted into a current. The Tran conductance ratio is issued
SENSE
dsON
or
by the external resistor R g placed outsi de the chip between ISEN x and PGNDSx pins toward the reading points.
The full differential current readi ng rejects noi se and allow s to place sensing el ement in differ ent lo cations without affecting the measurement's accuracy. The current reading circuitry reads the current during the time in
which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx
at the same voltage while during the time in w hich th e reading circ uitry is off, an internal clamp ke eps these two
pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet R
dsON
sense is implemented to avoid absolute maximum rating overcome on ISENx pin).
The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and
negative current. This circuit reproduces the current flowing through the sensing element using a high speed
Track & Hold Tran conductance amplifier. In particular, it reads the current during the second half of the OFF
time reducing noise injection into the device due to the mosfet turn-on (See fig. 4). Track time must be at least
200ns to make proper reading of the delivered current
This circuit sources a constant 50
µ
A current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at
the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following
equation:
10/33
I
ISENx
50µA
R
SENSEIPHASE
----------------------------------------------+ 50µAI
R
⋅
g
+==
INFOx
Page 11
Figure 4. Current Reading Timing (Left) and Circuit (Right)
I
LS1
I
LS2
Total current
information
Track & H old
LGATEX
ISENX
PGNDSX
50
I
ISENx
Rg
Rg
µµµµ
L6919E
SENSE
R
A
PHASE
I
Where R
resistor used between ISE Nx and PGNDSx pins toward the reading points; I
is an external sense resi stor or the rds,on of the l ow side mosfet and Rg is the transconductance
SEN SE
is the current car ried by each
PHASE
phase and, in particular, the current measured in the middle of the oscillator period
The current information reproduced internally is represented by the second term of the previous equation as
follow:
I
INFOx
R
SENSEIPHASE
----------------------------------------------=
R
⋅
g
Since the current is read in differential mode, also negative current information is kept; this allow the device to
check for dangerous returning current between the two phases assuring the complete equalization between the
phase's currents. From the current information of each phase, information about the total current delivered (I
=I
pared to I
The transconductance resistor Rg can be designed in order to have current information of 25
full nominal load; the over current intervention threshold is set at 140% of the nominal (I
to the above relationship, the over current threshold (I
INFO1
+I
) and the average current for each phase (I
INFO 2
to give the c orrection to the PW M output in order to equalize the c urrent carried by the two phas es.
AVG
OCPx
AVG
=(I
INFO 1
+I
)/2 ) is taken. I
INFO 2
INFOX
µ
A per phase at
= 35µA). According
INFOx
) for each phase, which has to be placed at one half
is then com-
FB
of the total delivered maximum current, results:
I
I
OCPx
35µARg⋅
---------------------------= Rg
R
SENSE
⋅
OCPxRSENSE
------------------------------------------ -=
35µA
Since the device senses the output current across the low-side mosfets (or across a sense resistors in series
with them) the device limits the bottom of the inductor current triangular waveform: an over current is detected
when the current flowing into the sense element is greater than I
OCPx
(I
INFO x
> 35µA).
Introducing now the maximum ON time dependence with the delivered current (where T is the switching period
T=1/f
):
SW
T
ON,MAX
0.80 IFB5.73k⋅()T⋅– 0.80
⋅ 0µA =
R
SENSE
----------------------
Rg
I
OUT
5.73k⋅⋅
0.80 T I
T
⋅–==
0.40 T I
FB
⋅ 70µA=
FB
This linear dependence has a v alue at zero load of 0.80·T and at maxi mum cur rent of 0.40·T typi cal and resul ts
in two different behaviors of the device:
11/33
Page 12
L6919E
U
1. TON Limited Output Voltage.
This happens when the maximum ON time is reached before the current in each phase reaches I
< 35µA).
Figure 5a shows the maximum output voltage that the device is able to regulate considering the T
imposed by the p revious relati onship. If the desired outpu t char acteri stic crosse s the T
limited maximum output
ON
voltage, t he ou tput resulting vol tage will start to drop a fter c ross ing . In th is c ase , the dev ice does n' t perfo r m co nstant current limitation but only limits the maximum ON time following the previous relationship. The output voltage follows the resulting characteristic (dotted in Figure 5b) until UVP is detected or anyway until I
Figure 5. TON Limited Operation
0.80·V
0.40·V
V
OUT
IN
IN
TON Limited Output
characteristic
V
0.80·V
0.40·V
OUT
IN
IN
Resulting Output
Desired Output
characteristic and
(I
OCPx
limitation
ON
= 70µA.
FB
characteristic
VP threshold
INFOx
I
OCP
(I
FB
=2·I
OCPx
=70µA)
I
OUT
I
OCP
(I
FB
=2·I
OCPx
=70µA)
I
OUT
a) Maximum output Voltage b) TON Limited Output Voltage
2. Constant Current Operation
This happens when ON time limitation is reached after the current in each phase reaches I
OCPx
(I
INFO x
>35µA).
The device enters in Quasi-Constant-Current operation: the low-side mosfets stays ON until the current read
becomes lower than I
a T
imposed by the control loop at the next available clock cycle and the device works in the usual way until
ON
OCPx
(I
< 35µA) skipping clock cycles. The high side mosfets can be turned ON with
INFO x
another OCP event is detected.
This means that the average curr ent delivered can sl ightly increase al so in Over Curr ent condition sinc e the current ripple incr eases. In fact, the ON time increases due to the OFF ti me rise because of the current has to reach
the I
bottom. The worst-case condition is when the ON time reaches its maximum value.
OCPx
When this happens, the device works in Constant Current and the output voltage decrease as the load increase.
Crossing the UVP threshold causes the device to latch (FAULT pin is driven high).
Figure 6 shows this working condition
It can be observed that the peak current (Ipeak) is greater than the I
VINVout
Where V
–
Ipeak I
is the minimum output voltage (VID-30% as follow).
outMIN
OCPx
-------------------------------------- -
MIN
Ton
⋅+ I
L
MAX
OCPx
but it can be determined as follow:
OCPx
VINVout
–
-------------------------------------- -
MIN
L
0.40 T⋅⋅+==
The device works in Constant-Current, and the output voltage decreases as the load increase, until the output
voltage reaches the Under-Voltage threshold (V
). When this threshold is crossed, all mosfets are turned
outMIN
off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The
maximum average current during the Constant-Current behavior results:
Ipeak I
–
I
MAX,TOT
2I
MAX
2I
⋅+⋅=
OCPx
------------------------------------- -+
OCPx
2
12/33
Page 13
Figure 6. Con s ta nt C urrent opera ti on
Ipeak
I
MAX
L6919E
Vout
Droop effect
TonMAX
I
OCPx
TonMAX
UVP
(IFB=50
Iout
MAX,TOT
I
A)
µ
I
=2·I
OCP
OCPx
(IFB=70µA)
a) Maximum current for each phase b) Output Characteristic
In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed
(T
Over current is set anyway wh en I
to work with conveni ent values for I
) while the OFF t i m e depends on the appli c ation:
onMAX
Ipeak I
T
OFF
------------------------------------- -
L
⋅= f
reaches 35µA (IFB = 70µA). The full load value i s only a co nvention
INFOx
. Since the OCP intervention t hreshold i s fixed, to modif y the percent -
FB
V
–
OUT
OCPx
------------------------------------------=
T
1
ONma xTOFF
+
age with respect to t he load val ue, it can be sim ply consider ed that, for exampl e, to have on OC P threshol d
of 170%, this will correspond to I
I
= 20.6µA (IFB = 41.1µA).
INFOx
= 35µA (IFB = 70µA). The full load current will then correspond to
INFOx
Integrated Droop Function
The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing
the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current
As shown in figure 7, the ESR drop is pr esent in any c ase, but using the droop func tion the total dev iation o f the
output voltage is minimized . In practice the droop function introduces a static error (V
in figure 8) propor-
DROOP
tional to the output c urrent. Si nce the devic e has an average c urrent mode regulati on, the i nformation abo ut the
total current delivered is used to implement the Droop Function.
This current (equ al to the sum of both I
and V
, the total current information flows only in this resistor because the compensation network between
OUT
) is sourced from the FB pin. Connecting a resistor between this pin
INFO x
FB and COMP has always a capacitor in series (See fig. 8). The voltage regulated is then equal to:
= VID - RFB · I
V
OUT
FB
Since IFB depends on the current information about the two phases, the output characteristic vs . load cur rent is
given by:
R
SENSE
V
OUT
VID R
FB
----------------------
⋅⋅–=
Rg
I
OUT
13/33
Page 14
L6919E
Figure 7. Output transient response without (a) and with (b) the droop function
ESR DROP ESR DROP
VMAX
VNOM
VMIN
(a) (b)
Figure 8. Active Droop Function Circuit
VDROOP
VDROOP
R
R
FB
COMP FB
COMP FB
Ref
Ref
FB
Total Curr ent Info (I
Total Curr ent Info (I
The feedback current is equal to 50µA at nominal full load (IFB = I
threshold, so the maximum output voltage deviation is equal to:
∆
V
FULL_POSITIVE_LOAD
= -RFB · 50µA
∆
OUT
OUT
To V
To V
)
)
INFO1+IINFO2
INFO1+IINFO2
+ I
INFO 1
V
OC_INTERVENTION
INFO 2
VDROOP
) and 70µA at the OC intervention
= -RFB · 70µA
Droop function is provided only for positive load; if negative load is applied, and then I
< 0, no current is
INFOx
sunk from the FB pin. The device regulates at the voltage programmed by the VID.
REMOTE VOLTAGE SENSE
A remote sense buffer is integrated into the dev ice to allow output voltage remo te sense implementation without
any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM
module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR
is for the regulated voltage sense while FBG is for the ground sense) and r eports this voltage internall y at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power
plane results in common mode coupling for any picked-up noise.
If remote sense is not required, it is enough connecting RFB directly to the regulated voltage: VSEN becomes
not connected and stil l sense s the output v oltage through the remote buffer . In thi s case the FB G and FBR pins
must be connected anyway to the regulated voltage (See figure 10).
The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy on the output voltage
when the RB Is used: eliminating it from the control loop causes the regulation error to be increased by the RB
offset worsening the device performances.
14/33
Page 15
Figure 9. - Remote Buffer Connections
L6919E
Reference
ERROR
FB
C
F
AMPLIFIER
COMP
R
F
IFB
R
FB
64k
64k
FBR
Remote
V
OUT
R
FB
Reference
IFB
FB
C
F
ERROR
AMPLIFIER
COMP
R
F
64k
64k
FBR
REMOTE
BUFFER
64k
64k
FBG
Remote
Ground
VSEN
64k
FBG
64k
REMOTE
BUFFER
VSEN
V
OUT
RB used (±0.5% Accuracy) RB Not Used
OUTPUT VOLTAGE MONITOR AND PROTECTIONS
The device monitors through pin VSEN the regulated voltage in order to build the PGOOD signal and manage
the OVP / UVP conditions.
Power good output is forced low if the voltage sensed by VSEN is not within ±12% (Typ.) of the programmed
value. It is an open drain output and it i s enabled only after the soft sta rt is finished (2048 clock cycles after star tup). During Soft-Start this pin is forced low.
Under voltage protection is provided. If the output voltage monitored by VSEN drops below the 60% of the reference voltage for more than one clock period, the device turns off all mosfets and the OSC/FAULT is driven
high (5V). The condition is latched, to recover it is required to cycle the power supply.
Over Voltage protection is also provided: when the voltage monitored by VSEN reaches the OVP threshold
VOVP the controller permanently switches on both the low-side mosfets and switches off both the high-side
mosfets in order to protect the load. The OSC/ FAULT pin is driven high (5V) and power supply (Vcc) turn off
and on is required to restart operations.
The over voltage percentage is then set by the ratio between the fixed OVP threshold VOVP and the reference
programmed by VID:
V
OVP %[]
---------------------------------------------------------------------- -
ReferenceVo ltage VID()
OVP
100⋅=
Both Over Voltage and Under Volt age are activ e also during soft star t (U nder Voltage after than the output voltage reaches 0.6V). The reference used in this case to determine the UV thresholds is the increasing voltage
driven by the 2048 soft start digital counter while the reference used for the OV threshold is the final reference
programmed by the VID pins.
SOFT START AND INHIBIT
At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in
2048 clock periods as shown in figure 10.
Once the soft start begins, the reference is increased: upper and lower MOS begin to switch and the output voltage starts to increase w ith closed l oop regulation. At the end of the digital soft start, the P ower Good comparator
is enabled and the PGOOD signal is then driven high (See fig. 10). The Under Voltage comparator is enabled
when the reference voltage reaches 0.6V. The Soft-Start will not take place, if both VCC and VCCDR pins are
not above their own turn-on thresholds.
During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down.
Forcing the OSC/INH pin to a voltage lower than 0.6V (Typ.) disables the device: all the power mosfets and
protections are turned off until the condition is removed.
15/33
Page 16
L6919E
R
x
T
Figure 10. Soft Start
VCC=V
CCD
V
LGA TE
Tur n ON thr eshold
t
V
OU
PGOOD
2048 Clo ck Cycles
t
t
t
Timing Diagram Acquisition:
(CH1=LGATEx; CH2=VCC; CH3=VOUT;
INPUT CAPACITOR
The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as
reported in figure 11. Considering the dual-phase topology, the input RMS current is highly reduced comparing
with a single phase operation.
Figure 11. Input RMS Current vs. Duty Cycle (D) and Driving Relationships
)
OUT
/I
RMS
0.50
0.25
Single Phase
Dual Phase
I
rms
I
OUT
2
=
I
OUT
2
<−⋅⋅
5.0DifD)2(12D
>−⋅⋅
0.5DifD)2(21)-(2D
Rms Current Norm a l i ze d (I
0.50 0.75 0.25
Duty Cycle (V
OUT/VIN
)
It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst
case condition that happens for D = 0.25 and D = 0.75.
The power dissipated by the input capacitance is then equal to:
P
RMS
ESR I
⋅=
()
2
RMS
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the
high RMS value needed by the CPU power supply application and also to minimize components cost, the input
capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of
the single capacitor's RMS current.
Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible
16/33
Page 17
L6919E
to reduce switching noise above all during load transient. Cerami c capacitor can also intr oduc e benefits in high
frequency noise decoupling, noise generated by parasitic components along power path.
OUTPUT CAPACITOR
Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the
range of tenth A/
Dual ph ase to polo gy r educ es th e am ount o f outpu t cap acit ance neede d b ecau se of faste r load tran sient r esp onse
(switching frequency is doubled at the load connections). Current ripple cancellation due to the 180° phase shift
between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple.
When a lo ad tr ansien t is app lied to the conv erter 's outp ut, for first few m icros econ ds the curren t to th e load is supplied b y th e outp ut ca paci tors. The co ntr oller re cogniz es imm edia tel y the lo ad t ransi ent and i ncr eases t he du ty
cycle, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where D
MAX
transient and the lower is the output voltage static ripple.
µ
s, the output capacitor is a basic component for the fast response of the power supply.
∆
V
= ∆I
OUT
V
∆
OUT
-----------------------------------------------------------------------------------=
4C
OUTVINDMAXVOUT
· ESR
OUT
2
∆ L⋅
I
OUT
–⋅()⋅⋅
is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load
INDUCTOR DESIGN
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current
∆
IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
Where f
–
V
INVOUT
------------------------------
L
f
SWIL
is the switching frequency, VIN is the input voltage and V
SW
V
OUT
-------------- -
⋅=
∆⋅
V
IN
is the output voltage.
OUT
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. The response time is the time required by the inductor to change its current
from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by
the output capacitors. Minimizing the response time can minimize the output capacitance required.
The response time to a load transient is different for the application or the removal of the load: if during the application of the loa d the inductor is c harged by a voltage equal to the differ ence between the input and th e output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for
∆
I load transient in case of enough fast compensation network response:
t
applicatio n
LI∆⋅
------------------------------=
–
V
INVOUT
t
removal
LI∆⋅
-------------- -=
V
OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response ti me after removal o f the load with the mi nimum output v oltage progr ammed and the maximum input voltage available.
17/33
Page 18
L6919E
Figure 12. Inductor ripple current vs V
Inductor Ripple [A]
OUT
9
8
7
6
5
4
3
2
1
L=1.5µH, Vin=12V
L=3µH, Vin=5V
L=2µH,
Vin=12V
L=3µH,
Vin=12V
L=1.5µH,
Vin=5V
L=2µH,
Vin=5V
0
0.5 1.5 2.5 3.5
Output Voltage [V]
MAIN CONTROL LOOP
The control loop is composed by the Current Sharing control loop and the Average Current Mode control loop.
Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation:
the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control
loop fixes the output voltage e qual to the referen ce programmed by VID. Figure 13 r eports the bl ock di agram of
the main control loop.
Figure 13. Main Control Loop Diagram
L
I
INFO2
1
+
PWM1
1/5
CURRENT
SHARING
DUTY CYCLE
1/5
+
PWM2
ERROR
AMPLIFIER
4/5
CORRECTION
REFERENCE
PROGRAMMED
+
BY VID
-
I
INFO1
L
2
C
O
R
O
FBCOMP
D02IN1392
Z
F(S)
R
FB
Current Sharing (CS) Control Loop
Active current sharing is implemented using the information from Tran conductance differential amplifier in an
average current mode control scheme. A current reference equal to the average of the read current (I
AVG
) is in ternally built; the error between the read current and this reference is converted to a voltage with a proper gain
and it is used to adju st the duty c ycle whose d ominant val ue is set by the error ampli fier at COM P pin (See fi g. 14).
The current sharing control is a high bandwidth control loop allowing current sharing even during load transients.
The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is
18/33
Page 19
L6919E
necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran
conductance differential amplifie r; cons idering a voltage offset equal to 2mV acr oss the sense resis tor, the current reading error is given by the following equation:
I
∆
READ
------------------- -
I
MAX
Where
For R
∆
I
READ
SENSE
is the difference between one phase current and the ideal current (I
= 4mΩ and I
= 40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and
MAX
Rsense mismatches.
Figure 14. Current Shari n g C ontrol Loop
+
PWM1
1/5
1/5
2mV
----------------------------------------=
R
SENSEIMAX
CURRENT
SHARING
DUTY CYCLE
CORRECTION
⋅
I
INFO2
I
INFO1
/2).
MAX
L
1
+
COMP
PWM2
D02IN1393
L
2
V
OUT
Average Current Mode (ACM) Control Loop
The average current mode control loop is reported in figure 15. The current information IFB sourced by the FB
pin flows into RFB implementing the dependence of the output voltage from the read current.
The ACM control loop gain results (obtained opening the loop after the COMP pin):
G
LOOP
s()
--------------------------------------------------------------------------------------------------------------------=
s() ZLs()+()
Z
P
PWM Z
s() R
F
DROOPZP
s()
Z
F
-------------- - 1
As()
s()+()⋅⋅
1
----------- -+
As()
R
⋅+⋅
FB
Where:
R
sense
– is the equivalent output resistance determined by the droop function;
R
DROOP
–Z
(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied
P
------------------ -
R
g
RFB⋅=
load Ro;
–Z
(s) is the compensation network impedance;
F
(s) is the parallel of the two inductor impedance;
–Z
L
– A(s) is the error amplifier gain;
VIN∆
4
-- -
– · is the ACM PWM transfer function where ∆V
PWM
⋅=
5
------------------ -
∆
V
OSC
is the oscillator ramp amplitude
OSC
and has a typical value of 3V
Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop
gain results:
19/33
Page 20
L6919E
G
LOOP
s()
4
---
5
V
------------------ -
⋅⋅ ⋅–=
V
∆
IN
OSC
ZFs()
------------------------------------
s() ZLs()+
Z
P
ZPs()
Rs
------- -
---------------+
Rg
R
FB
With further simplifications, it results:
V
4
---
G
LOOP
s()
5
⋅⋅⋅ ⋅–=
------------------ -
V
∆
Considering now that in the application of interest it can be assumed that Ro>>R
R
<<Ro, it results:
DROOP
G
LOOP
s()
IN
OSC
4
---
5
ZFs()
-------------- -
R
V
------------------ -
⋅⋅⋅–=
V
∆
Ro R
------------------------------------- -
FB
ZFs()
IN
-------------- -
R
OSC
+
Ro
DROOP
R
------ -+
2
----------------------------------------------------------------------------------------------------------------------------------
L
s
----------------------------------------------------------------------------------------------------------------------------------
2
FB
s
Co
L
--- s
2
1sCoR
2
1sCoR
L
Co
--- s
2
--------------- Co ESR Co
2Ro⋅
--------------- Co ESR Co
2Ro⋅
DROOP
L
DROOP
L
ESR+()⋅⋅+
//Ro ESR+()⋅⋅+
; ESR<<Ro and
L
R
L
------ -
⋅+⋅+ 1+⋅+⋅⋅
2
R
L
-------
⋅+⋅+ 1+⋅+⋅⋅
2
The ACM control loop gai n is designed to obtain a high D C gain to m inimiz e static error and cros s the 0dB ax es
with a constant -20dB/dec slope with the desired crossover frequency
ωT. Neglecting the effect of ZF(s), the
transfer function has one zero and two poles. Both the poles are fixed onc e the output filter is des igned and the
zero is fixed by ESR and the Droop resistance.
To obtain the desired shape an R
series network is considered for the ZF(s) implementation. A zero at
F-CF
ωF=1/RFCF is then introduced together with an integrator. Thi s integrator minimizes the static error while placing
the zero in correspondence with the L-C resonance a simple -20dB/dec shape of the gain is assured (See Figure
15). In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower
than the above reported zero.Compensation network can be simply designed placing
the cross-over frequency
ωT as desired obtaining:
ωZ =
ωLC and imposing
RFBV
----------------------------------
R
F
∆⋅
V
IN
5
OSC
---
⋅⋅ ⋅= C
4
--------------------------------------------------------
ω
T
2R
L
DROOP
ESR+()⋅
F
--------------------=
Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right)
dB
K
V
4
IN
---
---------------
⋅⋅
5
V
∆
osc
1
----------
R
FB
dB
G
LOOP
ω
ω
Z
LC
VCOMP
PWM
F
Z
d••••V
IFB
R
C
F
F
RFB
REF
L/2
IN
Cout
ESR
VOUT
Rout
K
=
Co
R
⋅
F
ZF(s)
ω
L
---
2
T
ω
LAYOUT GUIDELINES
Since the device manages control functions and high -current driv ers, layout is one of the most imp ortan t things
20/33
Page 21
L6919E
to consider when designing such high current applications.
A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radi-
ation and a proper connection between signal and power ground can optimize the performance of the control
loops.
Integrated power drivers reduc e components count and interconnections betw een control functions and dri vers,
reducing the board space.
Here below are listed the main points to focus on when starting a new layout and r ules are suggested for a correct implementation.
■ Power Connections.
These are the c onnections wher e switching and continuous current fl ows from the input supp ly towards the load.
The first priority when placing components has to be reserved to this power section, minimizing the length of
each connection as much as possible.
To minimize noise and vol tage spikes (EMI and l osses) these inter connecti ons must be a part of a pow er plane
and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must
be located as close as possible, together and to the controller.
Considering that the "electrical" components repor ted in figure are composed by more than one "physical" component, a ground plane or "star" groundi ng connecti on is s uggested to mi nimize effects due to m ultiple c onnections.
Figure 16. Power connections and related connections l ayout guidelines (same for bo th phases)
HGATEx
PHASEx
LGATEx
PGNDx
SGN D
VIN
HS
R
gate
L
LS
R
gate
D
C
IN
C
a. PCB power and ground planes areas
BOOTx
PHASEx
VCC
C
BOOTx
+VCC
HS
LS
VCC
C
VIN
L
D
IN
C
C
b. PCB small signal components placement
OUT
OUT
LOAD
LOAD
Fig. 16a shows the details of the power conn ections invol ved and the current lo ops. The input capacitance ( CIN),
21/33
Page 22
L6919E
or at least a portion of the total capacitance needed, has to be placed close to the pow er section in order to
eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are required.
■ Power Connec tions Related.
Fig.16b shows some small signal components placement, and how and where to mix signal and power ground
planes. The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay
times as well as for the voltage spikes generated by the distributed inductance along the copper traces are so
minimized.
In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a consequence, the higher are the voltage spikes corresponding to the gate PWM rising and falling signals. Even if
these spikes are clamped by inherent internal diodes, propagation delays, noise and potential causes of instabilities are introduced jeopardizing good system behavior. One important consequence is that the switching
losses for the high side mosfet are significantly increased.
For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and the
GATEx and PHASEx traces walking together toward the high si de mosfet in order to minimi ze distanc e (see fig
17). In addition, since the PHASEx pin is the return path for the high side driver, this pin must be connected
directly to the High Side mosfet Source pin to have a proper driving for this mosfet.
For the LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if
implemented) or in the same way to the LS mosfets Source pin. GATEx and PHASEx connections (and also
PGND when no power ground plane is implemented) must also be designed to handle current peaks in excess
of 2A (30 mils wide is suggested).
Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system
efficiency.
Figure 17. Device orientation (left) and sense nets routing (right)
Towards HS mosfet
(30 mils wide)
To LS mosfet
(or sense resistor)
Toward s LS mosfet
(30 mils wide)
Towards HS mosfet
(30 mils wide)
To LS mosfet
(or sense resistor)
To regulated output
The placement of other components is also important:
– The bootstrap capacitor must be placed as clos e as possib le to the BOOT x and PHASEx pins to mini-
mize the loop that is created.
– Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins.
– Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capacitor
sustains the peak currents requested by the low-side mosfet drivers.
– Refer to SGND all the sensible components such as frequency set-up resistor (when present) and also
the optional resistor from FB to GND used to give the positive droop effect.
– Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation effect
and to ensure the right precision to the regulation when the remote sense buffer is not used.
22/33
Page 23
L6919E
– An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in reduc-
ing noise.
– PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be observed
on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device
can absorb energy and it can cause damages. The voltage spikes must be limited by proper layout, the
use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber network on the
low side mosfets, to a value lower than 26V, f or 20nSe c, at FSW of 600kHz max.
■ Current S ens e Connect io ns.
Remote Buffer:
pins to the load in order to compensate losses along the output power traces and also to avoid the pick-up of
any common mode noise. Connec ting these pi ns i n points far fr om the l oad, will cause a non-optimum load regulation, increasing output tolerance.
Current Reading:
order to limit the noise injection into the device. The PCB traces connecting these resistors to the reading point
must be routed as parallel traces in order to avoid the pick-up of any common mode noise. It's also important
to avoid any offset in the measurement and to get a better precision, to connect the traces as cl ose as possi ble
to the sensing elements, dedicated current sense resistor or low side mosfet R
Moreover, when using the low side mosfet R
nected to the PH ASEx p in. DO NOT CO NNECT TH E PINS TOG ETHER AND THEN T O THE HS SOU RCE!
The device won't work properly because of the noise generated by the return of the high side driver. In this case
route two separate nets: connect the PHASEx pin to the HS Source (route together with HGATEx) with a wide
net (30 mils) and the ISENx pin to the LS Drain (route together with PGNDSx). Moreover, the PGNDSx pin is
always connected, through the Rg resistor, to the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In
this case the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net).
Right and wrong connections are reported in Figure 18.
Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter.
The input connections for this components must be routed as parallel nets from the FBG/FBR
The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx pins in
.
dsON
as current sense element, the ISENx pin is practically con-
dsON
Figure 18. PCB layout connections for sense nets
NOT CORRECT
VIA to GND plane
ToPHASE
connection
Wrong (left) and correct (right) connections for the current reading sensing nets.
CORRECT
To LS Dr ain
and Source
To HS Gate
and Source
23/33
Page 24
L6919E
Demo Board Description
The L6919E demo board shows the operation of the device in a dual phase application. This evaluation board
allows output voltage adjustability (0.800V - 1.550V) through the switches S0-S4 and high output current capability.
The board has been laid out with the possi bility to use up to two D
to give maximum flexibility in the mosfet choice.
The four layers demo board's copper thickness is of 70
µ
m in order to minimize conduction losses considering
the high current that the circuit is able to deliver.
Demo board schematic circuit is reported in Figure 19.
Figure 19. Demo Board Schematic
Vin
GNDin
GNDcc
Vcc
JP6
S4
S3
S2
S1
S0
DZ1
JP1
D4
C5
L1
D1
Q1a Q3a
To pin
VCC
R21
JP2
R16
Q2 C4
Q1
VCCDR
C8
R15
R18
R13
R6
R5
R2
2
BOOT1
5
UGATE1
4
PHASE1
3
LGATE1
1
ISEN1
13
14
L6919E
22
21
20
19
18
17
7
11
FBR
U1
PGNDS1
VID4
VID3
VID2
VID1
VID0
OSC / INH
SGND
VCC
6
BOOT2
24
UGATE2
25
PHASE2
26
LGATE2
27
ISEN2
16
PGNDS2
15
PGND
28
PGOOD
23
VSEN
10
FB
9
COMP
8
12
FBG
2
PACK mosfets for the low side sw itch in order
C11..C13
R11
D3
Q4 C3
Q3
D2
C7
R14
R17
R12
R3
R4
R10
C24
JP3
C1
R9
R7
R8
C2
C9,C10
C6
L2
R19
C14,
C23
R1
R20
VoutCORE
GNDCORE
PGOOD
JP5
JP4
FBG
FBR
Several jumpers allow setting different configurations for the device: JP3, JP4 and JP5 allow configuring the
remote buffer as desired. Simply shorting JP4 and JP5 the remote buffer is enabled and it senses the output
voltage on-board; to implement a real remote sense, leave these jumpers open and connect the FBG and FBR
connectors on the demo board to the remote load. To avoid usi ng the remote buffer, simpl y short all the jumpers
JP3, JP4 and JP5. Local sense through the R7 is used for the regulation.
The input can be configured in different ways using the jumpers JP1, JP2 and JP6; these jumpers control also
the mosfet driver supply v oltage. Anyway, power c onversion star ts from V
and the device is suppl ied from V
IN
CC
(See Figure 20).
Figure 20. Power supply conf i gu ra ti on
24/33
Vin
GNDin
Vcc
GNDcc
To Vcc pin
JP6
DZ1
JP1
JP2
To HS Drains (Power Input)
To BOOTx (HS Dr iver Supply)
To VCCDR pin (LS Driver Supply)
Page 25
L6919E
VCCDR (LS Supply) = 12V
Two main configurations can be distinguished: Single Supply (VCC=VIN=12V) and Double Supply (VCC=12V
VIN=5V or different).
– Single Supply: In this case JP6 has to be completely shorted. The device is supplied with the same rail
that is used for the conv ersion. With an addition al zener diod e DZ1 a lo wer volta ge can be derived t o
supply the mosfets dr iv er if Logic level mosfet ar e us ed. In this case JP1 must be lef t open so that the
HS driver is supplied with V
the right to use V
and JP2 can be freely shorted in one of the two positions .
– Double Supply: In this cas e VCC suppl y directl y the contr oller (12 V) while V
for the power conversion. This last one can start indifferently from the 5V bus (Typ.) or from other buses
allowing maximum flexibility in the power conversion. Supply for the mosfet driver can be programmed
through the jumpers JP1, JP2 and JP6 as previously illustrated. JP6 selects now V
on the requirements.
Some examples are reported in the following Figures 21 and 22.
Figure 21. Jumpers configuration: Double Supply
IN-VDZ1
IN-VDZ1
to supply the LS driver through VCCDR pin. Othe rwi s e, JP 1 must be shorted
through BOOTx and JP2 must be shorted to the left to use VIN or to
supplies the HS dr ains
IN
or VIN depending
CC
Vin = 5V
JP6
GNDin
Vcc = 12V
GNDcc
Vin = 5V
GNDin
Vcc = 12V
GNDcc
Figure 22. Jumpers configuration: Single Supply
Vin = 12V
GNDin
Vcc = Open
JP6
JP6
(a) V
(b) V
= 12V; V
CC
= V
CC
DZ1
DZ1
BOOTx
DZ1 6.8V
Vcc = 12V
HS Drains = 5 V
JP2
HS Supply = 5V
VCCDR (LS Supply) = 5V
Vcc = 12V
HS Drains = 5 V
HS Supply = 12V
Vcc = 12V
HS Drains = 1 2V
HS Supply = 5.2V
VCCDR (LS Supply) = 12V
JP2
JP1
= VCCDR = VIN = 5V
BOOTx
JP2
JP1
= VCCDR = 12V; VIN = 5V
JP1
GNDcc
Vin = 12V
GNDin
Vcc = Open
GNDcc
(a) VCC = VIN = VCCDR = 12V; V
JP6
DZ1
JP1
JP2
= 5.2V
BOOTx
Vcc = 12V
HS Drains = 1 2V
HS Supply = 12V
VCCDR (LS Supply) = 12V
(b) V
= VIN = V
CC
= VCCDR = 12V
BOOTx
25/33
Page 26
L6919E
PCB AND COMPONENT LAYOUT
Figure 23. PCB and Components Layouts (Dimensions: 10.8mm x 8.2mm)
Component Side
Internal PGND Plane
26/33
Internal SGND Plane
Solder Side
Page 27
L6919E
CPU Power Supply: 5 to 12VIN; 1.2V
OUT
; 45A
DC
Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast
reaction, this helps in reducing output and input capacitor. Inductance value is also reduced.
A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compensation network. Considering the high output current, power conversion will start from the 12V bus.
– Current Reading Network and Over Current:
Since the maximum output current is I
= 45A, the over current threshold has been set to 45A (22.5A
MAX
x 2)in the worst case (max mosfet temperature). Since the device limits the valley of the triangular ripple
across the inductors, the current ripple mus t be considered too. Consid ering the inductor core satur a-
tion, a curren t ripple of 10A has t o be consider ed so that the OCP t hreshold in worst cas e becomes
OCPx=17A (22.5A-5A). Considering to sense the output current across the low-side mosfet RdsON,
SUB85N03L-04P has 4.3m
Ω max at 25°C that becomes 5.6mΩ at 100ºC considering the temperature
variation; the resulting transconductance resistor Rg has to be:
Rg I
⋅ 17
OCPx
R
dsON
----------------- -
35µ
5.6m
-------------
⋅ 2.7kΩ (R3 to R6)===
35
µ
– Droop function Desi gn:
Considering a voltage drop of 70mV at full load, the feedback resistor R
R
70mV
---------------- 1k Ω (R7)==
FB
70
µA
has to be:
FB
– Inductor desig n:
Transient respons e performance needs a compro mi se in th e induc tor choice value: t he biggest the in-
ductor, the highest the efficient but the worse the transient response and v ice ve rsa.
Considering then an inductor value of 0.8
µH, the current ripple becomes:
Vin Vout–
---------------------------- -
I∆
L
-----------
⋅
Fsw
d
12 1.2–
-------------------- -
0.8µ
1.2
1
------- -
------------ -
⋅⋅ 6.5A (L1, L2)== =
12
200k
– Output Capacitor :
Five Rubycon MBZ (2200
2.4m
Ω resulting in an ESR voltage drop of 45A · 2.4mΩ = 108mV after a 45A load transient.
µF / 6.3V / 12mΩ max ESR) has been used implementing a resulting ESR of
– Compensation Netw ork :
A voltage loop bandwidth of 20kHz is con sider ed to let the device fast react after load transient .
The R
R
F
network results:
F CF
R
∆⋅
IN
5
-- -
ω
⋅⋅ ⋅
T
4
FBVOS
------------------------------
V
-------------------------------------------------------
2R
L
DROOP
C
F
ESR+()⋅
Co
⋅
------------------- -
R
F
1K 2⋅
---------------
L
-- -
2
---------------------------------------- - 33nF== =
5
-- -
12
20 K 2Π
4
62200µ
2k
⋅⋅
1µ
------ -
2
---------------------------------------------------------------
⋅⋅⋅⋅
2
⋅
0.8 µ
5.6m
-------------
2.7
1.2k 2.4m+⋅
(R8)
2.0kΩ== =
(C2)
Further adjustments can be done on the work bench to fit the requirements and to compensate layout parasitic
components.
27/33
Page 28
L6919E
Part List
R2 147k 1% SMD 0805
R1, R20,R21 Not Mounted SMD 0805
R3, R4, R5, R6 2.7k 1% SMD 0805
R7 1k 1% SMD 0805
R8 1.8k SMD 0805
R9 47k 1% SMD 0805
R10 510 SMD 0805
R11 82 SMD 0805
R12 to R19 0 SMD 0805
C1 Not Mounted SMD 0805
C2 22n SMD 0805
C3, C4 100n SMD 0805
C5, C6, C7, C8 1
C9, C10 10
C11 to C13 1800
C14 to C18 2200
C24 100n SMD 0805
µ
µ
or 22µ / 16V TDK Multilayer Ceramic SMD 1206
µ
/ 16V Rubycon MBZ Radial 10x23
µ
/ 6.3V Rubycon MBZ Radial 10x20
Ceramic SMD 1206
L1, L2 0.8
µ
77121 - 4Turns
U1 L6919E STMicroelectronics SO28
2
Q1, Q3 SUB85N03-04P Vishay D
Q2, Q4 SUB70N03-09BP Vishay D
PACK
2
PACK
D1, D2 STPS340U STMicroelectronics SMB
D3, D4 1N4148 STMicroelectronics SOT23
S0,S4 Short
S1,S2,S3 Open
STATIC PERFORMANCES
Figure 24 shows the demo board measured efficiency versus load current in steady state conditi ons without airflow at ambient temperature.
Figure 24. System Efficiency
90
85
80
75
70
65
Efficiency [%]
60
55
50
0 5 10 15 20 25 30 35 40 45
Output Current [A]
28/33
Page 29
L6919E
Figure 25 shows the mosfets temperature versus output current in steady state condition without any air-flow
or heat sink. It can be observed that the mosfets are under 100ºC in any conditions. Load regulation is also reported from 10A to 45A.
Figure 25. Mosfet Temperature and Load Regulation
100
90
C]
o
80
70
60
50
40
MOS Temperatur e [
30
20
0 5 10 15 20 25 30 35 40 45
High-side MOS Q2
High-side MOS Q4
Low-side MOS Q1
Low-side MOS Q3
Output Current [A]
1.250
1.240
1.230
1.220
1.210
1.200
Vout [V]
1.190
1.180
1.170
0 5 10 15 20 25 30 35 40 45
Output Current [A]
DYNAMIC PERFORMANCES
Figure 26 shows the system response to a load transient fr om 3A to 45A. The output voltage is contained i n the
±50mV range. Additional output capacitors can help in reducing the initial voltage spi ke mainly due to the ESR.
Figure 26. 3A to 45A Load Transient Response
Figure 27 sh ows t he syst em respon se t o a VID transient fro m 1.2 00V to 0.800 V and vice v ersa at min imum load (3A).
Figure 27. Dynamic VID Response
29/33
Page 30
L6919E
DEMO BOARD ENHANCEMENTS: 1.200V / 52A CPU Power Supply
Considering the same application schematic, minor changes can be done to achieve the 52A thermal output
current required by AMD Hammer processor core. Part list has been modified as follow:
Part List
R2 147k 1% SMD 0806
R1, R20,R21 Not Mounted SMD 0805
R3, R4, R5, R6 1.5k 1% SMD 0805
R7 1k 1% SMD 0805
R8 1.8k SMD 0805
R9 47k 1% SMD 0805
R10 510 SMD 0805
R11 82 SMD 0805
R12 to R19 0 SMD 0805
C1 Not Mounted SMD 0805
C2 10n SMD 0805
C3, C4 100n SMD 0805
C5, C6, C7, C8 1
C9, C10 10
C11 to C13 1800
C14 to C18 2200
C24 100n SMD 0805
µ
µ
or 22µ / 16V TDK Multilayer Ceramic SMD 1206
µ
/ 16V Rubycon MBZ Radial 10x23
µ
/ 6.3V Rubycon MBZ Radial 10x20
Ceramic SMD 1206
L1, L2 0.8
µ
77121 - 4Turns
U1 L6919E STMicroelectronics SO28
Q1, Q1a, Q3, Q3a SUB85N03-04P Vishay-Siliconix D
Q2, Q4 SUB70N03-09BP Vishay-Siliconix D
2
PACK
2
PACK
D1, D2 STPS340U STMicroelectronics SMB
D3, D4 1N4148 STMicroelectronics SOT23
S0,S4 Short
S1,S2,S3 Open
STATIC PERFORMANCES
Figure 28 shows the demo board measured efficiency versus load current in steady state conditi ons without airflow at ambient temperature.
Figure 28. System Efficiency
90
85
80
75
70
65
60
Effici ency [%]
55
50
45
40
0 5 10 15 20 25 30 35 40 45 50 55 60
Output Current [A]
30/33
Page 31
L6919E
Figure 29 shows the mosfets temperature versus output current in steady state condition without any air-flow
or heat sink. It can be observed that the mosfets are under 105°C in any conditions. Load regulation is also reported from 10A to 55A.
Figure 29. Mosfet Temperature and Load Regulation.
115
105
C]
o
95
85
75
65
55
45
MOS Temperature [
35
25
High-side M OS Q2
High-side M OS Q4
Low-side M OS Q1
Low-side M OS Q3
0 5 10 15 20 25 30 35 40 45 50 55 60
Output Current [A]
1.235
1.225
1.215
1.205
1.195
Vout [V]
1.185
1.175
1.165
1.155
0 5 10 15 20 25 30 35 40 45 50 55 60
Output Current [A]
Figure 30 shows the system response to a load transient fr om 3A to 45A. The output voltage is contained i n the
±50mV range. Additional output capacitors can help in reducing the initial voltage spi ke mainly due to the ESR.
Figure 30. 3A to 45A Load Transient Response
Figure 31 sh ows t he syst em r esponse t o a VI D trans ient f rom 1. 200V to 0 .800V and vi ce ver sa at mi nimum load ( 3A).
Figure 31. Dynamic VID Response
31/33
Page 32
L6919E
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.1 0.3 0.004 0.012
b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.013
C 0.5 0.020
c1 45° (typ.)
D 17.7 18.1 0.697 0.713
E 10 10.65 0.394 0.419
e 1.27 0.050
e3 16.51 0.65
F 7.4 7.6 0.291 0.299
L 0.4 1.27 0.016 0.050
S8° (max.)
mm inch
OUTLINE AND
MECHANICAL DATA
SO28
32/33
Page 33
L6919E
Information furnish e d is believed to be accura te and relia ble. Ho weve r, ST Microe lectr onic s assu mes no respon sibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grant ed
by impli cation o r otherwi se under any patent or pat ent rights of STMicroelectronic s. Specificati ons mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems wi thout express written approval of STMi croelec tronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the propert y of their respective ow ners
© 2003 STMi croelect ronics - All rights r eserved
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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
STMicroelectronics GROUP OF COMPANIES
www.st.com
33/33
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