Datasheet L6911E Datasheet (ST)

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5 BIT PROGRAMMABLE STEP DOWN CONTROLLER

■

OPERATING SUPPL Y IC VOLTAGE FROM 5V
TO 12V BUSES

■

UP TO 1.3A GATE CURRENT CAPABILITY

■

TTL-COMP A T I BLE 5 BIT P ROGR AMMABLE
OUTPUT CO MPLIANT WITH VRM 8.5 :

1.050V TO 1.825V WITH 0.025V BINARY
STEPS

■

VOLTAGE MODE PWM CONTROL

■

EXCELLENT OUTPUT ACCURACY: ±1%
OVER LINE AND TEMPERATURE
VARIATIONS

■

VERY FAST LOAD TRANSIENT RESPONSE:
FROM 0% TO 100% DUTY CYCLE

■

POWER GOOD OU T PUT VO LTA GE

■

OVERVOLTAGE PROTECTION AND
MONITOR

■

OVERCURRENT PROTECTION REALIZED
USING THE UPPER MOSFE T'S R d sON

■

200KHz INTERNAL OSCILLATOR

■

OSCILLATOR EXTERNALLY ADJUST ABLE
FROM 50KHz TO 1MHz

■

SOFT START AND INHIBIT FUNCTIONS

APPLICATIONS

■

POWER SUPPLY FOR ADVANCED
MICROPROCESSOR CORE

■

DISTRIBUTED PO WE R SUPP LY

L6911E

WITH SYNCHRONOUS RECTIFICATION

SO-20

ORDERING NUMBERS: L6911E

DESCRIPTION

The device is a power supply controller specifically
designed to provide a high performance DC/DC con­version for high cur rent m icr oprocess ors. A precis e 5
bit digital to analog converter (DAC) allows to adjust
the output voltage from 1.050 to 1.825 with 25mV bi­nary steps.

The high precision internal r eference ass ures the se­lected output voltage to be within ±1%. The high peak
current gate drive affords to have fast switching to the
external power mos providing low switching losses.

The device assures a fast protection against load
overcurrent and load over-voltage. An external SCR
is triggered to crowbar the input supply in case of
hard overvoltage. An internal crowbar is also provid­ed turning on the low side mosf et as long as the over­voltage is detected. In case of ove r-current detection,
the soft start capacitor is discharged an the system
works in HICCUP mode.

L6911ETR

(Tape and Reel)

BLOCK DIAGRAM

November 2001

PGOOD

OVP

VD0
VD1
VD2
VD3
VD4

D98IN957

Vcc 5V to12V

VCC OCSET

SS

RT

D/A

MONITOR and
PROTECTION

OSC

+

­E/A

COMP

­+

PWM

BOOT

UGATE

PHASE

LGATE

PGND

GND

VSEN

VFB

Vin 5V to12V

1.050V to 1.825V

Vo

1/20

L6911E

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Vcc Vcc to GND, PGND 15 V

V

BOOT-VPHASE

V

HGATE-VPHASE

PIN CONNECTION

Boot Voltage 15 V

15 V
OCSET, PHASE, LGATE -0.3 to Vcc+0.3 V
ROSC, SS, FB, PGOOD, VSEN 7 V
COMP, OVP 6.5 V

VSEN

OCSET

SS/INH

VID0
VID1
VID2
VID3
VID4

COMP PGOOD

FB GND

2
3
4
5
6
7
8
9
10

D98IN958

20
19
18
17
16
15
14
13
12
11

RT1
OVP
VCC
LGATE
PGND
BOOT
UGATE
PHASE

THERMA L D ATA

Symbol Parameter Value Unit

Rth j-amb Thermal Resistance Junction to Ambient 110 °

Tmax Maximum junction temperature 150 °

Tstorage Storage temperature range -40 to 150 °

2/20

T

J

Junction temperature range 0 to 125 °

C / W

C
C
C

L6911E

g

g

g

g

g

PIN FUNCTION

N Name Description

1 VSEN Connected to the output voltage is able to manage over-voltage conditions and the PGOOD signal.
2 OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection.

The internal 200µA current
The Over-Current threshold is due to the followin

enerator sinks a current from the drain through the external resistor.

equation:

I

I

------------------------------------------------=

P

Þ

OCSETROCSET

R

DSon

3 SS/INH

The soft start time is pro
internal current

enerator forces through the capacitor 10µA.

rammed connecting an external capacitor from this pin and GND. The

This pin can be used to disable the device forcing a voltage lower than 0.4V

4 - 8 VID0 - 4 Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They are

used to program the output voltage as specified in Table 1 and to set the overvoltage and power
good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.

9 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control

feedback loop.

10 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage

control feedback loop.
11 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
12 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above

specified threshlds.

If not used may be left floating.
13 PHASE This pin is connected to the source of the upper mosfet and provides the return path for the high side

driver. This pin monitors the drop across the upper mosfet for the current limit.
14 UGATE High side gate driver output.
15 BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet.

Connect through a capacitor to the PHASE pin and through a diode to Vcc (catode vs boot).
16 PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to

reduce the noise injection into the device
17 LGATE This pin is the lower mosfet gate driver output
18 VCC Device supply voltage. The operative supply voltage range is from 4.5 to 12V.

DO NOT CONNECT V

TO 12V IF VCC IS 5V.

IN

19 OVP Over voltage protection. If the output voltage reach the 15% above the programmed voltage this pin

is driven high and can be used to drive an external SCR that crowbar the supply voltage.

If not used, it may be left floating.
20 RT Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the external

frequency is increased according to the equation:

6

510

⋅

f

S

200kHz

--------------------+=

R

kΩ()

T

Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to the

equation:

7

410

f

S

200kHz

--------------------–=

R

⋅

kΩ()

T

If the pin is not connected, the switching frequency is 200KHz.

The volta

e at this pin is fixed at 1.23V. Forcing a 50µA current into this pin, the built in oscillator

stops to switch.

3/20

L6911E

ELECTRICAL CHARACTERISTIC

(Vcc=12V; T=25°C unless otherwise specified)

Symbol Parameter Test Condition Min Typ Max Unit

Vcc SUPPLY CURRENT

Icc Vcc Supply current UGATE and LGATE open 5 mA

POWER-ON

Turn-On Vcc threshold V
Turn-Off Vcc threshold V
Rising V

threshold 1.26 V

OCSET

= 4.5V 4.6 V

OCSET

= 4.5V 3.6 V

OCSET

Iss Soft Start Current 10 µ

OSCILLATOR

Free running frequency RT = OPEN 180 200 220 KHz

∆

Vosc

Total Variation

6 KΩ< R

to GND <200 K

T

Ramp amplitude RT = OPEN 1.9 Vp-p

Ω -15 15 %

REFERENCE AND DAC

DACOUT Voltage
Accuracy

VID0, VID1,VID2, VID3,
VID25mV see Table1;Tamb=0 to

-1 1 %

70°C

VID Pull-Up voltage 3.1 V

ERROR AMPLIFIER

DC Gain 88 dB

GBWP G ain-Bandw idth Produ ct 15 MHz

SR Slew-Rate C OMP= 10pF 10

GATE DRIVERS

I

UGATE

R

UGATE

I

LGATE

High Side Source
Current

High Side Sink
Resistance

Low Side Source

- V

V

BOOT

V

- V

UGATE

V

BOOT-VPHASE

I

= 300mA

UGATE

Vcc=12V, V

PHASE

PHASE

LGATE

=12V,

= 6V

=12V,

= 6V

1 1.3 A

24Ω

0.9 1.1 A

Current

R

LGATE

Low Side Sink

Vcc=12V, I

LGATE

= 300mA

1.5 3 Ω

Resistance
Output Driver Dead Time PHASE connected to GND 120 nS

PROTECTIONS

Over Voltage Trip (V

SEN

/

V

Rising 117 120 %

SEN

DACOUT)

I

OCSET

I

OVP

OCSET Current Source V
OVP Sourcing Current V

= 4.5V 170 200 230 µ

OCSET

> OVP Trip, V

SEN

=0V 60 mA

OVP

POWER GOOD

V

Rising 108 110 112 %

SEN

V

Falling 88 90 92 %

SEN

Upper and Lower threshold 2 %

= -5mA 0.5 V

PGOOD

V

PGOOD

Upper Threshold

/DACOUT)

(V

SEN

Lower Threshold
(V

/DACOUT)

SEN

Hysteresis
(V

/DACOUT)

SEN

PGOOD Voltage Low I

A

V/µS

A

4/20

Table 1. VID Setting

VID4

(25mV)

VID3 VID2 VID1 VID0

00100
10100
00011
10011
00010
10010
00001
10001
00000
10000
01111
11111
01110
11110
01101
11101

Output

Voltage (V)

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

VID4

(25mV)

VID3 VID2 VID1 VID0

01100
11100
01011
11011
01010
11010
01001
11001
01000
11000
00111
10111
00110
10110
00101
10101

L6911E

Output

Voltage (V)

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

Device Description

The device is an i ntegrated circuit r ealized in BCD technol ogy. It provides c omplete control logic and protections
for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed
to drive N Channel Mosfets in a synch ronou s-rectified buc k topology . The devic e works proper ly with V cc rang­ing from 5V to 12V and regulates the output voltage starting from a 1.26V power stage s upply voltage (Vin). The
output voltage of the converter can be precisely regulated, programming the VID pins, from 1.050V to 1.825V
with 25mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The
device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator
that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/
ms slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty
cycle ranges from 0% to 100%. The device protects against over -curr ent condi tions entering in H ICCUP mode.
The device moni tors the curr ent by us ing the r

of the upper MOSFET which eliminates the need for a cur-

DS(ON)

rent sensing resistor.
The device is available in SO20 package.

Oscillator

The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant c urrent an internal capacit or. The current deliver ed to the
oscillator is tipically 50

µ

A (Fsw=200KHz) and may be v ari ed usi ng an external r esistor ( RT) connected between
RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied
proportionally to the current sinked (forced) from (into) the pin.

In particular connecting it to GND the frequency is increased (current is sinked from the pin), according to the
following relationship:

6

⋅

4.94 10

f

S

200kHz

-------------------------+=

Ω()

R

k

T

Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according
to the following relationships:

5/20

L6911E

f

S

f

S

200kHz

200kHz

⋅

4.306 10

---------------------------- -+=

R

k

T

⋅

15 10

--------------------+=

R

k

T

Ω()

Ω()

7

V

7

V

CC

CC

= 12V

= 5V

Switching frequency variations vs. R

µ

Note that forcing a 50

A current into this pin, the device stops switching because no current is delivered to the

are reported in Fig.1.

T

oscillator.

Figure 1.

10000

1000

100

Resistance [kOhm ]

10

10 100 1000

R T to G ND
R T to VCC= 1 2V
R T to VCC= 5 V

Frequency [kHz]

Digital to Analog Converter

The built-in digital to analog converter allows the adjustment of the output voltage from 1.050V to 1.825V with
25mV binary steps as shown in the previous table 1. The internal reference is trimmed to ensure the precision
of 1%.

The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These
are TTL compatible inputs of an internal D AC that is realised by means of a series of resistors rpoviding a par­tition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precis e
point of the divider. The D AC output i s del ivered to an amplifier obtaining the VPROG voltage referenc e ( i.e. the
set-point of the error amplifier). Internal pull-ups are provided (realized with a 5

µ

A current generator); in this
way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short
the pin to GND.

The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over­voltage protection (OVP) thresholds.

Soft Start and Inhibit

At start-up a ramp is generated charging the external capacitor CSS by means of a 10µA constant current, as
shown in figure 2.

When the voltage across the soft start capacitor (V
charge the output capacitor. As V

6/20

reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper

SS

) reaches 0.5V the lower power MOS is turned on to dis-

SS

L6911E

MOS begins to switch and the output voltage starts to increase.
The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly in-

creases, as shown in figure 2. In this phase the system works in open loop. When VSS is equal to VC OMP the
clamp on the output of the error amplifier is released. In any case another clamp on the non-inverting input of
the error ampli fier remains active, all owing to VOUT to grow with a low er slope ( i.e. the slop e of the V SS voltage,
see figure 2). In this second phase the system works in closed loop with a growing r eference. As the output
voltage reaches the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft
start finishes. Vss increases until a maximum value of about 4V.

The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins
are not above their own Turn-On thresholds; in this way the device starts switching only if both the power sup­plies are present. During normal operation, if any under-voltage is detected on one of the two supplies, the SS
pin is internally shorted to GND and so the SS capacitor is rapidly discharged.

The device goes in INHIBIT state forcing SS pin below 0.4V. In this conditi on both external MOSFETS are kept
off.

Figure 2. Soft Start

Vcc

Vin

Vss

LGATE

Vout

to GND

Vcc Tu rn-on thresh o l d

Vin Turn-on threshold

1V

0.5V

Timing Diagram

Aquisition: CH1 = PHASE; CH2 = V
CH3 = PGOOD; CH4 = V

SS

OUT

;

Driver Section

The driver capability on the high and low side drivers allows to use different types of power MOS (also multiple
MOS to reduce the R

), maintaining fast switching transition.

DSON

The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use many kinds of mos-

fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the
low side turn-off.

The peak current is shown for both the upper (fig. 3) and the lowr (fig. 4) dr iver at 5V and 12V. a 4nF capaciti ve
load has been used in these measurements.

For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak
current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V.

Similary, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ Vboot­Vphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase =5V.

7/20

L6911E

Figure 3. Hi gh Side dr iver peak curr e nt.
Vboot-Vphase=12V (left) Vboot-Vphase=5V (right) CH1 = High Side Gate CH4 = Inductor Current

Figure 4. Low Side driver peak curren t.
Vcc=12V (left) Vcc=5V (right)CH1 = Low Side Gate CH4 = Inductor Current

Monitor and Protection

The output voltage is monitored by means of pin 1 (VSEN). If it is not w ithin ±10% (typ.) of the programm ed
value, the powergood output is forced low.

The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) greater than
the nominal one. If the output voltage exc eed this threshold, the OVP pin is for ced high (5V) and the lower dr iver
is turned on as long as the over-voltage is detect ed. The OVP pin is capable to deliv er up to 60mA (min) in order
to trigger an external S CR connected to burn the input fuse. The low-side mosfet tur n-on implement thi s function
when the SCR is not used and helps in keeping the ouput low .

To perform the overcurrent protection the device compares the drop across the high side MOS, due to its
RDSON, with the voltage across the external resistor (R
the upper MOS. Thus the overcurrent threshold (I

where the typical value of I
To calculate the R

value it must be considered the maximum R

OCS

and the minimum value of I

is 200µA.

OCS

. To avoid undesirable trigger of overcurrent protection this relation ship must be

OCS

) can be calculated with the following relationship:

P

I

OCSROCS

I

--------------------------------=

P

) connected between the OCSET pin and drain of

OCS

⋅

R

DSON

(also the variation with temperature)

DSON

satisfied:

8/20

L6911E

∆

l

=

---- -+≥

IPI

OUTMAX

∆

where

I is the inductance ripple current and I

OUTMAX

is the maximum output current.

In case of output short circuit the soft start capacitor is discharged with constant current (10
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al­ways active and if such kind of event occours, the device turns off both mosfets, and the SS capacitor is di­charged again after rea ching the upper threshold of about 4V. The system is now working in HICCUP mode, as
shown in figure 5a. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.

Figure 5.

I

PEAK

2

µ

A typ.) and when

a: Hiccup Mode

9
8
7
6
5
4
3
2

Inductor Ripple [A]

1
0

0.5 1.5 2.5 3.5

Output Voltage [V ]

b: Indu ctor Ripple Cur rent vs. Vout

L=1.5µH, Vin=12V

L=3µH, Vin=5V

L=2µH,
Vin=12V

L=3µH,
Vin=12V

L=1.5µH,
Vin=5V

L=2µH,
Vin=5V

Inductor design

The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current

∆

IL between 20% and 30% of the maximum output current. The inductance value can be cal-

culated with this relationship:

L

V

INVOUT

------------------------------

=

f

sIL

–

V

OUT

--------------

⋅

∆⋅

V

IN

Where f

is the switching frequency, VIN is the input voltage and V

SW

is the output voltage. Figure 5b shows

OUT

the ripple current vs. the output voltage for different values of the inductor, with vin=5V and Vin=12V.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter

response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging tim e, the output cur ­rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.

The response time to a load transient is different for the application or the removal of the load: if during the ap­plication of the loa d the inductor is c harged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx­imate response time for

∆

I load transient in case of enough fast compensation network response:

9/20

L6911E

t

applicatio n

⋅

L∆I

----------------------------- -=
–

V

INVOUT

t

removal

⋅

L∆I

-------------- -=

V

OUT

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response ti me after r emoval o f the load with the minimum output voltage programmed and the max­imum input voltage available.

Output Capacitor

Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the
range of tenth A/

µ

sec, the output capacitor is a basic component for the fast response of the power supply. In
fact for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.

The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):

∆

V

OUT

= ∆I

OUT

· ESR

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:

2

∆

I

L

OUT

–⋅()⋅⋅

Where D

∆

V

OUT

is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop

MAX

---------------------------------------------------------------------------------------------=

2C

OUTVINMINDMAXVOUT

during load transient and the lower is the output voltage static ripple.

Input Capacitor

The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:

I

rmsIOUT

–()⋅=

D1D

Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:

2

P ESR I

⋅=

rms

Compensation network design

The control loop is a voltage mode (figure 7) that uses a dr oop function to satisfy the requirements for a VRM
module, reducing the size and the cost of the output capacitor.

This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de­pendence of the output voltage on the load current: at light load the output voltage will be higher than the nom­inal level, while at high load the output voltage will be lower than the nominal value.

10/20

L6911E

Figure 6. Output transient response without (a) and with (b) the droop function

ESR DROP ESR DROP

V

MAX

V

V

NOM

V

MIN

(a) (b)

As shown in figure 6, the ESR drop is pr esent in any c ase, but using the droop func tion the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor­tional to the output current. Since a sense resistor is not present, the output DC current is measured by using
the intrinsic resistance of the inductance (a few m

Ω

). So the low-pass filtered inductor voltage (that is the induc­tor current) is added to the feedback signal, implementing the dr oop function in a simple way. Referring to the
schematic in figure 7, the static characteristic of the closed loop system is:

⋅

R

V

OUT

V

PROGVPROG

+

R3 R8 // R9

-------------------------------------

R2

R 8 // R9

L

---------------------------------- -

R8

⋅–⋅+=

I

OUT

DROOP

Where V

is the output voltage of the di gital to ana log conv erter (i .e. the set po int) and RL is the inductance

PROG

resistance. The second term of the equation allows a positive offset at zero load (
the droop effect (

∆

V

). Note that the droop effect is equal the ESR drop if:

DROOP

⋅

R8 // R9

R

L

---------------------------------- -

R8

=

ESR

Figure 7. Compensatio n ne tw o rk

IN

V

V

COMP

C18

PWM

Z

F

C20 R4

R3

PROG

V

R2

V

PHASE

Z

I

L2

R8

R9

C25

∆

V+); the third term introduces

L

R

OUT

V

ESR

C6-15

Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired
droop effect as follow:

■

Choose a value for R2 in the range of hundreds of KΩ to obtain realistic values for the other
components.

11/20

L6911E

)43(

■

From the above equations, it results:

R8

=

R9 R8

+

∆

⋅

V

R2

-----------------------

V

PROG

∆

V

DROOP

-------------------------- -

⋅⋅

⋅

R

LIMAX

⋅

R

LIMAX

-------------------------- -

⋅=

∆

V

DROOP

1

------------------------------------ -

∆

V

DROOP

-------------------------- -+

1

⋅

R

LIMAX

;

;

Where I

■

The component R3 must be chosen in order to obtain R3<<R8//R9 to permit these and successive

is the maximum output current.

MAX

simplifications.

Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output
impedance is equal to a resistance R

. It is easy to verify that the output voltage deviation under load tran-

OUT

sient is minimum when the output impedance is constant with frequency.
To choose the other components of the compensation network, the transfer function of the voltage loop is con-

sidered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9).

Figure 8. Compensatio n ne tw o rk def i ni t io n

|Av |

2

|R|

R

|Glo op |

G

LC

f

0

D

f

0

2

f

CE

f

1

f

ECfCC

f

3

f

f

f

fc

f

CRfingularityonNetworkSCompensati

⋅⋅=

π

fingularityConverterS

LC

f

CE

f

EC

f

CC

⋅=

π

2/1

CESR

⋅⋅=

π

2/1

π

2/1

π

2/1

OUT

⋅⋅=

⋅⋅=

doublepoleLC
ESRzero

1

2/1

2

byIntroducedCceramicESR

acitorCeramicCapCceramicRceramic

3

f

d

2042/1

CRRf

π
π

π

⋅+⋅=

20

CRf

⋅⋅=

2532/1

CRd

⋅⋅=

252/1

The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later,
this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this as­sumption, the voltage loop has the following transfer function:

12/20

Gloop s()Av s()Rs

()⋅

()

Av s

()

Zf s

------------- -

⋅==

()

Zi s

Where

()

Av s

Vin

--------------- -

∆

V

osc

()

s

Z

C

------------------------------------ -

⋅=

s()ZLs

Z

C

L6911E

()+

Where Z
The expression of Z

Where:

(s) and ZL(s) are the output capacitor and inductor impedance respectively.

C

(s) may be simplified as follow:

I

==

()

s

Z

I

τ

= R4×C20,

1

1

-- -

⋅⋅

Rd

--------------------------------- -

Rd

C25

s

1

-- -+

⋅

C25

s

τ

= (R4+R3)×C20 and

2

1



-- -

R4



----------------------------------------------------- -+



R4



⋅+

s

1

-- -

⋅+

s

=

Rd

⋅

C20

C20




-------------------------------------------------------------------- -

R3

+

R3

------- - τ

1s

R

1s

τ

= Rd×C25.

d

R3

⋅+

d

⋅+()

τ

2



Rd 1 s



-------------------------------------------------------------------------------------------------- -

⋅+()⋅

1s

d

τ

⋅+()⋅

1s

τ

1τd

1s

τ

1

d

+()

⋅+()

τ

2

2

R3

------- -

⋅⋅⋅+⋅+

s

1s

R

⋅+()⋅

d

τ

d

τ

1τd

=

The regulator transfer function became now:

()

Rs

------------------------------------------------------------------------------------------------------- -

≈

sC18R

1s

2

R3



------- -

1s

d



R

d

⋅+()

τ

Figure 8 shows a method to select the regul ator components (pleas e note that the fr equencies f

⋅+()⋅

1s

⋅+

τ

d

τ

d

1s

⋅+()⋅⋅⋅ ⋅

τ

1

and fCC cor-

EC

responds to the singularities introduced by additional ceramic capacitors in parallel to the output main electro­lytic capacitor).

■

To obtain a flat frequency response of the output impedance, the droop time constant

τ

has to be equal

d

to the inductor time constant (see the note at the end of the section):

L

τ

d

■

To obtain a constant -20dB/dec Gloop(s) shape the singularity f1 and f2 are placed in proximity of fCE
and f

respectively. This implies that:

LC

⋅

RdC25

f

2

----

f

1

f1 f

■

To obtain a Gloop bandwidth of fC, results:

G0f

⋅ 1f

LC

=== ==

C

G

⇒⋅ A

0

⋅

0R0

------ - τ

R

L

f

LC

-------- -

R4⇒R3

f

CE

C20

CE

C20 // C25

VIN

⋅

----------------- -

Vosc∆

-----------------------------

L

C18

⇒

C25

f



LC

-------- -1–

⋅==



f



CE

1

-- - π

R4 f

2

f

C

C18⇒

------- -

f

LC

L

-----------------------=== =

⋅()

R

LRd

⋅⋅⋅=⇒=

CE

----------------- -

Vosc∆

-----------------------------

C20 C25

+

C20 C25⋅

VIN

⋅⋅

f

------- -

f

LC

C

Note.

To understand the reason of the previous assumption, the scheme in figure 9 must be considered.
In this scheme, the inducto r current has been subs tituted by the l oad current, becaus e in the fr equenci es range

of interest for the Droop function these curr ent are substantially the same and it was supposed that the droop
network don't represent a charge for the inductor.

13/20

L6911E

Figure 9. Volta ge regulation with droop function block scheme

VoutVcomp

1

R

⋅

OUT

1

R

OUT

s

τ

⋅+

L

s

τ

⋅+

d

⋅== =

+

τ

1s

-----------------­+

τ

1s

Iout

L
d

It results:

Z

OUT

V

o

--------------- -

I

LOAD

Av(s)

R(s)

+

τ

1s

L

------------------

⋅⋅

R

d

+

τ

1s

d

G

LOOP

---------------------------- ­+

1G

LOOP

Because in the interested range |Gloop|>>1.
To obtain a flat shape, the relationship considered will naturally follow.

VRM Demo Board Description

Figure 10 shows the sche matic c ircuit of the VR M eval uation board. The desi gn has been developed for a VRM

8.5 Flexible Motherboard applicaton delivering up to 28.5A.
An additional circuit sense a Vtt bus (1.2V typ.) and generate a 2.5mS (typ.) delayed Vtt_PWRGD signal when

this rail is over 1.1V. The assertion of the Vtt_PWRGD si gnal enables the device together with the ENOUT input.

Figure 10. Schematic Circuit

L1

F1

+5 VIN

+12Vcc

VID0

VID1

VID2

VID3

VID25mV

Vtt_sense

OUTEN

C19

C18

OVP

C11

19

OCSET

2

UGATE

14

PHASE

13

LGATE

1

17

PGND

16

PGOOD

12

VSEN

1

10

VFB

R5

R2

R3

C20

R4

C10

R7

C1-3

Q1,Q2

L2

VOUTCORE

Q3,Q4,Q5

D2

R8

R9

C17

C4-9

R15

PWRGD

Vtt_PGOOD

L6911E CONNECTOR EVALUATION KIT REV. 1.1

R6

Vss

BOOT

D1

15

R1

C13

NOT RESET

CT

R12

VCC

GND

VID0

VID1

VID2

VID3

VID4

OSC

SS

Q7

D3

C15

18

11

4

5

6

7

8

20

3

COMP

L6911E

9

R14

C12

C14

RESET

6

Vdd

8

5

NOT RESIN

2

UZ

GND

TLC7701

4

SENSE

C16

R13

R10

R11

3

7

1

CONTROL

Q6

14/20

L6911E

]

m

Efficiency

The measured efficiency versus load current at different output voltages is shown in figure 11. In the application
two Mosfets STS12NF30L (30V, 8.5m
while three of them are used for the Low Side.

Figure 11. Efficiency vs. load current

90
80
70
60
50

Efficiency [%]

40

Inductor design

Since the maximum output current is 28.5A, to have a 20% ripple (5A) the inductor chosen is 1.5µH.

Output Capacitor

In the demo six OSCON capacitors, model 6SP680M, are used, with a maximum ESR equal to 12mΩ each.
Therefore the resultant ESR is of 2m

The voltage drop due to the capacitor discharge during load transient, consider ing that the maximum duty cicle
is equal to 100% results in 46.5mV with 1.85V of programmed output.

Ω

typ with VGS=12V) connected in parallel are used for the High Side,

Vout = 1.825V
Vout = 1.225V
Vout = 1.500V

0 5 10 15 20 25

Ω

Output Current [A

. For load transient of 28.5A in the worst case the voltage drop is of:

∆

Vout = 28.5 * 0.002 = 57mV

Input Capacitor

For I
trolityc capacitors 6SP680M, with a maximum ESR equal to 12m
losses in worst case are:

=28.5A and with D=0.5(worst case fo r input c urrent r ipple), Irms is equal to 17.8A . Three OSCON elec-

OUT

⋅

ESR I

2
rms

=

(

1.25 670

Ω

, are chosen to substain the ripple. So the

()

Over-Current Protection

Substituting the demo board parameters in the relationship reported in the relative section, (I

=33A; R

I

P

DSONMAX

=3mΩ) it results that R

OCS

=1kΩ.

OCSMIN

=170µA;

15/20

L6911E

Connector Pin Orientation

Pin # Row A Pin # Row B

1 5Vin 50 5Vin
2 5Vin 49 5Vin
3 5Vin 48 5Vin
4 5Vin 47 5Vin
5 12Vin 46 12Vin
6 12Vin 45 12Vin
7 Reserved 44 No Contact
8 VID0 43 VID1

9 VID2 42 VID3
10 VID4 (25mV) 41 PWRGD
11 OUTEN 40 Ishare
12 V

TT_PWRGD

13 Vss 38 Vss
14 Vcc
15 Vcc

CORE
CORE

16 Vss 35 Vss
17 Vcc

CORE

Mechanical Key
18 Vss 33 Vss
19 Vcc

CORE

20 Vss 31 Vss
21 Vcc

CORE

22 Vss 29 Vss
23 Vcc

CORE

24 Vss 27 Vss
25 Vcc

CORE

39 V

37 Vss
36 Vcc

34 Vcc

32 Vcc

30 Vcc

28 Vcc

26 Vcc

TT

CORE

CORE

CORE

CORE

CORE

CORE

16/20

PCB AND COMPONENTS LAYOUT
Figure 12. PCB and Components Layouts

Component Side Silkscreen Component Side

Figure 13. PCB and Components Layouts

L6911E

Internal Layer Internal Ground Plane

Figure 14. PCB and Components Layouts

Solder Side Solder Side Silkscreen

17/20

L6911E

PART LIST

Resistors

R1 Not Mounted SMD 0805
R2 470K 1% SMD 0805
R3 1K SMD 0805
R4 82 SMD 0805
R5 Not Mounted SMD 0805
R6 20K SMD 0805
R7 680 SMD 0805
R8 13K SMD 0805

R9 100K SMD 0805
R10 6.8K 1% SMD 0805
R11 10K 1% SMD 0805
R12 1K SMD 0805
R13 10K SMD 0805
R14
R15 1K SMD 0805

Capacitors

C1-C3
C4-C9

C10 1nF SMD 0805

C11,C13-C16 100nF SMD 0805

C12
C17 47nF SMD 0805
C18 3.3nF SMD 0805
C19 Not Mounted SMD 0805
C20 100nF SMD 0805

820 µF – 4V or

Magnetics

L1 1.5µH T44-52 Core, 7T - 18AWG

L2 1.8µH T50-52B Core, 8T – 16AWG

Transistors

Q1-Q5 STS12NF30L or

Q6 Signal NPN BJT SOT23
Q7 Signal MOSFET SOT23

Diodes

D1 1N4148 SOT23

D2 STPS3L25U STMicroelectronics SMB

D3

Ics

U1 L6911E STMicroelectronics SO20

U2 TLC7701QD Texas Instruments SO8

Fuse

F1 251015A-15A Littlefuse AXIAL

Ω SMD 0805

8.2

680µF- 6.3V

680µF – 6.3V

1µF

FDS6670

OSCON 6SP680M Radial 10x10.5
OSCON 4SP820M

OSCON 6SP680M

STMicroelectronics

Fairchild

Radial 10x10.5
Radial 10x10.5

SMD 0805

SO8
SO8

18/20

L6911E

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

K 0˚ (min.)8˚ (max.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO20

B

e

D

1120

110

L

h x 45˚

A

K

A1

C

H

E

SO20MEC

19/20

L6911E

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or p at ent rights of STMicroelectronics. Spec i fications mentioned i n this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri t i cal compone nts in life support device s or systems without express written approval of STMicroel ectronics.

The ST logo is a registered trademark of STMicroelectronics

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20/20