Datasheet L6452 Datasheet (SGS Thomson Microelectronics)



DUAL 13X16 MATRIX HEAD INK JET DRIVER

DRIVESTWO13X16MATRIX HEADS
HEAD TEMPERATURESENSING
POWERUP SYSTEM
ELECTRICALNOZZLE CHECK
8 BIT A/D
5 BIT D/A

4KV ESD PROTECTED OUTPUTS

±

L6452

DESCRIPTION

L6452 is a device designed to drive two 13x16
matrixink jet printheadsin printer applications.

The output stage is ableto sourcesimultaneously
400 mA on each of the 16 power lines (columns)
with a duty cycle of 33% in normal printing and
66% in head pre-heating. On the address lines
(rows), the load is only capacitive (MOSFET driv­ing capability). The driver can control two print­heads, but only one is active at a time. The ad­dress scanning counter is included and can be
disabled to allow a differentscanningscheme.

Figure 1. Block Diagram

LINES

&

PRINT HEAD

DRIVER

POWER

LOGICAL

SUPPLIES

CONTROL

PQFP100

In order to avoid output activation during the sup­ply transient, an internal power-up system is im­plemented.

As supporting function, L6452is capable of sens­ing the head silicon temperature and to electri­cally check each nozzle.

The device is also integrating a thermal protec­tion.

16 POWER LINES

13 ADDRESS LINES

CHANNEL A

PRINT HEAD

A

A/D & PRINT HEAD

TEMPERATURE

CONTROL LINES

March 1999

PRINT HEAD

TEMPERATURE

CONTROL

13 ADDRESS LINES

CHANNEL B

ANALOG

INPUTS

PRINT HEAD

B

D97IN523

1/16

L6452

PIN CONNECTION (Topview)

RXA

RXB

VXa

VXb

_ONENABLE

CRCLOCK

CRDATA

96

97

98

99

100

V

C

V

C

V

C

V

C

V

C

C

V

C

V

C

1
2
3
4
5
6
7
8
9

10

12
13
14
15
16OUTPUT7

17
18
19
20V
21
22
23
24
25OUTPUT1
26
27
28
29
30NCEN

31 32 33 34 35

SDI

LATCH_DATA

SDC

LONG_PULSE

SHORT_PULSE

CRLATCH

OUTPUT15

POWGND
OUTPUT14
OUTPUT13

OUTPUT12
OUTPUT11

OUTPUT10

OUTPUT9

OUTPUT8

POWGND

OUTPUT6
OUTPUT5

OUTPUT4
OUTPUT3 59

OUTPUT2

POWGND

OUTPUT0

LATCH_CLEAR

REXT

95 94 93 92 9091 89 88 87 86 85

361137 38 39 40 41

ADCK

_RESET

CONV_START

CS_GND

NCOUT

CH0_BUF

aVDD

V

VSTEP-UP

42 43 44

ADDATA

ANALOGND

STEPUP_BO

STEPUP_GND

CLKCS0

_ENCH

45 46 47 48 49 50

a

V

CH5

VREF

ADCGND

RESCS1

84 83 8182

CH4

UPC52

S3

CH3

CH2

CHSEL

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60

58
57
56
55
54
53
52
51

CH1

ENLC
GND
HSA1
HSA2
HSA3
HSA4
HSA5
HSA6
HSA7
HSA8
HSA9
HSA10
HSA11
HSA12
HSA13
V
HSB13
HSB12
HSB11
HSB10
HSB9
HSB8
HSB7
HSB6
HSB5
HSB4
HSB3
HSB2
HSB1
GND

D97IN489B

r

PIN FUNCTIONS

Pin # Name Function

1 CRlatch A rising edge latches the informationpresent intothe control register

2, 5, 6, 8, 9,

11, 12, 14,
16, 18, 19,
21, 22, 24,

25, 28

3, 7, 10, 13,

17, 20, 23,

26

4, 15, 27,

51, 79, 92

29 Latch Clear A high level resets all bit in thelatch

2/16

Output 15...0 Highside DMOS outputs. To be active, Short Pulse and/or Long Pulse and Nozzle

Check Enable must have a low level

Vc Outputs Power Supply

GND logicand power ground

PIN FUNCTIONS (continued)

Pin # Name Function

30 NCEn A high level enables the internal current sourcesand disables all DMOS outputs.To

be active, the internal current sources must have their corrsponding bit set inthe 16 bit
latchand Long Pulse must be set to low level. A low level enables the internalHSA/B

shortcircuit detection
31 Latch Data A rising edge latches the 16 bit stored in the shift register in the 16 bit latch
32 SDI Serialdata input of the shift register
33 SDC The data bit presented to the Serial Data Input pin is stored intothe register on the

risingedge of this pin
34 Long Pulse Alow level activates all outputs having their coresponding bit in the 16 bit latch set

(thispin has an internal pull-up resistor)
35 Short Pulse A low level activates all outputs having their coresponding bit in the 16 bit latch reset

(thispin has an internal pull-up resistor)
36 _Reset A low level disables all functions and clears all registers
37 ConvStart A high level enables the A/D to start the new conversion
38 ADCK A/D clock signal; the ADDATA signal are valid on the falling edge of this pin
39 NCOut If Nozzle Check Enable is high this output provides a high level when the open load is

detected on the output. If Nozzle Check Enable is lowthis output provides a highlevel

when a short circuit is detected on HSA/B output
40 CH0_buf Analogoutput signal (CH0 buffered)
41 ADDATA A/D serial data output
42 AnalogGND Analog ground connection
43 ADCGND Groundof internal ADC

44, 90 Va Power supply

45 Vref Reference voltage generator

46 to 50 CH5..CH1 A/D input signals
52 to 64 HSB1..HSB13 Head selector address output channel B

65 Vr Head Select Power Supply

66 to 78 HSA13..HSA1 Head selector address output channel A

80 EnlC A high level enables the counter and the internaldecoder will activate of the HSx

outputsaccording to the counter’s outputs. Signal S0 becomes Clock Counter and S1

becomes Reset Counter
81 ChSel A low level enables channel A and a high level enables channel B
82 S3 Decoder input signals when Enable Counter is low
83 UpC/ S2 A high level enables the internalcounter to up counting. A low level enables down

counting
84 ResC/S1 A low level resets the internal counter
85 _EnCh A low level enables the selected channel (this input has an internal pull up resistor)
86 ClkC/S0 Ahighlevel clocks the internal counter
87 Step up GND Groundof step up block
88 Step up boost Boostvoltage
89 Vstep up Driving voltage of power DMOS stage
91 VDD 5V logic supply
93 Rext An external resistor connected versus ground fixes the internal current source value

94, 95 RxB, RxA Current source outputs
96, 97 VxA, VxB RxA, RxB voltage after an optional external filter

98 _ONenable Alowlevel enables the current source generator according the _A/B and ON/_OFF

control register bit
99 CRclock Data on pin CRdata are stored into the register on the rising edge of this pin

100 CRdata Control register serial data input

L6452

3/16

L6452

Figure 2. Block Diagram: Nozzle activationpart.

* LONGPULSE

* SHORTPULSE

16 BIT

INPUT

PARALLEL

OUTPUT

SERIAL DATA INPUT

SERIAL DATA CLOCK

LATCH CLEAR

LATCH DATA

NOZZLE CHECK ENABLE

SERIAL

&

16 BIT LATCH

16

POWER
OUTPUT
STAGES

OUTPUT 0
OUTPUT 1
OUTPUT 2
OUTPUT 3
OUTPUT 4
OUTPUT 5
OUTPUT 6
OUTPUT 7
OUTPUT 8

OUTPUT 9
OUTPUT 10
OUTPUT 11
OUTPUT 12
OUTPUT 13
OUTPUT 14
OUTPUT 15

NOZZLE

OUTPUT

CHECK

INTERNAL

ENABLE

COUNTER

SEL 3

UP COUNTING/SEL 2

*RESET COUNTER/SEL1

CLOCK COUNTER/SEL 0

*SELECT CHANNEL

*ENABLE CHANNEL

0to

13
UP/DOWN
COUNTER

SELECTOR

D97IN524

HSA 1
HSA 2
HSA 3
HSA 4
HSA 5

13

MOS

DRIVERS

CHANNEL A

C0

C1

4to13

LINES

DECODER

C2

C3

13

MOS

DRIVERS

CHANNEL B

HSA 6
HSA 7
HSA 8

HSA 9
HSA 10
HSA 11
HSA 12
HSA 13

HSB 1

HSB 2

HSB 3

HSB 4

HSB 5

HSB 6

HSB 7

HSB 8

HSB 9
HSB 10
HSB 11
HSB 12
HSB 13

4/16

Figure 3. Block Diagram: Power Line Output Stage.

DATA BIT 0

1
0

L6452

POWER SUPPLY

10mA

OUTPUT 0

FROM 16 BIT
DATA LATCH

DATA BIT 1

DATA BIT 15

*LONG PULSE

* SHORT PULSE

NOZZLE CHECK ENABLE

D97IN525

OUTPUT 1

OUTPUT 15

TRIGGER

NOZZLE CHECK OUTPUT

5/16

L6452

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

c

V

r

V

a

V

dd

V

step_up

V

in

I

out

T

j

T

amb

T

stg

DC ELECTRICAL CHARACTERISTICS (Tj=25°C)

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

c

V

r

V

a

V

dd

I

cs

I

rs

I

as

I

c

I

r

I

a

I

dd

V

ref

I

refext

I

css

I

∆

css/Icss

V

ampout

V

cm

g1 Amp. A1 Voltage gain 1.188 1.2 1.212
g2 Amp.A2 Voltage gain 2.95 3.02 3.10

V

step-up

* the three supply voltage are independent insidethe specified value;
** the Min value for Vc Power line could be decreased up to9V (under evaluation);
*** e = 2 ⋅ V

Power line supply voltage 14 V
Address line supply voltage 14 V
Analog supply voltage 14 V
Logic supplyvoltage 6 V
Driving voltage of power DMOS stage 28 V
Logic inputvoltage range -0.3 to Vdd+0.3 V
Output continuous current 0.5 A
Junction temperature 150 °C
Operating temperature range 0 to 70 °C
Storage temperature range -55 to 150 °C

Power Line Supply voltage * 10.5 ** 11.5 12.5 V
Address line supply voltage * 10.5 11.5 12.5 V
Analog supply voltage * 10.5 11.5 12.5 V
Logic supply voltage 4.5 5 5.5 V
Vcsleep supply current ONenable = 1
Vrsleepsupply current 0.3 mA

Reset = 0

1mA

Vasleepsupply current 3 mA
Vc supply current 1.5 mA
Vr supply current 0.6 mA
Va supply current I

= 3mA 13 mA

Rext

Vddsupply current sleep or normal condition 5 mA
Reference Voltage T

= 5 to 55°C 4.85 5 5.15 V

amb

Reference current(external) 7 mA

V

Programmed constantcurrent

ref

2R

ext

4

⋅

I

=

ccs

Constant current regulation Va=11V T
Output voltage of integrated

= 5 to 55°C 0.33 %

amb

e *** Va-1 V

12 13.5 mA

amplifier
Operating input voltage at pins

V

= 5V g1=1.2 g2=3 7 V

ref

Vxa and Vxb

Driving Voltageof power DMOS Vc +11 V

step

A/D CONVERTER

V

I

A/Din

exch

A/D input voltage Selected Channel:

A/D input current Input CH1 to CH5 Channel

OFFSET VOLTAGE GENERATION / DAC

V

V

K

offset

step
dac

Offset Voltage V
Voltage increment (1LSB) V
Voffset/Vref Any step N>=4

6/16

CH1toCH5
Selected Ch=CH0

0

e ***

Vref
Vref

±1 µA

selected or not

= 5V 2.5+e*** 7.34 V

ref

= 5V 156 mV

ref

3%

±

V
V

DC ELECTRICAL CHARACTERISTICS(Tj=25°C)

Symbol Parameter Test Condition Min. Typ. Max. Unit

A/D CONVERTER TIMINGS

T

cscks

T

csckh

T

ckout

T

csz

F

adck

T

cslow

T

acq th

T

acqpr

DIGITAL INTERFACE INPUT

V

inp

V

inm

V

hys

I

in

* This applies to input pins having an internal pull-up (ENABLE_CHANNEL,LONG_PULSE, SHORT_PULSE)

CR LATCH TIMINGS

T

ls

T

lhigh

T

lconv

NB: The control register (driving signals CRdata, CRclock) is accessed with the same timingspecifications as the
data 16 bit shift register (signals Serial data, Serial clock)

Conv. start set uptime 200 ns
Conv. Start hold time 200 ns
Falling edge of clock to data

20pF 200 ns

C

≤

load

out valid delay
ConvStart falling edge to output

200 ns

in Hi-Z delay
Clock frequency 250 KHz
Conv. Start low level time 5.6
Theoretical acquisition time f
Real acquisition time f

Schmitt Trigger positive-going

= 250 kHz 32.4

adck

= 250 kHz 36

adck

2/3V

dd

Threshold
Schmitt Trigger negative-going

1/3V

dd

Threshold
Scmitt Trigger Hysteresis 0.1 0.3 1 V
Input Current (Vin=0; Vdd=5)* 50 150 300

Latch set up time 100 ns
Latch high time 100 ns
Latch data valid to A/D input

valid delay

Selected channel:
CH1..CH5
CH0

4
7

L6452

s

µ

s

µ

s

µ

V

V

A

µ

µs

s

µ

SHIFT REGISTER AND LATCH TIMING

T

a

T

b

T

c

T

d

T

e

T

f

T

g

T

set

Set up time 50 ns
Hold time 50 ns
Serial clock low time 50 ns
Serial clock high time 50 ns
Serial clock period 150 ns
Latch set up time 100 ns
Latch data high time 100 ns
Long Pulse set_up time with

respect to NCEn

T

hold

Long Pulse hold time with
respect to NCEn

OUTPUTS ELECTRICAL CHARACTERISTICS

R

ds (ON)

I

out

T

on

T

off

Output Current (outputs 0..15) DC=33%;
On Resistance Tj=25°C 1.3

Turn on Time (Tdelay+ Trise) From 50% Long Pulse to 90%

Toff delay time From 50% Long Pulse to 90%

160 ns

0ns

preheating DC=66% 400 mA

Ω

160 ns
power output rising edge
Load = 30 Ohm in parallel with

1.5nF

100 ns
power output falling edge
Load = 30 Ohm in parallel with

1.5nF

7/16

L6452

DC ELECTRICAL CHARACTERISTICS(Tj=25°C)

Symbol Parameter Test Condition Min. Typ. Max. Unit

HEAD ADDRESS SELECTOR OUTPUT

T

h

T

k

T

j

T

i

T

m

T

n

T

o

f

clk-counter

ClK

dc

T

on/off

Up Counting, Reset Counter,
Select Channel, Clock Counter
and Enable Internal Counter
set-up time with respect to
Enable channel

Up Counting, Reset Counter,
Select Channel, Clock Counter
and Enable Internal Counter
hold time with respect to
Enable channel

Up Counting with respect to
Clock Counter hold time

Up counting with respect to
Clock Counter set_up time

Enable input to active output
delay time

Clock to active output delay
time

Disable input to inactive output
delay time

Counter Clock Frequency 1 MHz
Clock duty cycle 10 90 %
Turn on/off time From 50% Clock counter or

selector signal to 90% of the
address output variation Load:
see fig. 10

150 ns

50 ns

200 ns

100 ns

100 ns

150 ns

100 ns

325 ns

COUNTERTRUTH TABLE

Enable internal counter = 1
Up Counting= 1
Reset Counter = 1

Clock Counter C3 C2 C1 C0

00000

0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1000
0000

8/16

COUNTERTRUTH TABLE (continued)
Enable internal counter = 1

Up Counting= 0
Reset Counter = 1

Clock Counter C3 C2 C1 C0

00000

1000
1010
1110
1111
1101
1100
0100
0101
0111
0110
0010
0011
0001
0000

L6452

DECODER TRUTH TABLE

OUTPUTS (HS)

ACTIVE

All inactive 0 0 0 0

10001
20011
30010
40110
50111
60101
70100
81100

91101
101111
111110
121010
131000

All inactive 1 0 0 1
All inactive 1 0 1 1

C3 C2 C1 C0

This table is valid for both ChannelA and Channel B and whenEnable Channel is set to low level.

9/16

L6452

PRINTHEAD TEMPERATURECONTROL PART
Introduction

For quality printing, it is necessary to know and
control the temperature of the printhead. Thus,
the latter has a built - in aluminium resistor,
whose value changes slightly with the tempera­ture. The temperature determination is done by
injecting a constant current in the resistor, and
measuring the voltagedrop across it. Since high ­end printers have two heads, it must also be pos­sible to switch quikly the measurement process
from one to the other. The function is foreseen to
be integrated into the head driver, and is de­scribed hereafter.

Print Head Block Diagram (fig. 4)

At first we have a constant current source, which
can be disabled by an external pin (ONenable)or
by a controlregister, described later. Thevalue of
the current can be programmed by an external
resistor,and is given by:

4

V

⋅

ref

=

I

CCS

2 ⋅ R

ext

This current is injected either into the aluminium
resistor of thehead A (Ralu. A) or B (Ralu. B), de­pending of the switch SW3. The alu. resistors are
grounded, and the voltage at their << hot >> side

(Vx) is re-entered via the pins Vxa and Vxb. Us­ing separatepins from Rxa and Rxb permits to be
more flexible, and a filter can eventuallybe added
as shownin the drawing.

The voltage Vx is amplified by A1 and A2, and
then converted in a digital value. To be compat­ible with the input range of the A/D converter,it is
necessary to subtract an offset voltage Voffset
from Vx. Moreover, as the initial value of the alu.
resistor is very unprecise. Voffset must be adjust­able; this is done by means of a 5 bit - D/A con­verter, giving 32 different values. Finally, the volt­age at the input of the A/D converteris:

=g1⋅g2⋅VX-g2⋅V

V

CH0

OFFSET

or

V

=g1⋅g2 ⋅ Ralu⋅ I

CH0

V

OFFSET=VREF

/2 + N ⋅ V

The reference voltage generator (V

-g2⋅V

CCS

/32 N = 0, 1, ...31

REF

OFFSET

REF

;

) is inte­grated, and used for the current source and both
the A/D and D/A converters. In this way, the sys­tem performance is independent from the preci­sion of V

; this one should, however, be stable.

REF

Vref is also available on pin #45, and can be
used for low consumption purposes. (The exter­nal sinkedcurrenthas to be a DC current)

The system is under control of a 10 bit register,
CR. CR is accessed serially and has a transpar­ent latch, which can be used or not (by trying the
latch signal CR latch to V

CC

).

Figure 4. PrintHead Block Diagram

Va

REF

VOLT

VREF OUT

REXT

ONENABLE

RXA, RXB VXA, VXB

VREF

HIGH-SIDE

CONSTANT

CURRENT

SOURCE

SW1

SW2

SW3

RALU BRALU A

VREF/2

Vx

A/B ON/OFF DA4 DA3 DA2 DA1 DA0 S2 S1 S0

Note;the analog groundis separated from the digital ground of the remaining partof the driver

A1

g1

+

VOFFSET

D/A 5BIT

VREF

ANALOG GND

CONV START
ADCK
ADDATA

CH5
CH4
CH3

INPUTS

CH2
CH1

CH0_BUF

CRLATCH

CRCLOCK
CRDATA

D97IN533B

A/D

CONTROL

REGISTER

A

A2

CH0+

g2

-

VREF

A
B
D
C

D

LATCH 10 BIT

SHIFT REG. 10 BIT

10/16

Figure 5. ControlRegister details.

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

A/B ON/OFF DA4 DA3 DA2 DA1 DA0 S2 S1 S0

L6452

SHIFT DIRECTION

SELECTION OF RESISTOR A
(A/B = 0) orB
(A/B = 0) for
TEMPERATURE MEASUREMENT

SWITCHES THE CURRENT SOURCE ON or OFF;
LINKED WITH ONENABLE INPUT PIN

ON/OFF ONENABLE ACTION

0
1
0
1

Figure 6. CR Latch Timings

CRDATA

CRCLOCK

CRLATCH

D/A INPUTS FOR OFFSET

COMPENSATION

DA0 = LSB

DA4 = MSB

POSITIVE LOGIC

S2 SELECTED CHANNEL CH0 BUF

1
1
0
0

OFF
OFF
OFF

ON

DA0 S2 S1 S0

CHANNEL SELECTION

A/D INPUT

ONE INTERNAL CHANNEL
(VX MEASUREMENT)
FIVE UNCOMMITTED, GENRAL-PURPOSE
EXTERNAL CHANNELS

S1

S0

0

0

0

0

0

1

0

1

0

0

1

1

11000

1

D97IN534A

0 (INTERNAL)
1 (EXTERNAL)
2 (EXTERNAL)
3 (EXTERNAL)
4 (EXTERNAL)

5 (EXTERNAL)
110 6
111 7

t

ls

t

lhigh

A
B
B
B
B
B
C
D

CONVSTART

Figure 7. A/D Converter Timings

CONVSTART

ADCK

ADDATA

HIGH IMPEDANCE

t

cscks

t

csckh

t

ckout

t

lconv

D97IN535

65 4 27 3 1 0 HIGH IMPEDANCE

t

csx

D97IN536

11/16

L6452

Figure 8. PowerOutputTiming

LONG PULSE or

SHORT PULSE

POWER OUTPUT

50% 50%

10% 10%

t

d

Figure 9. Triggerof Nozzle Check Signal

90% 90%

t

r

V

POWER

V

t

LOGIC

t

d

f

D97IN526

12/16

FROM THE COMMON CONNECTION

OF ANALOG MULTIPLEXERS

INTERNAL

REFERENCE

HSA/B SHORT CIRCUIT DETECTION

-

1

NOZZLE

CHECK

OUTPUT

+

0

NCEM

D97IN527

Figure 10. AddressOutput Timing

L6452

SEL 0 to 3

ADDRESS

MEASURED AT POINT A

OUTPUT

Figure 11. ModeCounter

UP COUNTING

HS OUTPUT

50% 50%

10% 10%

t

d

200Ω

250pF

90% 90%

t

r

A

SIGNAL

CLOCK

COUNTER

SELECTOR SIGNAL

t

t

d

f

D97IN528A

RESET COUNTER

SELECT CHANNEL

ENABLE INTERNAL

COUNTER

CLOCK COUNTER

ENABLE CHANNEL

OUTPUT 1 :13

HSA or HSB)

t

t

h

t

m

t

i

j

t

k

t

n

D97IN529A

t

o

13/16

L6452

Figure 12. ModeSel 0:3

SEL 0:3

SELECT CHANNEL

ENABLE

INTERNAL

COUNTER

ENABLE CHANNEL

t

h

OUTPUT 1 :13

HSA or HSB)

t

m

Figure 13. Sequenceof ShiftRegisterData Loading

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0SERIAL DATA

SERIAL CLOCK

LATCH DATA

LONG PULSE

SHORT PULSE

OUTPUT *

OUTPUT **

* THE CORRESPONDING DATA BITIS SET
** THE CORRESPONDING DATA BITIS RESET

t

k

t

D97IN530

n

D97IN531

t

o

Figure 14. Latch Timing

14/16

SERIAL DATA

SERIAL CLOCK

LATCH DATA

D97IN532

t

a

t

c

t

b

t

f

t

e

t

t

g

d

L6452

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 3.40 0.134
A1 0.25 0.010
A2 2.55 2.80 3.05 0.100 0.110 0.120

B 0.22 0.38 0.0087 0.015

C 0.13 0.23 0.005 0.009

D 22.95 23.20 23.45 0.903 0.913 0.923
D1 19.90 20.00 20.10 0.783 0.787
D3 18.85 0.742

e 0.65 0.026

E 16.95 17.20 17.45 0.667 0.677 0.687
E1 13.90 14.00 14.10 0.547 0.551
E3 12.35 0.486

L 0.65 0.80 0.95 0.026 0.031 0.037
L1 1.60 0.063

K 0°(min.),7°(max.)

mm inch

0.791

0.555

OUTLINE AND

MECHANICAL DATA

PQFP100

15/16

L6452

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved

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