Datasheet L6388ED Specification

High voltage high and low-side driver

DIP-8 SO-8

Features

 High voltage rail up to 600 V

 dV/dt immunity ± 50 V/nsec in full temperature

range

 Driver current capability:

– 400 mA source
– 650 mA sink

 Switching times 70/40 nsec rise/fall with 1 nF

load

 3.3 V, 5 V, 15 V CMOS/TTL input comparators

with hysteresis and pull-down

 Internal bootstrap diode

 Outputs in phase with inputs

 Deadtime and interlocking function

L6388E

Datasheet - production data

Description

The L6388E is a high voltage gate driver,
manufactured with the BCD ™ “offline”
technology, and able to drive a half-bridge of
power MOSFET/IGBT devices. The high-side
(floating) section is enabled to work with voltage
rail up to 600 V. Both device outputs can sink and
source 650 mA and 400 mA respectively and
cannot be simultaneously driven high thanks to an
integrated interlocking function. Further
prevention from outputs cross conduction is
guaranteed by the deadtime function.

The L6388E device has two input and two output
pins, and guarantees the outputs switch in phase
with inputs. The logic inputs are CMOS/TTL
compatible (3.3 V, 5 V and 15 V) to ease the
interfacing with controlling devices.

The bootstrap diode is integrated in the driver
allowing a more compact and reliable solution.

The L6388E device features the UVLO protection
on both supply voltages (V
ensuring greater protection against voltage drops
on the supply lines.

CC

and V

BOOT

)

Applications

 Home appliances

 Industrial applications and drives

 Motor drivers

– DC, AC, PMDC and PMAC motors

 Induction heating

 HVAC

 Factory automation

 Lighting applications

 Power supply systems

October 2015 DocID13991 Rev 5 1/18

This is information on a product in full production.

The device is available in a DIP-8 tube and SO-8
tube, and tape and reel packaging options.

www.st.com

Contents L6388E

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6 Input logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

C

selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BOOT

8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

9.1 DIP-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

9.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/18 DocID13991 Rev 5

L6388E Block diagram

-0(*$

67

%&5&$5*0/

-&7&-

4)*'5&3

#005453"1%3*7&3

3

4

7

$$

-7(

%3*7&3

7

$$











)*/

-*/

)7(

%3*7&3

)7(

)7

50-0"%

065

-7(

(/%

7

#005







$

#005

4)005

5)306()

13&7&/5*0/

67

%&5&$5*0/

3

".

1 Block diagram

Figure 1. Block diagram

DocID13991 Rev 5 3/18

18

Electrical data L6388E

2 Electrical data

2.1 Absolute maximum ratings

Symbol Parameter

dV

V

V

OUT

V

CC

BOOT

V

hvg

V

lvg

V

OUT

P

tot

T

T

Output voltage V

Supply voltage - 0.3 18 V

Floating supply voltage - 0.3 618 V

High-side gate output voltage V

Low-side gate output voltage -0.3 VCC +0.3 V

Logic input voltage -0.3 VCC +0.3 V

i

/dtAllowed output slew rate 50 V/ns

Total power dissipation (TJ = 85 °C) 750 750 mW

Junction temperature 150 150 °C

j

Storage temperature -50 150 °C

s

ESD Human body model 2 kV

2.2 Thermal data

Table 1. Absolute maximum ratings

Min. Max.

BOOT

OUT

Value

-18 V

-0.3 V

BOOT

BOOT

Unit

V

V

Table 2. Thermal data

Symbol Parameter SO-8 DIP-8 Unit

R

Thermal resistance junction to ambient 150 100 °C/W

th(JA)

2.3 Recommended operating conditions

Symbol Pin Parameter Test condition Min. Typ. Max. Unit

V

OUT

V

BS

f

sw

V

CC

T

1. If the condition V

2. VBS = V

6 Output voltage

(2)

8 Floating supply voltage

3 Supply voltage 17 V

J

- V

BOOT

Table 3. Recommended operating conditions

Switching frequency HVG, LVG load CL = 1 nF 400 kHz

Junction temperature -45 125 °C

- V

BOOT

OUT

< 18 V is guaranteed, V

OUT

.

can range from -3 to 580 V.

OUT

(1)

(1)

17 V

580 V

4/18 DocID13991 Rev 5

L6388E Pin connection

7

$$

)*/

-*/

(/%







-7(

065

)7(

7

#005









%*/"W

3 Pin connection

Figure 2.Pin connection (top view)

Table 4. Pin description

No. Pin Type Function

1 LIN I Low-side driver logic input

2 HIN I High-side driver logic input

3 V

P Low-voltage power supply

CC

4 GND P Ground

(1)

5 LVG

O Low-side driver output

6 OUT P High-side driver floating reference

7 HVG

8 V

1. The circuit guarantees 0.3 V maximum on the pin (at I
“bleeder” resistor connected between the gate and the source of the external MOSFET normally used to
hold the pin low.

(1)

O High-side driver output

P Bootstrap supply voltage

BOOT

= 10 mA). This allows the omission of the

sink

DocID13991 Rev 5 5/18

18

Electrical characteristics L6388E

4 Electrical characteristics

4.1 AC operation

Table 5. AC operation electrical characteristics (VCC = 15 V; TJ = 25 °C)

Symbol Pin Parameter Test condition Min. Typ. Max. Unit

t

on

1 vs. 5
2 vs. 7

t

off

t

r

t

f

High/low-side driver turn-on
propagation delay

High/low-side driver turn-off
propagation delay

= 0 V 225 300 ns

V

OUT

= 0 V 160 220 ns

V

OUT

5, 7 Rise time CL = 1000 pF 70 100 ns

5, 7 Fall time CL = 1000 pF 40 80 ns

DT 5, 7 Deadtime 220 320 420 ns

4.2 DC operation

Symbol Pin Parameter Test condition Min. Typ. Max. Unit

Low supply voltage section

V

CCth1

V

CCth2

V

CChys

I

QCCU

I

QCC

R

DS(on)

3

UV turn-on threshold 9.1 9.6 10.1 V

V

CC

VCC UV turn-off threshold 7.9 8.3 8.8 V

VCC UV hysteresis 0.9 V

Undervoltage quiescent supply
current

Quiescent current VCC = 15 V 350 450 A

Bootstrap driver on resistance

Bootstrapped supply voltage section

Table 6. DC operation electrical characteristics

 9 V 250 330 A

V

CC

(1)

V

 12.5 V 125 

CC

V

V

V

I

BSth1

BSth2

BShys

Q

BS

I

LK

8

UV turn-on threshold 8.5 9.5 10.5 V

V

BS

VBS UV turn-off threshold 7.2 8.2 9.2 V

VBS UV hysteresis 0.9 V

VBS quiescent current HVG ON 250 A

High voltage leakage current V

hvg

= V

OUT

High/low-side driver

I

so

I

si

Source short-circuit current V

5, 7

= Vih (tp < 10 s) 300 400 mA

IN

Sink short-circuit current VIN = Vil (tp < 10 s) 500 650 mA

6/18 DocID13991 Rev 5

= V

= 600 V 10 A

BOOT

L6388E Electrical characteristics

R

DSON

VCCV

BOOT1

–VCCV

BOOT2

––

I

1VCC,VBOOT1

I2VCC,V

BOOT2

–

-----------------------------------------------------------------------------------------------=

Table 6. DC operation electrical characteristics (continued)

Symbol Pin Parameter Test condition Min. Typ. Max. Unit

Logic inputs

1. R

V

V

ih

I

ih

I

il

DS(on)

il

Low logic level input voltage 1.1 V

High logic level input voltage 1.8 V

1, 2

High logic level input current VIN = 15 V 20 70 A

Low logic level input current VIN = 0 V -1 A

is tested in the following way:

where:

I

is pin 8 current when V

1

BOOT

= V

BOOT1

, I2 when V

BOOT

= V

BOOT2

.

DocID13991 Rev 5 7/18

18

Waveform definitions L6388E

DT DT

DT

LIN

HIN

LVG

HVG

Interlocking function

5 Waveform definitions

Figure 3. Deadtime time waveform definition

Figure 4. Propagation delay waveform definition

8/18 DocID13991 Rev 5

L6388E Input logic

C

EXT

Q

gate

V

gate

-------------- -=

6 Input logic

Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG)
being active at the same time when both the logic input pins (LIN, HIN) are at a high logic
level. In addition, to prevent cross conduction of the external MOSFETs, after each output is
turned off, the other output cannot be turned on before a certain amount of time (DT) (see

Figure 3).

7 Bootstrap driver

A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 5 a). In the L6388E device,
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as
shown in Figure 5 b. An internal charge pump (Figure 5 b) provides the DMOS driving
voltage. The diode connected in series to the DMOS has been added to avoid an
undesirable turn-on.

C

BOOT

selection and charging

To choose the proper C
capacitor. This capacitor C

Equation 1

The ratio between the capacitors C
It must be:

E.g.: if Q

is 30 nC and V

gate

300 mV.

If HVG must be supplied for a long period, the C
losses into account.

E.g.: HVG steady-state consumption is typical 250 A, so, if HVG T
supply 1.25 C to C

EXT

The internal bootstrap driver offers important advantages: the external fast recovery diode
can be avoided (it usually has a high leakage current).

This structure can work only if V
LVG is on. The charging time (T
fulfilled and it must be long enough to charge the capacitor.

value, the external MOSFET can be seen as an equivalent

BOOT

is related to the MOSFET total gate charge:

EXT

is 10 V, C

gate

EXT

and C

C

BOOT

EXT

is proportional to the cyclical voltage loss.

BOOT

>>>C

EXT

is 3 nF. With C

selection must also take the leakage

BOOT

= 100 nF the drop is

BOOT

is 5 ms, C

ON

BOOT

. This charge on a 1 F capacitor means a voltage drop of 1.25 V.

is close to GND (or lower) and, at the same time, the

OUT

charge

) of the C

is the time in which both conditions are

BOOT

must

The bootstrap driver introduces a voltage drop due to the DMOS R

(typical value:

DS(on

)

125 ). This drop can be neglected at low switching frequency, but it should be taken into
account when operating at high switching frequency.

DocID13991 Rev 5 9/18

18

Bootstrap driver L6388E

V

dropIch eargRdsonVdrop



Q

gate

T

ch earg

------------------- R

dson

==

V

drop

30nC

5 s

-------------- - 125 0.8V=

TO LOAD

H.V.

HVG

a

b

LVG

HVG

LVG

C

BOOT

TO LOAD

H.V.

C

BOOT

D

BOOT

V

BOOT

V

S

V

S

V

OUT

V

BOOT

V

OUT

The following equation is useful to compute the drop on the bootstrap DMOS:

Equation 2

where Q
of the bootstrap DMOS, and T

is the gate charge of the external power MOSFET, R

gate

is the charging time of the bootstrap capacitor.

charge

is the on-resistance

DS(on

)

For example: using a power MOSFET with a total gate charge of 30 nC, the drop on the
bootstrap DMOS is about 1 V, if the T

charge

is 5 s.

In fact:

Equation 3

V

should be taken into account when the voltage drop on C

drop

is calculated: if this drop

BOOT

is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.

Figure 5. Bootstrap driver

10/18 DocID13991 Rev 5

L6388E Typical characteristics

For both high and low side buffers @25˚C Tamb

0 1 2 3 4 5 C (nF)

0

50

100

150

200

250

time

(nsec)

T

r

D99IN1054

T

f

0

2 4 6 8 10 12 14 16 V

S

(V)

10

10

2

10

3

10

4

Iq

(μA)

D99IN1055

-45 -25 0 25 50 75 100 125

5

6

7

8

9

10

11

12

13

V

BSth1

(V)

Tj (˚C

)

Typ.

@ Vcc = 15V

-45 -25 0 25 50 75 100 125

6

7

8

9

10

11

Vccth2(V)

Tj (˚C

)

Typ.

-45 -25 0 25 50 75 100 125

6

7

8

9

10

11

12

13

14

Typ.

@ Vcc = 15V

V

BSth2

(V)

-45-250 255075100125

0

200

400

600

800

1000

current (mA)

Tj (˚C

)

Typ.

@ Vcc = 15V

8 Typical characteristics

Figure 6. Typical rise and fall times

Figure 8. V

vs. load capacitance

UV turn-on threshold

BOOT

vs. temperature

Figure 7. Quiescent current vs. supply

voltage

Figure 9. VCC UV turn-off threshold

vs. temperature

Figure 10. V

UV turn-off threshold

BOOT

vs. temperature

DocID13991 Rev 5 11/18

Figure 11. Output source current

vs. temperature

18

Typical characteristics L6388E

-45 -25 0 25 50 75 100 125

7

8

9

10

11

12

13

Vccth1(V)

Tj (˚C

)

Typ.

-45 -25 0 25 50 75 100 125

0

200

400

600

800

1000

current (mA)

Tj (˚C

)

Typ.

@ Vcc = 15V

Figure 12. VCC UV turn-on threshold

vs. temperature

Figure 13. Output sink current

vs. temperature

12/18 DocID13991 Rev 5

L6388E Package information

$0Y

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK

9.1 DIP-8 package information

Figure 14. DIP-8 package outline

DocID13991 Rev 5 13/18

18

Package information L6388E

Table 7. DIP-8 package mechanical data

Dimensions (mm)

Symbol

Min. Typ. Max.

A 3.32

a1 0.51

B 1.15 1.65

b 0.356 0.55

b1 0.204 0.304

D 10.92

E 7.95 9.75

e 2.54

e3 7.62

e4 7.62

F 6.6

I 5.08

L 3.18 3.81

Z 1.52

14/18 DocID13991 Rev 5

L6388E Package information

$0Y

9.2 SO-8 package information

Figure 15. SO-8 package outline

Table 8. SO-8 package mechanical data

Dimensions (mm)

Symbol

Min. Typ. Max.

A 1.75

A1 0.10 0.25

A2 1.25

b 0.28 0.48

c 0.17 0.23

D 4.80 4.90 5.00

E 5.80 6.00 6.20

E1 3.80 3.90 4.00

e1.27

h 0.25 0.50

L 0.40 1.27

L1 1.04

k0° 8°

ccc 0.10

DocID13991 Rev 5 15/18

18

Order codes L6388E

10 Order codes

Part number Package Packaging

L6388E DIP-8 Tube

L6388ED SO-8 Tube

L6388ED013TR SO-8 Tape and reel

Table 9. Order codes

16/18 DocID13991 Rev 5

L6388E Revision history

11 Revision history

Table 10. Document revision history

Date Revision Changes

11-Oct-2007 1 First release

Updated Table 2, Table 7 and Section 6.1.

29-Feb-2012 2

DIP-8 mechanical data and package dimensions have been
updated.

SO-8 mechanical data and package dimensions have been updated.

31-Jan-2013 3 Update note in Section 2.1.

Added Section : Applications on page 1.
Updated Section : Description on page 1 (replaced by new

description).
Updated Table 1: Device summary on page 1 (moved from page 17

to page 1, renamed title of Table 1).
Updated Figure 1: Block diagram on page 3 (moved from page 1 to

page 3, added Section 1: Block diagram on page 3).

19-Jun-2014 4

Updated Section 2.1: Absolute maximum ratings on page 4
(removed note below Table 2: Absolute maximum ratings).

Updated Table 5: Pin description on page 5 (added “Type” for
several pins).

Updated Section 9: Package information on page 14 (added/updated
titles, reversed order of Figure 14 and Tabl e 8 , Figure 15 and
,Tab le 9 minor modifications).

Minor modifications throughout document.

21-Oct-2015 5

Updated Table 1 on page 4 (added ESD row).
Updated note 1. below Table 6 on page 6 (replaced V

).

V

BOOTx

CBOOTx

by

Added Section 10: Order codes on page 16 (moved Table 9 from
page 1, updated title).

Minor modifications throughout document.

DocID13991 Rev 5 17/18

18

L6388E

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

18/18 DocID13991 Rev 5