Datasheet KS88C8432, KS88C8424, KS88P8432 Datasheet (Samsung)

Product Overview

Address Spaces

Addressing Modes

Control Registers

Interrupt Structure

Instruction Set

KS88C8424/C8432/P8432 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM87 PRODUCT FAMILY

Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Release of Idle and Stop power-down modes by interrupt
— Built-in basic timer circuit with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.

KS88C8424/C8432/P8432 MICROCONTROLLERS

The KS88C8424 microcontroller has a 24-Kbyte on-chip program memory and the KS88C8432 has a 32-Kbyte.
Both chips have a 272-byte general-purpose internal register file. The interrupt structure has nine interrupt
sources with nine interrupt vectors. The CPU recognizes seven interrupt priority levels.

Using a modular design approach, the following peripherals were integrated with the SAM87 core to make the
KS88C8424/C8432/P8432 microcontrollers suitable for use in color television and other types of screen display
applications:

— Four programmable I/O ports (26 pins total: 16 general-purpose I/O pins; 10 n-channel, open-drain

output pins)
— 4-bit resolution A/D converter (4 channels)
— 14-bit PWM output (Two channels: push-pull type, open-drain type)
— Basic timer (BT) with watchdog timer function
— One 8-bit timer/counter (T0) with interval timer and PWM mode
— One 8-bit general-purpose timer/counter (TA) with prescalers
— On-screen display (OSD) with a wide range of programmable features, including halftone control

signal output
The KS88C8424 and the KS88C8432 are available in versatile 42-pin SDIP package.

OTP

The KS88C8424/C8432 microcontrollers are also available in OTP (One Time Programmable) version, named
the KS88P8432. The KS88P8432 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM
instead of a masked ROM. The KS88P8432 is comparable to the KS88C8424/C8432, both in function and pin
configuration.

1-1

PRODUCT OVERVIEW KS88C8424/C8432/P8432

FEATURES

CPU

• SAM87 CPU core

Memory

• 24-Kbyte (KS88C8424) or 32-Kbyte (KS88C8432)
internal program memory

• 272-byte general-purpose register area

Instruction Set

• 78 instructions

• IDLE and STOP instructions added for power­down modes

Instruction Execution Time

• 750 ns (minimum) with an 8 MHz CPU clock

Interrupts

• 9 interrupt sources with 9 vectors

• 7 interrupt levels

• Fast interrupt processing for select levels

General I/O

• Four I/O ports (26 pins total)

• Six open-drain pins for up to 6 V loads

• Four open-drain pins for up to 5 V loads

Pulse Width Modulation Module

• 14-bit PWM with two-channel output (push-pull
type, open-drain type)

• 8-bit PWM with four-channel, push-pull and open­drain

• PWM counter and data capture input pin

• Frequency: 5.859 kHz to 23.437 kHz with a 6 MHz
CPU clock

On-Screen Display (OSD)

• Video RAM: 252 × 13-bits

• Character generator ROM: 384 × 18 × 16-bits
(384 display characters; fixed; 2, variable; 382)

• 252 display positions (12 rows × 21 columns)

• 16-dot × 18-dot character resolution

• 16 different character sizes

• Eight character colors

• Vertical direction fade-in/fade-out control

• Eight colors for character and frame background

• Halftone control signal output; selectable for
individual characters

• Synchronous polarity selector for H-sync and
V-sync input

8-Bit Basic Timer

• Three selectable internal clock frequencies

• Watchdog or oscillation stabilization function

Timer/Counters

• One 8-bit timer/counter (T0) with three internal
clocks or an external clock and interval timer
mode or PWM mode.

• One general-purpose 8-bit timer/counters with
interval timer mode (timer A)

A/D Converter

• Four analog input pins; 4-bit resolution

• 3.125 µs conversion time (8 MHz CPU clock)

1-2

Oscillator Frequency

• 5 MHz to 8 MHz external crystal oscillator

• Maximum 8 MHz CPU clock

Operating Temperature Range

• – 20°C to + 85°C

Operating Voltage Range

• 4.5 V to 5.5 V

Package Type

• 42-pin SDIP

KS88C8424/C8432/P8432 PRODUCT OVERVIEW

BLOCK DIAGRAM

X

OSC

OSC

H-sync

V-sync

Vgreen

Vblue

Vblank

OSDHT

ADC0
ADC1

ADC2
ADC3

X

IN

OUT

IN

OUT

Vred

RESET

INT0 - INT3

Main

Osc

L-C Osc

On-

Screen

Display

4-Bit

ADC

P0.0 - P0.7

Port 0 Port 1

SAM87 Bus

Port I/O and Interrupt

Control

SAM87 CPU

24/32-KByte

ROM

SAM87 Bus

Port 2

P1.0 - P1.7

272-Byte Register

File

Port 3

Test

Timer A

Timer 0

PWM

Block

PWM

Counter

and Data

Capture

14-Bit

PWM

8-Bit

PWM

TO
T0CK

CAPA

PWM0
PWM1

PWM2
PWM3
PWM4
PWM5

P2.0 - P2.7

Figure 1-1. Block Diagram

P3.0 - P3.1

1-3

PRODUCT OVERVIEW KS88C8424/C8432/P8432

PIN ASSIGNMENTS

P2.5/PWM0
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.0/PWM5

P2.6/T0

P1.7/T0CK
P3.0/ADC0
P3.1/ADC1
P0.6/ADC2
P0.7/ADC3

TEST

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3

P1.4
P1.5
P1.6

P2.7/OSDHT

1
2
3
4
5
6
7
8
9

KS88C8424/

10

C8432/P8432

11

42-PIN SDIP

12
13
14
15
16
17
18
19
20
21

(Top View)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P0.0
P0.1
P0.2
P0.3
P0.4
V

SS2

CAPA
P0.5
V

DD

RESET

X

OUT

X

IN

V

SS1

OSC
OSC
V-sync
H-sync
Vblank
Vred
Vgreen
Vblue

OUT
IN

1-4

Figure 1-2. KS88C8424/C8432/P8432 Pin Assignment Diagram

KS88C8424/C8432/P8432 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. KS88C8424/C8432/P8432 Pin Descriptions

Pin Name Pin

Type

P0.0–P0.3 I/O General I/O port (4-bit), configurable for

digital input or n-channel open-drain, push­pull output.
Pins can withstand up to 5 V loads.

P0.4–P0.5 General I/O port (2-bit), configurable for

digital input or push-pull output.

P0.6–P0.7 General I/O port (2-bit), configurable for

digital input or n-channel open-drain output.
P0.6–P0.7 can withstand up to 5 V loads.
Multiplexed for alternative use as external
inputs, ADC2–ADC3.

P1.0–P1.3 I/O General I/O port (4-bit), configurable for

digital input or n-channel open-drain output.
P1.0–P1.3 can withstand up to 6 V loads.
Multiplexed for alternative use as external
interrupt inputs, INT0–INT3.

P1.4–P1.5 General I/O port (2-bit), configurable for

digital input or n-channel open-drain output.
P1.4–P1.5 can withstand up to 6 V loads.
High current port(10mA)

P1.6–P1.7 General I/O port (2-bit), configurable for

digital input or push-pull output.
Each pin has an alternative function.
P1.7: T0CK (Timer 0 clock input)

P2.0–P2.7 I/O General I/O port (8-bit). Input/output mode

or n-channel open-drain, push-pull output
mode are software configurable. Pins can
withstand up to 5 V loads.
Each pin has an alternative function.
P2.0: PWM5 (8-bit PWM output)
P2.1: PWM1 (14-bit PWM output)
P2.2: PWM2 (8-bit PWM output)
P2.3: PWM3 (8-bit PWM output)
P2.4: PWM4 (8-bit PWM output)
P2.5: PWM0 (14-bit PWM output)
P2.6: T0 (Timer 0 PWM and interval output)
P2.7: OSDHT (Halftone signal output)

P3.0–P3.1 I/O General I/O port (2-bit), configurable for

digital input or n-channel open-drain output.
P3.0–P3.1 can withstand up to 5 V loads.
Multiplexed for alternative use as external
inputs ADC0–ADC1.

Pin Description Circuit

Type

2 39–42

3 38, 35

6 11–12

7 14–17

5 18–19

3 20, 8

2 1–7, 21

6 9–10

Pin

Numbers

Share

Pins

(See pin

description)

ADC2–ADC3

INT0–INT3

T0CK

PWM0–

PWM5

T0, OSDHT

ADC0–ADC1

1-5

PRODUCT OVERVIEW KS88C8424/C8432/P8432

Table 1-1. KS88C8424/C8432/P8432 Pin Descriptions (Continued)

Pin Name Pin

PWM0–

Type

O Output pin for 14-bit PWM circuit 2 1, 2 P2.5, P2.1

Pin Description Circuit

Type

Pin

Numbers

Share

Pins

PWM1
PWM2–

PWM5

O Output pin for 8-bit PWM circuit 2 3–6 P2.2–P2.4,

P2.0

ADC0–ADC3 I Analog inputs for 4-bit A/D converter 6 9–12 P3.0–P3.1,

P0.6–P0.7
INT0–INT3 I External interrupt input pins 7 14–17 P1.0–P1.3
T0 O Timer 0 output (interval, PWM) 2 7 P2.6
T0CK I Timer 0 clock input 3 8 P1.7
OSDHT O Halftone control signal output for OSD 2 21 P2.7
Vblue, Vgreen

Vred, Vblank
H-sync,

O Digital blue, green, red, and video blank

4 22–25 –

signal outputs for OSD

I H-sync, V-sync input for OSD 1 26, 27 –

V-sync
OSCIN,

OSC

OUT

XIN, X

OUT

RESET

TEST –

I, O L-C oscillator pins for OSD clock frequency

– 28, 29 –

generation

I, O System clock pins – 31, 32 –

I System reset input pin 8 33 –

Test Pin (must be connected to VSS).

– 13 –

Factory test mode is activated when 12V is
applied.

VDD, V
V

SS2

SS1,

– Power supply pins – 34, 30, 37 –

CAPA I Input for capture A module 1 36 –

1-6

KS88C8424/C8432/P8432 PRODUCT OVERVIEW

PIN CIRCUITS

Input

Noise

Filter

Figure 1-3. Pin Circuit Type 1 (V-Sync H-Sync, CAPA)

V

DD

Data

I/O

Open-drain

Output

Disable

V

SS

Input

Figure 1-4. Pin Circuit Type 2 (P2.0–P2.7, P0.0–P0.3, PWM0–PWM5, T0, OSDHT)

1-7

PRODUCT OVERVIEW KS88C8424/C8432/P8432

V

DD

Data I/ O

V

SS

Input

Figure 1-5. Pin Circuit Type 3 (P0.4–P0.5, P1.6–P1.7, T0CK)

V

DD

Data Output

V

SS

Figure 1-6. Pin Circuit Type 4 (Vblue, Vgreen, Vred, Vblank)

1-8

KS88C8424/C8432/P8432 PRODUCT OVERVIEW

I/O

Data

V

SS

Input

NOTE: Circuit type 5 can withstand up to 6 V loads.

Figure 1-7. Pin Circuit Type 5 (P1.4–P1.5)

I/O

Data

V

SS

Input

A/D In

NOTE: Circuit type 6 can withstand up to 5 V loads.

Figure 1-8. Pin Circuit Type 6 (P3.0–P3.1, P0.6–P0.7, ADC0–ADC3)

1-9

PRODUCT OVERVIEW KS88C8424/C8432/P8432

I/O

Data

V

SS

Input

INT Noise Filter

NOTE: Circuit type 7 can withstand up to 6 V loads.

Figure 1-9. Pin Circuit Type 7 (P1.0–P1.3, INT0–INT3)

200 K

Ω

Input

Noise

Filter

Figure 1-10. Pin Circuit Type 8 (RESET)

1-10

KS88C8424/C8432/P8432 ELECTRICAL DATA

15 ELECTRICAL DATA

OVERVIEW

In this section, the KS88C8424 and the KS88C8432 electrical characteristics are presented in tables and graphs.
The information is arranged in the following order:

— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Input timing measurement points for t

— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by RESET
— Main oscillator and L-C oscillator frequency
— Clock timing measurement points for X

— Main oscillator clock stabilization time (tST)
— A/D converter electrical characteristics

— Characteristic curves

NF1

IN

and t

NF2

15-1

ELECTRICAL DATA KS88C8424/C8432/P8432

Table 15-1. Absolute Maximum Ratings

(TA = 25°C)

Parameter Symbol Conditions Rating Unit

Supply Voltage V
Input Voltage V

Output Voltage V
Output Current

I

DD

V

OH

I1
I2
O

P1.0–P1.5 (open-drain) – 0.3 to + 7 V
All port pins except V
All output pins – 0.3 to VDD + 0.3 V
One I/O pin active – 18 mA

– – 0.3 to + 6.0 V

I1

– 0.3 to VDD + 0.3

High

All I/O pins active – 60

Output Current

I

OL

One I/O pin active + 30 mA

Low

Total pin current for port 1 + 100
Total pin current for ports 0, 2, and 3 + 100

Operating

T

A

– – 20 to + 85 °

C

Temperature
Storage

T

STG

– – 65 to + 150 °

C

Temperature

Table 15-2. D.C. Electrical Characteristics

(T

= – 20°C to + 85°C, VDD = 4.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High
Voltage

Input Low Voltage V

Output High
Voltage

V

IH1

V

IH2
IL1

V

IL2

V

OH

All input pins except V

X

IN, XOUT

All input pins except V
X

IN, XOUT

IOH = – 500 µA

IH2

IL2

0.8 V

DD

– V

DD

2.7 V
– – 0.2 V

1.0 V

V

– 0.8 – – V

DD

DD

P0.0–P0.5, P1.6–P1.7, P2
R, G, B, Vblank

Output Low
Voltage

V

V

OL1

OL2

IOL = 4 mA
P0.0–P0.5, P1.6–P1.7

IOL = 10 mA

– – 0.4 V

– – 0.8

P1.4–P1.5

V

OL3

IOL = 2 mA

– – 0.4

P1.0–P1.3, P3.0–P3.1,
P0.6–P0.7

V

OL4

IOL = 1 mA

– – 0.4 V

R, G, B, Vblank, P2

V

V

15-2

KS88C8424/C8432/P8432 ELECTRICAL DATA

Table 15-2. D.C. Electrical Characteristics (Continued)

(T

= – 20°C to + 85°C, VDD = 4.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High
Leakage Current

Input Low
Leakage Current

Output High
Leakage Current

I

LIH1

I

LIH2

I

LIH3

I

LIL1

I

LIL2

I

LIL3

I

LOH1

I

LOH2

VIN = V
All input pins except I
and I

DD

LIH2

LIH3

VIN = VDD, OSCIN, OSC
VIN = VDD, X
V

= 0 V

IN

All input pins except I
I

, and RESET

LIL3

V

= 0 V,

IN

OSCIN, OSC
V

= 0 V, X

IN

V

OUT

All output pins except I
V

OUT

= V

= 6 V

IN, XOUT

LIL2

OUT

IN, XOUT

DD

LOH2

OUT

,

– – 3 µA

10

2.5 10 20
– – – 3 µA

– 10

– 2.5 – 10 – 20

– – 3 µA

10

P1.0–P1.5

Output Low
Leakage Current

Supply Current

(note)

I

LOL

I

DD1

V

= 0 V

OUT

All output pins
Normal mode;

V

= 4.5 V to 5.5 V

DD

– – – 3 µA

– 7 20 mA

8-MHz CPU clock

I

DD2

Idle mode;
V

= 4.5 V to 5.5 V

DD

2 10

8-MHz CPU clock

I

DD3

NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads.

Stop mode;
V

= 4.5 V to 5.5 V

DD

1 10 µA

15-3

ELECTRICAL DATA KS88C8424/C8432/P8432

Table 15-3. Input/Output Capacitance

(TA = – 20°C to + 85°C, V

DD

= 0 V)

Parameter Symbol Conditions Min Typ Max Unit

Input
capacitance

Output

C

C

IN

OUT

f = 1 MHz; unmeasured pins

are connected to V

SS

– – 10 pF

capacitance
I/O capacitance C

IO

Table 15-4. A.C. Electrical Characteristics

(T

= – 20°C to + 85°C, V

A

= 4.5 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

V-sync Pulse

t

VW

– 4 – – µs

Width
H-sync Pulse

t

HW

– 3 – – µs

Width
Noise Filter t

NOTE: f

CAPA

= f

OSC

/128

NF1

t

NF2

t

NF3

t

NF4

P1.0–P1.3 – 350 – ns

RESET, H-sync, V-sync – 1000

Glitch filter (oscillator block) – 25
CAPA – 5 – t

CAPA

15-4

1t

CPU

t

NF1L

t

NF2

0.8

0.2

t

NF1H

V

DD

V

DD

Figure 15-1. Input Timing Measurement Points for t

NF1

and t

NF2

KS88C8424/C8432/P8432 ELECTRICAL DATA

Table 15-5. Data Retention Supply Voltage in Stop Mode

(TA = – 20 °C to + 85 °C)

Parameter Symbol Conditions Min Typ Max Unit

Data Retention

V

DDDR

Stop mode 2 – 6 V

Supply Voltage
Data Retention

I

DDDR

Stop mode, V

= 2.0 V – – 5 µA

DDDR

Supply Current

NOTES:

1. Supply current does not include the current drawn through internal pull-up resistors or external output current loads.

2. During the oscillator stabilization wait time (t

~

~

V

DD

~

~

), all the CPU operations must be stopped.

WAIT

STOP MODE

DATA RETENTION MODE

t

SREL

OSCILLATION
STABILIZATION
TIME

NORMAL
OPERATING
MODE

RESET

V

EXECUTION OF

STOP INSTRUCTION

NOTE: t

is the same as 4096 x 16 x 1 / f

WAIT

DDDR

OSC

Figure 15-2. Stop Mode Release Timing When Initiated by a RESET

t

WAIT

15-5

ELECTRICAL DATA KS88C8424/C8432/P8432

Table 15-6. Main Oscillator and L-C Oscillator Frequency

(TA = – 20°C + 85°C, V

= 4.5 V to 5.5 V)

DD

Oscillator Clock Circuit Conditions Min Typ Max Unit

Crystal

C1

C2

X

X

IN

OUT

OSD block active 5 6 8 MHz

OSD block inactive 0.5 6 8

Ceramic

C1

C2

X

X

IN

OUT

OSD block active 5 6 8 MHz

OSD block inactive 0.5 6 8

External Clock

X

X

IN

OUT

OSD block active 5 6 8 MHz

OSD block inactive 0.5 6 8

L-C Oscillator

C1

C2

OSC

OSC

Recommend value;
C1 = C2 = 20 pF

IN

OUT

5 6.5 8 MHz

CPU Clock Frequency – 0.032 6.0 8 MHz

15-6

1 / f

OSC

t

XL

X

IN

t

XH

2.7 V

1.0 V

Figure 15-3. Clock Timing Measurement Points for X

IN

KS88C8424/C8432/P8432 ELECTRICAL DATA

Table 15-7. Main Oscillator Clock Stabilization Time

(TA = – 20°C + 85°C, VDD = 4.5 V to 5.5 V)

Oscillator Symbol Test Condition Min Typ Max Unit

Crystal – VDD = 4.5 V to 6.0 V – – 20 ms
Ceramic (Oscillation stabilization occurs when

10

VDD is equal to the minimum
oscillator voltage range.)

External Clock XIN input High and Low level width

65 – 100 ns

(tXH, tXL)

Release Signal

t

SREL

Normal operation – 1000 – ns

Setup Time
Oscillation

Stabilization
Wait Time

(1)

t

WAIT

CPU clock = 8 MHz; Stop mode
released by RESET

CPU clock = 8 MHz; Stop mode

– 8.3 – ms

(2)

released by an interrupt

NOTES:

1. Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a
power-on occurs, or when Stop mode is released.

2. The oscillation stabilization interval is determined by the basic timer (BT) input clock setting.

Table 15-8. A/D Converter Electrical Characteristics

(T

= – 20°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Absolute
Accuracy

(1)

Conversion

(2)

Time
Analog Input

– CPU clock = 8 MHz – –

t

CON

V

IAN

– V

t

CPU

× 25

(3)

SS

± 0.5

– µs

– V

DD

Voltage
Analog Input

R

AN

– 2 –

Impedance

NOTES:

1. Excluding quantization error, absolute accuracy values are within ± 1/2 LSB.

2. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.

3. The unit t

means one CPU clock period.

CPU

LSB

V

MΩ

15-7

ELECTRICAL DATA KS88C8424/C8432/P8432

NOTES

15-8

KS88C8424/C8432/P8432 MECHANICAL DATA

16 MECHANICAL DATA

OVERVIEW

The KS88C8424 and the KS88C8432 microcontrollers are available in 42-pin SIP package
(42-SDIP-600).

42 22

42-SDIP-600

14.00 ± 0.2

#1 21

39.10 ± 0.2

(1.77)

0.50 ± 0.1

NOTE: Package dimensions are in millimeters.

1.00 ± 0.1

1.778

15.24

0.51MIN 3.50 ± 0.2

3.30 ± 0.3 5.08MAX

+0.1

– 0.05

0.25

0 ~ 15

°

Figure 16-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)

16-1

MECHANICAL DATA KS88C8424/C8432/P8432

NOTES

16-2

KS88C8424/C8432/P8432 KS88P8432 OTP

17 KS88P8432 OTP

OVERVIEW

The KS88P8432 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

KS88C8424/C8432 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is
accessed by serial data format.

The KS88P8432 is fully compatible with the KS88C8424/C8432, both in function and pin configuration. The
simple programming requirements of the KS88P8432 make the device ideal for use as an evaluation chip for the
KS88C8424/C8432.

17-1

KS88P8432 OTP KS88C8424/C8432/P8432

P2.5/PWM0

P2.1

SCLK/ P2.2

SDAT/P2.3

P2.4
P2.0
P2.6

P1.7
P3.0/ADC0
P3.1/ADC1

P0.6

P0.7

TEST/TEST

P1.0/INT0
P1.1/INT1

P1.2

P1.3

P1.4

P1.5

P1.6

P2.7/OSDHT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

KS88P8432

42-PIN SDIP

(Top View)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P0.0
P0.1
P0.2
P0.3
P0.4
V

SS2/VSS

CAPA
P0.5
VDD/VDD

RESET

RESET

/

X

OUT

X

IN

V

SS1/VSS

OSC

OUT

OSC

IN

V-sync
H-sync
Vblank
Vred
Vgreen
Vblue

Figure 17-1. KS88P8432 Pin Assignment (42-SDIP)

17-2

KS88C8424/C8432/P8432 KS88P8432 OTP

Table 17-1. Descriptions of Pins Used to Read/Write the EPROM (KS88P8432)

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P2.3 (Pin 4) SDAT 4 I/O Serial data pin (output when reading, Input when

writing) Input and push-pull output port can be
assigned

P2.2 (Pin 3) SCLK 3 I/O Serial clock pin (Input only pin)

V

TEST

PP

(TEST)

13 I 0 V: operating mode

5 V: test mode

12.5 V: OTP mode

RESET RESET

VDD/V

SS

VDD/V

SS

33 I 5 V: operating mode, 0 V: OTP mode

34/30, 37 I Logic power supply pin.

Table 17-2. Comparison of KS88P8432 and KS88C8424/C8432 Features

Characteristic KS88P8432 KS88C8424/C8432

Program Memory 32-Kbyte EPROM 24/32-Kbyte mask ROM
Operating Voltage (VDD)

OTP Programming Mode

4.5 V to 5.5 V 4.5 V to 5.5 V
VDD = 5 V, TEST VPP = 12.5 V

–

Pin Configuration 42 SDIP 42 SDIP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP(TEST) pin of the KS88P8432, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 16-3 below.

Table 17-3. Operating Mode Selection Criteria

V

DD

VPP

(TEST)

REG/
MEM

ADDRESS

(A15-A0)

R/W MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

17-3

KS88P8432 OTP KS88C8424/C8432/P8432

NOTES

17-4