Datasheet KS88P4716, KS88C4716, KS88C4708 Datasheet (Samsung)

KS88C4708/C4716/P4716 (Preliminary Spec) PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM87RC PRODUCT FAMILY

Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a
wide range of integrated peripherals, and various mask-programmable ROM sizes.

Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RC
microcontrollers have an external interface that provides access to external memory and other peripheral devices.

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
one interrupt level at a time.

KS88C4708/C4716 MICROCONTROLLER

The KS88C4708/C4716 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter,
UART, PWM application field. Its powerful SAM87RC CPU architecture includes. The internal register file is
logically expanded to increase the on-chip register space.

The KS88C4708/C4716 has 8/16 K bytes of on-chip program ROM. Following Samsung's modular design
approach, the following peripherals are integrated with the SAM87RC core:

— Large number of programmable I/O ports (42 SDIP: 34 pins, 44 QFP: 36 pins)
— One asynchronous UART module
— Analog-to-digital converter with eight input channels and 10-bit resolution
— One 8-bit basic timer for watchdog function
— One 8-bit timer/counter with three operating modes (Timer 0)
— One general-purpose 16-bit timer/counters with three operating modes (Timer 1)

The KS88C4708/C4716 is a versatile general-purpose microcontroller that is ideal for use in a wide range of
electronics applications requiring complex timer/counter, PWM, capture, and UART.
It is available in a 42-pin SDIP or 44-pin QFP package.

OTP

The KS88P4716 is an OTP (One Time Programmable) version of the KS88C4708/C4716 microcontroller. The
KS88P4716 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of a masked
ROM. The KS88P4716 is comparable to the KS88C4708/C4716, both in function in D.C. electrical characteristics
and in pin configuration.

1-1

PRODUCT OVERVIEW KS88C4708/C4716/P4716 (Preliminary Spec)

FEATURES

CPU

• SAM87RC CPU core

Memory

• 272-byte general purpose register area

• 8/16-Kbyte internal program memory

Instruction Set

• 79 instructions

• IDLE and STOP instructions added for
power-down modes

Instruction Execution Time

• 333 ns at 12 MHz f

(minimum)

OSC

Interrupts

• 14 interrupt sources and 14 vectors

• Eight interrupt levels

• Fast interrupt processing

General I/O

• Five I/O ports (total 36 pins)

• Four bit-programmable ports

• Two n-channel open-drain output port

Timer/Counters

• One 8-bit basic timer for watchdog function

• One 8-bit timer/counter with three operating
modes (timer 0)

• One 16-bit general-purpose timer/counters with
three operation modes (timer 1)

UART

• One UART module

• Full duplex serial I/O interface with three UART
modes

A/D Converter

• Eight analog input pins

• 10-bit conversion resolution

• 20 µs conversion time (10 MHz CPU clock)

Buzzer Frequency Output

• 200 Hz to 20 kHz signal can be generated

Oscillator Frequency

• 1 MHz to 12 MHz external crystal oscillator

• Maximum 12 MHz CPU clock

Operating Temperature Range

• – 40°C to + 85°C

Operating Voltage Range

• 1.8 V to 5.5 V

Package Types

• 42-pin SDIP, 44-pin QFP

1-2

KS88C4708/C4716/P4716 (Preliminary Spec) PRODUCT OVERVIEW

BLOCK DIAGRAM

P1.0-P1.5

T0, T1CK, T1,

P0.0-P0.7

BUZ, RxD, TxD

X

X

OUT

T0(CAP)

T0(PWM)

T1(CAP)

T1(PWM)

ADC0-ADC7

P1.4/RxD

P1.5/TxD

P1.3/BUZ

Basic
Timer

IN

OSC

Timer 0

Timer 1

ADC

UART

BUZ

Port 0

Port I/O and Interrupt

Control

SAM87RC CPU

8/16-Kbyte

ROM

Port 1

272-byte
Register

File

Port 2

Port 3

Port 4

P2.0-P2.7
INT0-INT7

P3.0-P3.7
ADC0-ADC7

P4.0-P4.3

P4.4-P4.5

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW KS88C4708/C4716/P4716 (Preliminary Spec)

PIN ASSIGNMENTS

P1.0/T0

P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P4.3
P4.2

V

DD

V

SS

X

OUT

X

TEST

P4.1
P4.0

RESET

P2.0/INT0
P2.1/INT1
P2.2/INT2

1
2
3
4
5
6
7
8
9
10
11
12
13

IN

14
15
16
17
18
19
20
21

KS88C4708
KS88C4716

(42-SDIP-600)

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

P1.1/T1CK
P1.2/T1
P1.3/BUZ
P1.4/RxD
P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AV

SS

AV

REF

P2.7/INT7
P2.6/INT6
P2.5/INT5
P2.4/INT4
P2.3/INT3

1-4

Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)

KS88C4708/C4716/P4716 (Preliminary Spec) PRODUCT OVERVIEW

P2.0/INT0

P2.1/INT1

P2.2/INT2

P2.3/INT3

P2.4/INT4

P2.5/INT5

P2.6/INT6

P2.7/INT7

P4.4

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0/T0(CAP/PWM)

P1.1/T1CK

P1.2/T1(CAP/PWM)

P1.3/BUZ

4443424140393837363534

P1.4/RxD

P0.1
P0.0
P4.3
P4.2

V

DD

V

SS

X

OUT

X

TEST

P4.1
P4.0

1
2
3
4
5
6
7

IN

8
9
10
11

KS88C4708
KS88C4716

(44-QFP-1010)

1213141516171819202122

33
32
31
30
29
28
27
26
25
24
23

P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AV

SS

P4.5

RESET

AVREF

Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

1-5

PRODUCT OVERVIEW KS88C4708/C4716/P4716 (Preliminary Spec)

Table 1-1. KS88C4708/C4716 Pin Descriptions

Pin

Name

P0.0–P0.7 I/O Nibble-programmable I/O port for Schmitt trigger

P1.0–P1.5 I/O Bit-programmable I/O port for Schmitt trigger input

Pin

Type

Pin Description Circuit

input or push-pull, open-drain output. Pull-up
resistors are assignable by software.

or push-pull output. Pull-up resistors are assignable
by software. Port 1 pin can also by used as

Number

E 8-1

D 42-37

Pin

Number

(2-1,

43-38)

(37-32)

Share

Pins

–

T0, T1CK,

T1, BUZ,

RxD, TxD

alternative function (T0, T1CK, T1, BUZ, RxD, TxD)

P2.0–P2.7 I/O Bit-programmable I/O port for Schmitt trigger input

or push-pull output. Pull-up resistors are assignable

D 19-26

(13-20)

INT0-

INT7
by software. Port 2 pins can also be used as
external interrupt.

P3.0–P3.7 I/O Bit-programmable I/O port for Schmitt trigger input

or push-pull output. Pull-up resistors are assignable

F 29-36

(24-31)

ADC0-

ADC7
by software. Port 3 pins can also be used as A/D
converter by software.

P4.0–P4.3 I/O Bit-programmable I/O port for Schmitt trigger input

or push-pull, open-drain output. Pull-up resistors
are assingable by software.

E 17-16,

10-9

(11-10,

–

4-3)
P4.4–P4.5 O Push-pull output only C (44, 21) –
X

IN, XOUT

– Crystal or ceramic oscillator signal for system clock. – 14, 13

–

(8, 7)

RESET

TEST I Test signal input pin (for factory use only; muse be

I System reset signal input pin. B 18 (12) –

– 15 (9) –

connected to VSS)

AV

REF,

AV

SS

V

DD, VSS

– A/D converter reference voltage input and ground – 27, 28

(22, 23)

– Voltage input pin and ground – 11, 12

–

–

(5, 6)
T0 I/O Timer 0 capture input or PWM output pin D 42 (37) P1.0
T1CK I Timer 1 external clock input pin D 41 (36) P1.1
T1 I/O Timer 1 capture input or PWM output pin D 40 (35) P1.2
BUZ O 200 Hz-20 KHz frequency output for buzzer sound D 39 (34) P1.3
RxD I/O UART receive and transmit input or output D 38 (33) P1.4
TxD O UART transmit output D 37 (32) P1.5
INT0-INT7 I External interrupt input E 19-26

P2.0-P2.7

(13-20)

ADC0­ADC7

I A/D converter input F 29-36

(24-31)

P3.0-P3.7

NOTE: Pin numbers shown in parentheses "( )" are for the 44-pin QFP package.

1-6

KS88C4708/C4716/P4716 (Preliminary Spec) PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

DD

V

P-Channel

In

N-Channel

Figure 1-4. Pin Circuit Type A

V

DD

Pull-Up
Resistor

In

Schmitt Trigger

Data

Output

DIsable

Pull-up
Enable

Data

Output

DIsable

Data

P-Channel

N-Channel

Figure 1-6. Pin Circuit Type C

V

DD

Circuit

Type C

Out

In/Out

Figure 1-5. Pin Circuit Type B

Figure 1-7. Pin Circuit Type D

1-7

PRODUCT OVERVIEW KS88C4708/C4716/P4716 (Preliminary Spec)

V

DD

Data

Output

DIsable

PNE

Schmitt Trigger

Figure 1-8. Pin Circuit Type E

V

DD

47 K

Pull-up
Enable

P-CH

In/Out

N-CH

V

DD

1-8

Pull-up

Enable

Data

Output

Circuit

Type C

DIsable

Data

TO ADC

Figure 1-9. Pin Circuit Type F

In/Out

KS88C4708/C4716/P4716 (Preliminary Spec) ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this chapter, KS88C4708/C4716 electrical characteristics are presented in tables and graphs. The information
is arranged in the following order:

— Absolute maximum ratings
— Input/output capacitance
— D.C. electrical characteristics
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
— Data retention supply voltage in stop mode
— UART timing characteristics in mode 0
— A/D converter electrical characteristics

14-1

ELECTRICAL DATA KS88C4708/C4716/P4716 (Preliminary Spec)

Table 14-1. Absolute Maximum Ratings

(TA = 25 °C)

Parameter Symbol Conditions Rating Unit

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

DD

V

All ports

I

V

I

All output ports

O

One I/O pin active – 18 mA

OH

– – 0.3 to + 6.5 V

– 0.3 to VDD + 10

– 0.3 to VDD + 0.3

V
V

All I/O pins active – 60

Output Current Low

I

One I/O pin active + 30 mA

OL

Total pin current for ports 1, 2, and 3 + 100
Total pin current for ports 0 and 4 + 200

Operating

T

A

– – 40 to + 85

°

C

Temperature
Storage Temperature

T

STG

– – 65 to + 150

°

C

14-2

KS88C4708/C4716/P4716 (Preliminary Spec) ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics

(T

= − 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

A

Parameter Symbol Test Conditions Min Typ Max Unit

Input High
Voltage

Input Low
Voltage

Output High

V

Ports 0, 1, 2, 3 ,4

IH1

and RESET

V
V

X

IH3

IL1

IN,

Ports 0, 1, 2, 3, 4

and X

OUT

and RESET
V
V

XIN and X

IL3

IOH = – 1 mA V

OH

OUT

V

= 2.7 to 5.5 V 0.8 V

DD

V

= 2.7 to 5.5 V

DD

= 4.5 to 5.5 V V

DD

DD

–

VDD–0.1

– – 0.2

DD

1.0

–

– –

V

V

0.1

DD

DD

V

V

Voltage Ports 0, 1, 2, 3, 4
Output Low

V

OL1IOL

= 15 mA VDD = 4.5 to 5.5 V

– 0.4 2.0 V

Voltage

Port 0, and 4

V

OL2IOL

= 4 mA VDD = 4.5 to 5.5 V

0.4 2.0 V

Ports 1, 2, and 3

Input High
Leakage Current

Input Low
Leakage Current

Output High

I

LIH1

I

LIH2

I

LIL1

I

LIL2

I

LOH

All input pins except

I

and RESET

LIH2

X

and X

IN,

OUT

All input pins except

I

LIL2

X

and X

IN,

OUT

All output pins

VIN = V

VIN = V
VIN = 0 V

VIN = 0 V
V

= V

OUT

DD

DD

DD

– – 1 uA

20

– – – 1 uA

– 20

– – 2 uA

Leakage Current
Output Low

I

LOL

All output pins

V

OUT

= 0 V

– – – 2 uA

Leakage Current
Pull-up Resistor

Supply Current

R
R

I

DD1

VIN = 0 V, Ports 0-4 VDD = 5 V

P1

RESET

P1

RUM mode

VDD = 5 V
VDD = 4.5 to 5.5 V

30 47 70

100 200 350

– 10 20 mA

KΩ

12 MHz CPU clock

VDD = 1.8 to 2.2 V
VDD = 4.5 to 5.5 V

1.1 3

– 4 8

I

DD2

3 MHz CPU clock

Idle mode

12 MHz CPU clock

VDD = 1.8 to 2.2 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 2.2 V

0.6 1.5

– 0.1 5 uA

0.1 3

I

DD3

3 MHz CPU clock

Stop mode

14-3

ELECTRICAL DATA KS88C4708/C4716/P4716 (Preliminary Spec)

Table 14-3. A.C. Electrical Characteristics

(T

= − 40 °C to + 85 °C, VDD = 4.5 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Interrupt Input
High, Low Width

Input

Low Width

t

INTH

t

INTL

t

RSL

Ports 2

,

VDD = 5 V ± 10 %
Input

VDD = 5 V ± 10 %

t

INTL

t

RST

0.8 V

0.2 V

– 200 – ns

– 1 –

t

INTH

DD

DD

µs

Figure 14-1. Input Timing Measurement Points

14-4

KS88C4708/C4716/P4716 (Preliminary Spec) ELECTRICAL DATA

Table 14-4. Oscillation Characteristics

(TA = – 40 °C + 85 °C)

Oscillator Clock Circuit Test Condition Min Typ Max Unit

Main Crystal or
Ceramic

X

IN

C1 C2

X

OUT

VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
VDD = 1.8 V to 2.7 V

1 – 12 MHz

8
3

External Clock
(Main System)

XINX

OUT

VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
VDD = 1.8 V to 2.7 V

1 – 12 MHz

8
3

14-5

ELECTRICAL DATA KS88C4708/C4716/P4716 (Preliminary Spec)

Main Oscillator Frequency

CPU Clock

12 kHz
10 kHz

8 kHz
6 kHz
4 kHz
2 kHz

1 2 3 4 5 6 7

1.8 V 2.7 V
Supply Voltage (V)

CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)

(Divided by 4)

Figure 14-2. Operating Voltage Range

Table 14-5. Oscillation Stabilization Time

(T

= – 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)

A

Oscillator Test Condition Min Typ Max Unit

f

Main Crystal
Main Ceramic

> 1.0 kHz;

OSC

Oscillation stabilization occurs when VDD is equal

– – 20 ms
– – 10 ms

to the minimum oscillator voltage range.

External Clock

XIN input High and Low width (tXH, tXL)

25 – 500 ns

(Main System)
Oscillator
Stabilization

Wait Time

NOTES:

1. f

2. The duration of the oscillator stabilization wait time, t

is the oscillator frequency.

OSC

settings in the basic timer control register, BTCON.

t

when released by a reset

WAIT

t

when released by an interrupt

WAIT

(1)

(2)

, when it is released by an interrupt is determined by the

WAIT

–

216/f

OSC

–

–

– ms
– ms

14-6

KS88C4708/C4716/P4716 (Preliminary Spec) ELECTRICAL DATA

Table 14-6. UART Timing Characteristics in Mode 0 (10 MHz)

(T

= – 40°C to + 85°C, V

A

= 1.8 V to 5.5 V, Load capacitance = 80 pF)

DD

Parameter Symbol Min Typ Max Unit

Serial port clock cycle time
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Serial port clock High, Low level width

NOTES:

1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.

2. The unit t

means one CPU clock period.

CPU

t

SCK

t

S1

t

S2

t

H1

t

H2

t

HIGH, tLOW

500
300

t

CPU

t

CPU

× 6
× 5

– – 300

t

– 50 t

CPU

CPU

0 – –

200

t

CPU

× 3

700 ns

–

–

400

0.8 V

DD

t

HIGH

0.2 V

DD

t

LOW

t

SCK

Figure 14-3. Waveform for UART Timing Characteristics

14-7

ELECTRICAL DATA KS88C4708/C4716/P4716 (Preliminary Spec)

CLOCK

SHIFT

t

SCK

IN

NOTE: The symbols shown in this diagram are defined as follows:

t

t

t

t

t

H1

H2

Output data hold after clock rising edge

Input data hold after clock rising edge

SCK

S1

S2

Serial port clock cycle time

Output data setup to clock rising edge

Clock rising edge to input data valid

VALID

VALID VALID VALID VALID VALID VALID VALID

DATA

S2

H2

DATA

OUT

t

D0 D1 D2 D3 D4 D5 D6 D7

S1

t

t

H1

t

14-8

Figure 14-4. A.C. Timing Waveform for the UART Module

KS88C4708/C4716/P4716 (Preliminary Spec) ELECTRICAL DATA

Table 14-7. Data Retention Supply Voltage in Stop Mode

(T

= – 40 °C to + 85 °C, V

A

= 1.8 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Data Retention

V

DDDR

Stop mode 1.8 – 5.5 V

Supply Voltage
Data Retention

I

DDDR

Stop mode, V

DDDR

= 1.8 V

– 0.1 5 µA

Supply Current

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

VDD

RESET

RESET

occurs

~

Execution of

STOP Instrction

NOTE:

~

~

~

tWAIT is the same as 4096 x 32 x 1/fOSC.

Stop Mode

Data Retention Mode

VDDDR

tWAIT

Figure 14-5. Stop Mode Release Timing When Initiated by a Reset

VOUT

VDD

A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD

VSS

Oscillation

Stabilzation

Time

Normal
Operating
Mode

VINA B C D

Figure 14-6. Schmitt Trigger Input Characteristics

14-9

ELECTRICAL DATA KS88C4708/C4716/P4716 (Preliminary Spec)

Table 14-8. A/D Converter Electrical Characteristics

(TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V)

Parameter Symbol Test Conditions Min Typ Max Unit

Total accuracy –
Integral linearity

ILE CPU clock = 8 MHz

error
Differential

DLE

VDD = 5.12 V

AV

= 5.12 V

REF

AVSS = 0 V

– –

± 3

–

–

± 2

± 1

LSB

linearity error
Offset error of

EOT

± 1 ± 3

top
Offset error of

EOB

± 1 ± 2

bottom
Conversion

(1)

time
Analog input

t

CON

V

IAN

f

OSC

= 10 MHz

(3)

–

20 – –

AV

SS

–

AV

REF

µs

V

voltage
Analog input

R

AN

– 2 – –

MΩ

impedance
ADC reference

AV

REF

– 2.5 –

V

DD

V

voltage
ADC reference

AV

SS

–

V

SS

–

VSS + 0.3

V

ground
Analog input

I

ADIN

AVCC = VCC = 5 V

– – 10

µA

current
Analog block

current

(2)

I

ADC

AVCC = VCC = 5 V

AVCC = VCC = 3 V
AVCC = VCC = 5 V

– 1 3 mA

0.5 1.5

100 500 nA

power down mode

NOTES:

1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.

2. I

3. f

14-10

is operating current during A/D conversion.

ADC

is the main oscillator clock.

OSC

KS88C4708/C4716/P4716 (Preliminary Spec) ELECTRICAL DATA

Digital Output

11 1111 1111
11 1111 1110
11 1111 1101

.
.
.
.
.

00 0000 0010
00 0000 0001
00 0000 0000

AVSSV

EOBV2

V

(K-1)

(K)

V

EOTAVREF

V

Analog Input

1LSB = (V
DLE(K) = {(V

ILE(K) = {V

EOT-VEOB

(K)-V(K-1)

(K)

-(1LSB x K + V

)/1022

)-1LSB}/1LSB

EOB

)}/1LSB

DLE = MAX{DLE(K)}
ILE = MAX{ILE(K)}

Figure 14-7. Definition of DLE and ILE

14-11

ELECTRICAL DATA KS88C4708/C4716/P4716 (Preliminary Spec)

NOTES

14-12

KS88C4708/C4716/P4716 (Preliminary Spec) MECHANICAL DATA

15 MECHANICAL DATA

OVERVIEW

This section contains the following information about the device package:
— Package dimensions in millimeters

— Pad diagram

(1.77)

#42 #22

42-SDIP-600

14.00 ± 0.2

39.50 MAX

39.10

± 0.2

0.50 ±

0.1

1.778

NOTE :

Dimensions are in millimeters.

1.00 ±

0.1

0-15

15.24

#21#1

0.2
±

3.50

5.08 MAX

3.30 ± 0.3

0.51 MIN

+ 0.1

0.25

- 0.05

Figure 15-1. 42-SDIP-600 Package Dimensions

15-1

MECHANICAL DATA KS88C4708/C4716/P4716 (Preliminary Spec)

± 0.3

13.20
0-8

± 0.2

10.00

0.15

+ 0.10

- 0.05

± 0.3

13.20

10.00 ± 0.2

44-QFP-1010

#44

#1

0.80

NOTE

: Dimensions are in millimeters.

Figure 15-2. 44-QFP-1010 Package Dimensions

0.35

+ 0.10

- 0.05

(1.00)

0.10 MAX

0.80 ± 0.20

0.05 MIN

2.05

± 0.10

2.30 MAX

15-2

KS88C4708/C4716/P4716 (Preliminary Spec) KS88P4716 OTP

16 KS88P4716 OTP

OVERVIEW

The KS88P4716 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

KS88C4708/C4716 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is
accessed by serial data format.

The KS88P4716 is fully compatible with the KS88C4708/C4716, both in function in D.C. electrical characteristics
and in pin configuration. Because of its simple programming requirements, the KS88P4716 is ideal as an
evaluation chip for the KS88C4708/C4716.

P1.0/T0(CAP/PWM)

42

P1.1/T1CK

41

P1.2/T1(CAP/PWM)

40

P1.3/BUZ

39

P1.4/RxD

38

P1.5/TxD

37

P3.7/ADC7

36

P3.6/ADC6

35

P3.5/ADC5

34

P3.4/ADC4

33

P3.3/ADC3

32

P3.2/ADC2

31

P3.1/ADC1

30

P3.0/ADC0

29

AVSS/

28

AV

27

P2.7/INT7

26

P2.6/INT6

25

P2.5/INT5

24

P2.4/INT4

23

P2.3/INT3

22

REF

RESET

SDAT

/P4.3

SCLK

/P4.2

VDD/V

VSS/V

OUT/XOUT

X

XIN/X

VPP/TEST

/RESET

P2.0/INT0
P2.1/INT1
P2.2/INT2

P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0

DD

SS

P4.1
P4.0

IN

NOTE:

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

KS88P4716

(42-SDIP-600)

The bolds indicate an OTP pin name.

Figure 16-1. KS88P4716 Pin Assignments (42-SDIP Package)

AV

/

AV

SS

REF

16-1

KS88P4716 OTP KS88C4708/C4716/P4716 (Preliminary Spec)

P4.4

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0/T0(CAP/PWM)

P1.1/T1CK

P1.2/T1(CAP/PWM)

P1.3/BUZ

4443424140393837363534

P1.4/RxD

33
32
31
30
29
28
27
26
25
24
23

P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0

AV

SS

AVSS/

SDAT

/P4.3

SCLK

/P4.2

VDD/V

VSS/V

OUT/XOUT

X

XIN/X

VPP/TEST

P0.1
P0.0

DD

SS

P4.1
P4.0

1
2
3
4
5
6
7

IN

8

KS88P4716

(44-QFP-1010)

9
10
11

1213141516171819202122

REF

P4.5

AV

P2.0/INT0

P2.1/INT1

P2.2/INT2

P2.3/INT3

P2.4/INT4

P2.5/INT5

P2.6/INT6

P2.7/INT7

RESET /RESET

NOTE:

The bolds indicate an OTP pin name.

Figure 16-2. KS88P4716 Pin Assignments (44-QFP Package)

16-2

KS88C4708/C4716/P4716 (Preliminary Spec) KS88P4716 OTP

Table 16-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P4.3 SDAT 9(3) I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input/push-pull output port.

P4.2 SCLK 10(4) I Serial clock pin. Input only pin.

TEST V

PP

14(16) I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is aplied, OTP is in reading mode.
(Option)

RESET RESET

VDD/V

SS

VDD/V

SS

18(12) I Chip Initialization

11(5)/12(6) – Logic power supply pin. V

should be tied to

DD

+5 V during programming.

NOTE: ( ) means 44 QFP package.

Table 16-2. Comparison of KS88P4716 and KS88C4708/C4716 Features

Characteristic KS88P4716 KS88C4708/C4716

Program Memory 16-Kbyte EPROM 8/16-Kbyte mask ROM
Operating Voltage (VDD) 1.8 V to 5.5 V 1.8 V to 5.5 V

OTP Programming Mode VDD = 5 V, V

(EA) = 12.5 V

PP

Pin Configuration 42 SDIP/44 QFP 42 SDIP/44 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP (TEST) pin of the KS88P4716, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 16-3 below.

Table 16-3. Operating Mode Selection Criteria

V

DD

V

PP

(TEST)

REG/

MEM

ADDRESS

(A15–A0)

R/W MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16-3

KS88P4716 OTP KS88C4708/C4716/P4716 (Preliminary Spec)

NOTES

16-4