Datasheet KS88P4632, KS88C4632, KS88C4616 Datasheet (Samsung)

KS88C4616/C4632/P4632 PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

SAM8 PRODUCT FAMILY

Samsung's new SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.

A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM8 microcontrollers have an
external interface that provides access to external memory and other peripheral devices.

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
one interrupt level at a time.

KS88C4616/C4632 MICROCONTROLLER

The KS88C4616/C4632 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter,
UART, SIO, ZCD extended PWM application field. Its powerful SAM87 CPU architecture includes. The internal
register file is logically expanded to increase the on-chip register space.

The KS88C4616/C4632 has 16/32 K bytes of on-chip program ROM. A sophisticated bus interface enables
access to external memory and other peripherals when you use the chip in ROM-less mode. Following
Samsung's modular design approach, the following peripherals are integrated with the SAM87 core:

— Large number of programmable I/O ports (total 56 pins)
— One asynchronous UART module
— One synchronous SIO module
— Analog-to-digital converter with eight input channels and 10-bit resolution
— One 8-bit basic timer for watchdog function
— One 8-bit timer/counter with three operating modes (timer 0)
— One 8-bit timer for zero-cross detection circuit (timer 2)
— Two general-purpose 16-bit timer/counters with four operating modes (timer module 1)
— PWM block with one capture module, 16-bit timer/counter, PWM extension mode, and two PWM outputs
— One zero cross detection module

The KS88C4616/C4632 is a versatile general-purpose microcontroller that is ideal for use in a wide range of
electronics applications requiring complex timer/counter, PWM, capture, SIO, UART and ZCD functions.
It is available in a 64-pin SDIP or 64-pin QFP package.

OTP

The KS88P4632 is an OTP (One Time Programmable) version of the KS88C4616/C4632 microcontroller. The
KS88P4632 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of a masked
ROM. The KS88P4632 is comparable to the KS88C4616/C4632, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW KS88C4616/C4632/P4632

FEATURES

CPU

• SAM87 CPU core

Memory

• 528-byte general purpose register area

• 16/32-Kbyte internal program memory

• ROM-less operating mode

External Interface

• 64-Kbyte external data memory area

• 64-Kbyte external program memory area
(ROM-less mode)

Instruction Set

• 79 instructions

• IDLE and STOP instructions added for
power-down modes

Instruction Execution Time

• 500 ns at 12 MHz f

(minimum)

OSC

Interrupts

• 21 interrupt sources and 21 vectors

• Eight interrupt levels

• Fast interrupt processing

Timer/Counters

• One 8-bit basic timer for watchdog function

• One 8-bit timer/counter with three operating
modes (timer 0)

• One 8-bit timer for the zero-cross detection
circuit

• Two 16-bit general-purpose timer/counters with
four operating modes (timer C and D)

UART

• One UART module

• Full duplex serial I/O interface with three UART
modes

A/D Converter

• Eight analog input pins

• 10-bit conversion resolution

• 20 µs conversion time (10 MHz CPU clock)

Zero Cross Detection Circuit

• Zero cross detection circuit that generates a
digital signal in synchronization with an AC
signal input

Buzzer Frequency Output

• 200 Hz to 20 kHz signal can be generated

General I/O

• Seven I/O ports (total 56 pins)

• Seven bit-programmable ports

PWM and Capture

• Two 14-bit PWM output

• One capture

Serial I/O

• One synchronous serial I/O module

• Selectable transmit and receive rates

• Selectable baud rate for Rx and Tx respectively

1-2

Oscillator Frequency

• 1 MHz to 12 MHz external crystal oscillator

• Maximum 12 MHz CPU clock

Operating Temperature Range

• – 40°C to + 85°C

Operating Voltage Range

• 2.7 V to 5.5 V

Package Types

• 64-pin SDIP, 64-pin QFP

KS88C4616/C4632/P4632 PRODUCT OVERVIEW

BLOCK DIAGRAM

X

X

OUT

T0CK

T0

TCG

TDG
TCCK
TDCK

PWM0
PWM1

CAPA

SI

SO

SCK

RxD

TxD

ADC0

-ADC7

P0.0-P0.7

(A8-A15)

Basic
Timer

IN

OSC

Timer

Timers

C and D

PWM/

CAP

SIO

UART

16/32-Kbyte

ROM

ADC

P1.0-P1.7

(AD0-AD7)

Port 1 Port 0Port 0

SAM8 BUS

P2.4/ZCD-P2.7/INT3

Port I/O and Interrupt

Control

SAM8 CPU

528-byte

Register File

P2.0-P2.3

Port 3

Port 4

Port 5

Port 6

P3.0-P3.7

P4.0/INT4­P4.7/INT11

P5.0-P5.7

P6.0-P6.7

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW KS88C4616/C4632/P4632

PIN ASSIGNMENTS

P1.0/AD0

P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10

P0.1/A9

P0.0/A8
P4.7/INT11/TDG
P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK
P4.3/INT7/CAPA

P4.2/INT6

P4.1/INT5/RxD

V

DD

V

SS

X

OUT

X

EA

P4.0/INT4

P3.7/TxD

RESET

P3.6/SO

P3.5/SI

P3.4/

SCK

P3.3/T0CK

P3.2/T0

P3.1/PWM1
P3.0/PWM0

P2.7/INT3
P2.6/INT2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

IN

19

KS88C4616
KS88C4632

(64-SDIP-750)

20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AV

SS

AV

REF

P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P2.0/

AS

P2.1/

DS

P2.2/R/

W

P2.3/

DM

P2.4/ZCD
P2.5/BUZ

1-4

Figure 1-2. Pin Assignment Diagram (64-Pin SDIP Package)

KS88C4616/C4632/P4632 PRODUCT OVERVIEW

P3.1/PWM1

P3.0/PWM0

P0.1/A9

P0.2/A10

P0.3/A11

P0.4/A12

P0.5/A13

P0.6/A14

P0.7/A15

P1.0/AD0

P1.1/AD1

P1.2/AD2

P1.3/AD3

P1.4/AD4

P1.5/AD5

64636261605958575655545352

P1.6/AD6

P4.7/INT11/TDG

P0.0/A8

P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK

P4.3/INT7CAPA

P4.2/INT6

P4.1/INT5/RxD

V

DD

V

SS

X

OUT

X

EA

P4.0/INT4

P3.7/TxD

RESET

P3.6/SO

P3.5/SI

P3.4/

SCK

1
2
3
4
5
6
7
8
9
10
11

IN

12

KS88C4616
KS88C4632

(64-QFP-1420F)

13
14
15
16
17
18
19

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P1.7/AD7
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AV

SS

AV

REF

P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1

20212223242526272829303132

W

P6.0

P3.2/T0

P3.3/T0CK

P2.5/BUZ

P2.4/ZCD

P2.7/INT3

P2.6/INT2

P2.1/DS

P2.3/DM

P2.2/R/

P2.0/AS

Figure 1-3. Pin Assignment Diagram (64-Pin QFP Package)

1-5

PRODUCT OVERVIEW KS88C4616/C4632/P4632

Table 1-1. KS88C4616/C4632 Pin Descriptions

Pin

Name

Pin

Type

Pin Description Circuit

P0.0–P0.7 I/O Bit-programmable I/O port for Schmitt trigger

input or push-pull, open-drain, output. Pull-up
resistors are assignable by software.
Port 0 can also be configured as external
interface address line A8–A15

P1.0–P1.7 I/O Same general characteristics as port 0.

Port 1 can also be configured as external
interface address/data lines AD0–AD7

P2.0–P2.3

I/O Bit-programmable I/O port for Schmitt trigger

input or push-pull output. P2.0–P2.3 can be
configured for external bus control signals.

P2.4–P2.7

P2.4–P2.7 are used for general I/O or for the
ZCD, BUZ, INT2 and INT3

P3.0–P3.7 I/O Bit-programmable I/O port for Schmitt trigger

input or push-pull output. Each port 3 pin has
an alternative function:
P3.0: PWM0 (PWM0 module output)
P3.1: PWM1 (PWM1 module ouptut)
P3.2: T0 (T0 capture input or PWM output)
P3.3: T0CK (timer 0 external clock input)
P3.4: SCK (SIO module input)
P3.5: SI (SIO module clock I/O)
P3.6: SO (SIO module output)
P3.7: TxD: SO1
(The T0 function for P3.2 is selected using the
T0CON register.)

P4.0–P4.7 I/O Bit-programmable I/O port for Schmitt trigger

input or push-pull output. Port 4 pins are used
external interrupts INT4–INT11 or for the
following share functions:
P4.1: RxD (UART module input)
P4.3: CAPA (capture input)
P4.4: TCCK (timer/counter C clock input)
P4.5: TDCK (timer/counter D clock input)
P4.6: TCG (timer C gate input)
P4.7: TDG (timer D gate input)

Number

1 8–1

(1, 64–58)–A8–A15

1 64–57

2

3

4 30–22

5 21, 15–9

Pin

Number

Share

Pins

(57–50)–AD0–AD7

38–35

(31–28)

–

AS, DS

DM, R/W

34–31

(27–24)

ZCD, BUZ

INT2, INT3

(See pin

(23–15)

description)

(See pin

(14–2)

description)

1-6

KS88C4616/C4632/P4632 PRODUCT OVERVIEW

Table 1-1. KS88C4616/C4632 Pin Descriptions (Continued)

Pin

Name

P5.0–P5.7 I/O Bit-programmable I/O port for Schmitt trigger

Pin

Type

Pin Description Circuit

input or push-pull, output. Pull-up resistors are

Number

6 49–56

Pin

Number

(42–49)

Share

Pins

ADC0–

ADC7
assignable by software. Port 5 pins can also be
used as A/D converter inputs.

P6.0–P6.7 I/O Individual pins are software configurable as

input or push-pull, open-drain, output. Pull-up

1 39–46

(32–39)

–

resistors are assignable by software.

AD0–AD7 I/O External interface address/data line 6 64–57

P1.0–P1.7

(57–50)

AS
DS

I/O External bus control signals 2 38–35

(31–28)

P2.0–P2.3

R/W

DM

ZCD I/O Zero cross detector input 2 34 (27) P2.4
BUZ I/O 200 Hz–20 kHz frequency output for buzzer

2 33 (26) P2.5

sound

PWM0
PWM1

I/O PWM output 3 30, 29

(23, 22)

P3.0–P3.1

T0 (CAP) I/O T0 capture input or PWM output 3 28 (21) P3.2
T0CK I/O External clock input for Timer 0 3 27 (20) P3.3
SCK I/O SIO clock signal 3 26 (19) P3.4
SI, SO I/O SIO data input/output 3 25, 24

P3.5–P3.6

(18, 17)
TxD I/O UART data output 3 22 (15) P3.7
INT2–INT3 I/O External interrupts: the triggering edge is

selectable.

INT4 I/O External interrupts: the triggering edge is

2 32, 31

P2.6–P2.7

(25, 24)

4 21 (14) P4.0

selectable.

RxD/INT5 I/O UART data input or external interrupt: the

4 15 (8) P4.1

triggering edge is selectable.

INT6
CAPA/INT7

I/O Capture module input or external interrupt: the

triggering edge is selectable.

4 14,13

(7, 6)

P4.2–P4.3

1-7

PRODUCT OVERVIEW KS88C4616/C4632/P4632

Table 1-1. KS88C4616/C4632 Pin Descriptions (Concluded)

Pin

Name

TCCK/INT8
TCDK/INT9

TCG/INT10
TDG/INT11

ADC0–

Pin

Pin Description Circuit

Type

I/O Timer/counter C and D clock input or external

interrupts: the triggering edge is selectable.

I/O Timer/counter C and D clock input or external

interrupts: the triggering edge is selectable.

I/O A/D converter inputs 5 49–56

ADC7
XIN, X

OUT

– System clock input and output pins – 19, 18

I System reset pin 7 23 (16) –

EA I External access (EA) pin with three modes:

0 V: Normal operation (internal ROM)
5 V: ROM-less operation (external interface)

12.5 V: OTP read/write mode

AV

,

REF

AV

SS

V

,V

DD

SS

NOTE: Pin numbers shown in parentheses "( )" are for the 64-pin QFP package.

– A/D converter reference voltage input and ground – 47, 48

– Voltage input pin and ground – 16, 17

Pin

Number

Number

4 12, 11

(5, 4)

4 10, 9

(3, 2)

(42–49)

(12, 11)

– 20 (13) –

(40, 41)

(9, 10)

Share

Pins

P4.4–P4.5

P4.6–P4.7

P5.0–P5.7

–

–

–

1-8

KS88C4616/C4632/P4632 PRODUCT OVERVIEW

PIN CIRCUITS

Table 1-2. Pin Circuit Assignments for the KS88C4616/C4632

Circuit Number Circuit Type KS88C4616/C4632 Assignments

1 I/O Port 0,1 and port 6
2 I/O Port 2 (P2.0–P2.3 only)
3 I/O Port 2 (P2.4–P2.7 only)
4 I/O Port 3
5 I/O Port 4
6 I/O Port 5
7 I

NOTE: Diagrams of circuit types 1–7 are presented below.

RESET

1-9

PRODUCT OVERVIEW KS88C4616/C4632/P4632

V

DD

Pull-up Resistor
(Typical Value: 47 KΩ)

Pull-up
Enable

V

DD

Data

In/Out

Open-drain

Output DIsable

In

Figure 1-4. Pin Circuit Type 1 (Port 0,1 and Port 6)

Pull-up
Enable

Port 2 (Low Byte) Data

External Interface

(AS, DS, R/W, DM)

Output DIsable

Figure 1-5. Pin Circuit Type 2 (Port 2, P2.0–P2.3 only)

V

DD

Pull-up Resistor
(Typical Value: 47 KΩ)

Select

M

Data

V

DD

U

X

In/Out

In

1-10

KS88C4616/C4632/P4632 PRODUCT OVERVIEW

V

DD

Pull-up Resistor
(Typical Value: 47 KΩ)

Pull-up
Enable

Port 2 (High Byte) Data

Select

M

V

DD

U

Control Output (BUZ)

X

In/Out

Output DIsable

External

Interrupt Input

Noise Filter

Normal

Input

ZCD Input

Figure 1-6. Pin Circuit Type 3 (Port 2, P2.4–P2.7 only)

1-11

PRODUCT OVERVIEW KS88C4616/C4632/P4632

V

DD

Pull-up Resistor
(Typical Value: 47 KΩ)

Pull-up
Enable

Port 3

Control

Output

Select

M
U

X

Data

V

DD

In/Out

Output

DIsable

Normal

Input

Figure 1-7. Pin Circuit Type 4 (Port 3)

Pull-up
Enable

Data

Output

DIsable

External

Interrupt Input

Alternative

Input

Normal

Input

DD

V

Pull-up Resistor
(Typical Value: 47 KΩ)

V

DD

Noise Filter

Figure 1-8. Pin Circuit Type 5 (Port 4)

In/Out

1-12

KS88C4616/C4632/P4632 PRODUCT OVERVIEW

DD

V

Pull-up Resistor
(Typical Value: 47 KΩ)

Pull-up
Enable

DD

V

Data

In/Out

Output

DIsable

Normal

Input

Analog

Input

Figure 1-9. Pin Circuit Type 6 (Port 5)

V

DD

Pull-up Resistor
(Typical Value: 200 KΩ)

RESET

Figure 1-10. Pin Circuit Type 7 (RESET)

1-13

PRODUCT OVERVIEW KS88C4616/C4632/P4632

NOTES

1-14

KS88C4616/C4632/P4632 ELECTRICAL DATA

19 ELECTRICAL DATA

OVERVIEW

In this chapter, KS88C4616/C4632 electrical characteristics are presented in tables and graphs. The information
is arranged in the following order:

— Absolute maximum ratings
— Input/output capacitance
— D.C. electrical characteristics
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
— Data retention supply voltage in stop mode
— Serial I/O timing characteristics
— UART timing characteristics in mode 0
— A/D converter electrical characteristics
— Zero crossing detector
— External memory timing characteristics

19-1

ELECTRICAL DATA KS88C4616/C4632/P4632

Table 19-1. Absolute Maximum Ratings

(TA = 25°C)

Parameter Symbol Conditions Rating Unit

Supply Voltage
Input Voltage
Output Voltage
Output Current High

V

DD

V

All input ports

I

V

I

All output ports

O

One I/O pin active – 18 mA

OH

– – 0.3 to + 6.5 V

– 0.3 to VDD + 0.3

– 0.3 to VDD + 0.3

V
V

All I/O pins active – 60

Output Current Low

I

One I/O pin active + 30 mA

OL

Total pin current for ports 0, 2–4, and 6 + 100
Total pin current for ports 1 and 5 + 200

Operating

T

A

– – 40 to + 85

°

C

Temperature
Storage Temperature

T

STG

– – 65 to + 150

°

C

Table 19-2. Input/Output Capacitance

(T

= – 40°C to 85°C, V

A

DD

= 0 V )

Parameter Symbol Conditions Min Typ Max Unit

C

C

OUT

C

IN

IO

f = 1 MHz; unmeasured pins
are tied to V

SS

– – 10 pF

Input Capacitance

Output Capacitance
I/O Capacitance

19-2

KS88C4616/C4632/P4632 ELECTRICAL DATA

Table 19-3. D.C. Electrical Characteristics

(T

= – 40°C to + 85°C, VDD = 2.7 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Input High Voltage

V

IH1

V

= 2.7 V to 5.5 V

DD

0.8 V

DD

–

V

DD

V

All Port and RESET

Input Low Voltage

V

V

IH2

IL1

V

= 4.5 V to 5.5 V

DD

XIN and X
V

DD

OUT

= 2.7 V to 5.5 V

V

– 1.0

DD

– –

0.2 V

DD

V

All Ports and RESET

Output High Voltage

V

V

IL2

OH

V

= 4.5 V to 5.5 V

DD

XIN and X
V

DD

I

OH

OUT

= 4.5 V to 5.5 V

= – 1 mA

0.1

V

DD

– 1.0

– – V

All Ports

Output Low Voltage

V

OL1

V

= 4.5 V to 5.5 V

DD

– 0.4 2.0 V

IOL = 15 mA
Ports 1,5, and 6

V

OL2

V

= 4.5 V to 5.5 V

DD

IOL = 4 mA
Ports 0, 2, 3, and 4

Input High Leakage
Current

Input Low Leakage
Current

I

LIH1

I

LIH2

I

LIL1

VIN = V

DD

All input pins except I
VIN = V

DD

XIN, X

OUT

V

= 0 V

IN

LIH2

All input pins except and I

– – 1 µA

20

– – – 1 µA

LIL2

and RESET

Output High
Leakage Current

Output Low Leakage
Current

I

LIL2

I

LOH1

I

LOL

V

= 0 V

IN

XIN, X

OUT

V

= V

OUT

DD

All output pins
V

= 0 V

OUT

All output pins

– 20

– – 2 µA

– – – 2 µA

19-3

ELECTRICAL DATA KS88C4616/C4632/P4632

Table 19-3. D.C. Electrical Characteristics (Continued)

(T

= – 40°C to + 85°C, VDD = 2.7 V to 5.5 V)

A

Parameter Symbol Conditions Min Typ Max Unit

Pull-up Resistor

Supply Current

(note)

R

R

I

DD1

P1

P2

V

= 5 V; V

DD

V

= 3 V; Ports 0–6

DD

V

= 5 V; V

DD

V

= 3 V; only

DD

V

= 4.5 V to 5.5 V

DD

RUN mode

= 0 V

IN

IN

= 0 V

30 47 70

30 – 350
100 200 400
200 400 800

– 16 30 mA

kΩ

12 MHz CPU clock
V

= 2.7 V to 3.3 V

DD

5.5 12

8 MHz CPU clock

I

DD2

V

= 4.5 V to 5.5 V

DD

3 6

Idle mode
12 MHz CPU clock

V

= 2.7 V to 3.3 V

DD

1 2.5

8 MHz CPU clock

I

DD3

V

= 4.5 V to 5.5 V

DD

1 5 µA

Stop mode
V

= 2.7 V to 3.3 V

DD

Stop mode

NOTE: Supply current does not include current drawn through internal pull-up resistors, ZCD, ADC and external output

current loads.

Table 19-4. A.C. Electrical Characteristics

(T

= – 40°C to + 85°C, V

A

= 2.7 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Interrupt Input
High, Low Width

Input

t

INTH

t

INTL

t

RSL

Ports 2, 3, and 4 – 270 – ns

,

Input – 1500 – ns

Low Width

t

t

INTL

t

RSL

0.8 V

0.2 V

INTH

DD

DD

Figure 19-1. Input Timing Measurement Points

19-4

KS88C4616/C4632/P4632 ELECTRICAL DATA

Table 19-5. Oscillation Characteristics

(TA = – 40°C + 85°C)

Oscillator Clock Circuit Test Condition Min Typ Max Unit

Main Crystal or
Ceramic

X

IN

C1 C2

X

OUT

VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V

1 – 12 MHz
1 – 8

External Clock
(Main System)

XINX

CPU Clock

12 kHz

8 kHz

1 kHz

OUT

VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V

Main Oscillator Frequency

1 – 12 MHz
1 – 8

1 2 3 4 5 6 7

2.7 V 5.5 V

Supply Voltage (V)

Figure 19-2. Operating Voltage Range

19-5

ELECTRICAL DATA KS88C4616/C4632/P4632

Table 19-6. Oscillation Stabilization Time

(T

= – 40°C + 85°C, VDD = 2.7 V to 5.5 V)

A

Oscillator Test Condition Min Typ Max Unit

f

Main Crystal
Main Ceramic

> 400 kHz;

OSC

Oscillation stabilization occurs when VDD is equal

– – 20 ms
– – 10 ms

to the minimum oscillator voltage range.

External Clock

XIN input High and Low width (tXH, tXL)

25 – 500 ns

(Main System)
Oscillator

Stabilization

t

when released by a reset

WAIT

(1)

–

216/f

OSC

– ms

Wait Time

t

when released by an interrupt

WAIT

NOTES:

1. f

2. The duration of the oscillator stabilization wait time, t

is the oscillator frequency.

OSC

settings in the basic timer control register, BTCON.

(2)

, when it is released by an interrupt is determined by the

WAIT

–

–

– ms

19-6

KS88C4616/C4632/P4632 ELECTRICAL DATA

Table 19-7. Data Retention Supply Voltage in Stop Mode

(T

= – 40°C to + 85°C, V

A

= 2.7 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Data Retention

V

DDDR

Stop mode 2 – 5.5 V

Supply Voltage
Data Retention

I

DDDR

Stop mode, V

DDDR

= 2.0 V

– – 5 µA

Supply Current

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

V

RESET

DD

RESET

occurs

~

Execution of

STOP Instrction

NOTE:

~

~

~

t

WAIT

is the same as 4096 x 16 x 1/f

Stop Mode

Data Retention Mode

V

DDDR

OSC

.

t

WAIT

Figure 19-3. Stop Mode Release Timing When Initiated by a Reset

Oscillation

Stabilzation

Time

Normal
Operating
Mode

19-7

ELECTRICAL DATA KS88C4616/C4632/P4632

Table 19-8. Serial I/O Timing Characteristics

(T

= – 40°C to + 85°C, V

A

= 2.7 V to 5.5 V)

DD

Parameter Symbol Conditions Min Typ Max Unit

Cycle Time

t

CKY

External source 1000 – – ns
Internal source 1000

High, Low Width

SI Setup Time to Low

tKH, t

t

SIK

External source 500 – –

KL

t

Internal source

KCY

/2 – 50
External source 250 – –
Internal source 250

SI Hold Time to High

t

KSI

External source 400 – –
Internal source 400

Output Delay for to SO

t

KSO

External source – – 300
Internal source 250

NOTE: " " means serial I/O clock frequency, "SI" means serial data input, and "SO" means serial data output.

SCK

SO

t

KCY

t

t

KL

t

SIK

SI

t

KSO

Input Data

KH

0.8 V

DD

0.2 V

DD

t

KSI

0.8 V

DD

0.2 V

DD

Output Data

Figure 19-4. Serial Data Transfer Timing

19-8

KS88C4616/C4632/P4632 ELECTRICAL DATA

Table 19-9. UART Timing Characteristics in Mode 0 (10 MHz)

(T

= – 40°C to + 85°C, V

A

= 2.7 V to 5.5 V, Load capacitance = 80 pF)

DD

Parameter Symbol Min Typ Max Unit

Serial port clock cycle time
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Serial port clock High, Low level width

NOTES:

1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.

2. The unit t

means one CPU clock period.

CPU

t

SCK

t

S1

t

S2

t

H1

t

H2

t

HIGH, tLOW

500
300

t

CPU

t

CPU

× 6
× 5

– – 300

t

– 50 t

CPU

CPU

0 – –

200

t

CPU

× 3

700 ns

–

–

400

0.8 V

t

SCK

t

HIGH

DD

t

LOW

0.2 V

DD

Figure 19-5. Waveform for UART Timing Characteristics

19-9

ELECTRICAL DATA KS88C4616/C4632/P4632

SCK

Data

In

NOTE: The symbols shown in this diagram are defined as follows:

fSCK Serial port clock cycle time

tS1 Output data setup to clock rising edge

tS2 Clock rising edge to input data valid

tH1 Output data hold after clock rising edge

tH2 Input data hold after clock rising edge

VALID VALID VALID VALID VALID VALID VALID VALID

Out

Data

D0 D1 D2 D3 D4 D5 D6 D7

t

S1

Clock

Shift

tS2

t

tH1

tH2

19-10

Figure 19-6. A.C. Timing Waveform for the UART Module

KS88C4616/C4632/P4632 ELECTRICAL DATA

Table 19-10. A/D Converter Electrical Characteristics

(TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V)

Parameter Symbol Test Conditions Min Typ Max Unit

Resolution – 10 – bit
Total accuracy

Integral linearity
error

Differential

ILE CPU clock = 10 MHz

DLE

VDD = 5.12 V

AV

= 5.12 V

REF

AVSS = 0 V

– –

± 3

–

–

± 2

± 1

LSB

linearity error
Offset error of

EOT

± 1 ± 3

top
Offset error of

EOB

± 0.5 ± 2

bottom
Conversion time

(1)

Analog input

t

CON

V

IAN

10-bit conversion
50 x 4/f

OSC

(3)

, f

–

= 10 MHz

OSC

20 – –

AV

SS

–

AV

REF

µs

V

voltage
Analog input

R

AN

– 2 – –

MΩ

impedance
Analog

AV

REF

– 2.5 –

V

DD

V
reference
voltage

Analog ground
Analog input

current
Analog block

current

(2)

AV

I

ADIN

I

ADC

SS

AV

= VDD = 5 V

REF

conversion time = 20 µs
AV

= VDD = 5 V

REF

conversion time = 20 µs
AV

= VDD = 3 V

REF

–

V

SS

–

VSS + 0.3

– – 10

1 3 mA

0.5 1.5 mA

V

µA

conversion time = 20 µs
AV

= VDD = 5 V

REF

100 500 nA

when power down mode

NOTES:

1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.

2. I

3. f

is operating current during A/D conversion.

ADC

is the main oscillator clock.

OSC

19-11

ELECTRICAL DATA KS88C4616/C4632/P4632

Table 19-11. Zero Crossing Detector

(TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V, V

SS

= 0 V)

Parameter Symbol Test Conditions Min Typ Max Unit

Zero-crossing
detection input

V

ZC

AC connection

1.0 – 3.0 Vp-p

c = 0.1 µF

voltage
Zero-crossing

detection accuracy

Zero-crossing

V

AZC

f

ZC

fZC = 60 Hz (sine wave)
VDD = 5 V
f

= 10 MHz

OSC

–

– –

± 150

40 – 200 Hz
detection input
frequency

1/fzc

mV

19-12

V

AC input V

ZCINT

AZC

Figure 19-7. Zero Crossing Waveform Diagram

AZ (P-P)

KS88C4616/C4632/P4632 ELECTRICAL DATA

Table 19-12. External Memory Timing Characteristics (8 MHz)

(T

= – 40°C to + 85°C, V

A

= 2.7 V to 5.5 V)

DD

Number Symbol Parameter Normal Timing (ns)

Min Max

1
2
3
4

5
6a
6b

7

8

9
10
11
12
13

tdA (AS)
t

(A)

dAS

t

(DR)

dAS

t

wAS

tdA (DS)
t

(read)

wDS

t

(write)

wDS

t

(DR)

dDS

t

(DR)

hDS

t

(A)

dDS

t

(AS)

dDS

t

(DS)

dDO

t

(AS)

dRW

t

(DW)

dDS

Address valid to ↑ delay

↑ to address float delay
↑ to read data required valid

10 –
35 –

– 140

Low width 43.75 (35) –

Address float to ↓

0 –
(read) Low width 156.25 (125) –
(write) Low width 81.25 (65) –
↓ to read data required valid

Read data to ↑ hold time

↑ to address active delay
↑ to ↓ delay

Write data valid to (write) ↓ delay
R/ valid to ↑ delay

↑ to write data not valid delay

– 80

0 –

20 –
30 –
10 –
20 –
20 –

NOTES:

1. All times are in nanoseconds (ns) and assume an 8-MHz input frequency.

2. Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7.

3. The values for t

wAS

and t

that are shown in parentheses "( )" assume a 10-MHz input clock.

wDS

19-13

ELECTRICAL DATA KS88C4616/C4632/P4632

R/W (P2.2)

12

Port 0

DM (P2.3)

A8-A15,

3 9

DM

AS

DS

Port 1

(P2.0)

(P2.1)

D0-D7 OutA0-A7

1

4

112

5

7

D0-D7 In Out

Figure 19-8. External Memory Read and Write Timing

(See Table 19-10 for a description of each timing point.)

10

8

136

19-14

KS88C4616/C4632/P4632 MECHANICAL DATA

20 MECHANICAL DATA

OVERVIEW

The KS88C4616/C4632/P4632 microcontrollers are available in a 64-SDIP-750, 64-QFP-1420F package.

(1.34)

#64 #33

± 0.20

17.00

NOTE :

Dimensions are in millimeters.

64-SDIP-750

0.45 ±

0.10

1.00 ±

0.10

58.20 MAX

57.80

± 0.20

1.778

0-15

19.05

#32#1

4.10 ± 0.20

5.08 MAX

0.51 MIN

3.30 ± 0.30

+ 0.10

0.25

- 0.05

Figure 20-1. 64-SDIP-750 Package Dimensions

20-1

MECHANICAL DATA KS88C4616/C4632/P4632

23.90

± 0.30

17.90 ± 0.30

± 0.20

14.00
#64

1.00

64-QFP-1420F

#1

20.00

0.40

± 0.20

+ 0.10

- 0.05

0.15 MAX

0.80

± 0.20

(1.00)

0-8

+ 0.10

- 0.05

0.15

0.10 MAX

0.80 ± 0.20

0.05 MIN

2.65

± 0.10

3.00 MAX

20-2

NOTE

: Dimensions are in millimeters.

Figure 20-2. 64-QFP-1420F Package Dimensions

KS88C4616/C4632/P4632 KS88P4632 OTP

21 KS88P4632 OTP

OVERVIEW

The KS88P4632 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

KS88C4616/C4632 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is
accessed by serial data format.

The KS88P4632 is fully compatible with the KS88C4616/C4632, both in function in D.C. electrical characteristics
and in pin configuration. Because of its simple programming requirements, the KS88P4632 is ideal as an
evaluation chip for the KS88C4616/C4632.

21-1

KS88P4632 OTP KS88C4616/C4632/P4632

P1.0/AD0

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AV

SS

AV

REF

P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0

AS

P2.0/

DS

P2.1/

W

P2.2/R/

DM

P2.3/
P2.4/ZCD
P2.5/BUZ

P4.7/INT11/TDG

P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK
P4.3/INT7/CAPA

SDAT

SCLK

/P4.1/INT5/RxD

RESET

P3.1/PWM1
P3.0/PWM0

P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10

P0.1/A9
P0.0/A8

/P4.2/INT6

VDD/V

DD

VSS/V

SS

X

OUT

X

VPP/EA

P4.0/INT4

P3.7/TxD

/RESET

P3.6/SO

P3.5/SI

P3.4/

SCK

P3.3/T0CK

P3.2/T0

P2.7/INT3
P2.6/INT2

1
2
3
4
5
6
7
8
9
10
11
12
13
14

KS88C4616

15
16

KS88C4632

17
18

IN

(64-SDIP-750)

19
20
21
22
23
24
25
26
27
28
29
30
31
32

NOTE:

The bolds indicate an OTP pin name.

Figure 21-1. KS88P4632 Pin Assignments (64-SDIP Package)

21-2

KS88C4616/C4632/P4632 KS88P4632 OTP

P0.1/A9

P0.2/A10

P0.3/A11

P0.4/A12

P0.5/A13

P0.6/A14

P0.7/A15

P1.0/AD0

P1.1/AD1

P1.2/AD2

P1.3/AD3

P1.4/AD4

P1.5/AD5

64636261605958575655545352

P1.6/AD6

51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P1.7/AD7
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2
P5.1/ADC1
P5.0/ADC0
AV

SS

AV

REF

P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1

P4.7/INT11/TDG
P4.6/INT10/TCG
P4.5/INT9/TDCK
P4.4/INT8/TCCK

P4.3/INT7CAPA

SDAT

SCLK

/P4.1/INT5/RxD

RESET

P0.0/A8

/P4.2/INT6

VDD/V

DD

VSS/V

SS

X

OUT

X

VPP/EA

P4.0/INT4

P3.7/TxD

/RESET

P3.6/SO

P3.5/SI

P3.4/

SCK

1
2
3
4
5
6
7
8
9
10
11

IN

12

KS88C4616
KS88C4632

(64-QFP-1420F)

13
14
15
16
17
18
19

20212223242526272829303132

W

P6.0

NOTE:

P3.2/T0

P3.3/T0CK

P3.1/PWM1

P2.5/BUZ

P2.7/INT3

P2.6/INT2

P3.0/PWM0

P2.4/ZCD

The bolds indicate an OTP pin name.

P2.1/DS

P2.3/DM

P2.2/R/

P2.0/AS

Figure 21-2. KS88P4632 Pin Assignments (64-QFP Package)

21-3

KS88P4632 OTP KS88C4616/C4632/P4632

Table 21-1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip During Programming

Pin Name Pin Name Pin No. I/O Function

P4.2 SDAT 14(7) I/O Serial data pin. Output port when reading and

input port when writing. Can be assigned as a
Input/push-pull output port.

P4.1 SCLK 15(8) I Serial clock pin. Input only pin.

EA V

PP

20(13) I Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is aplied, OTP is in reading mode.
(Option)

RESET RESET

VDD/V

SS

VDD/V

SS

23(16) I Chip Initialization

16(9)/17(10) – Logic power supply pin. V

should be tied to

DD

+5 V during programming.

NOTE: ( ) means 64 QFP package.

Table 21-2. Comparison of KS88P4632 and KS88C4616/C4632 Features

Characteristic KS88P4632 KS88C4616/C4632

Program Memory 32-Kbyte EPROM 16/32-Kbyte mask ROM
Operating Voltage (VDD) 2.7 V to 5.5 V 2.7 V to 5.5 V

OTP Programming Mode VDD = 5 V, V

(EA) = 12.5 V

PP

Pin Configuration 64 SDIP/64 QFP 64 SDIP/64 QFP
EPROM Programmability User Program 1 time Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP (EA) pin of the KS88P4632, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 21-3 below.

Table 21-3. Operating Mode Selection Criteria

V

DD

V

PP

(EA)

REG/

MEM

ADDRESS

(A15–A0)

R/W MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

21-4