Datasheet J112RLRA, J112RL1, J112 Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel — Depletion

GATE

MAXIMUM RATINGS

Rating Symbol Value Unit

Drain–Gate Voltage V
Gate–Source Voltage V
Gate Current I
Total Device Dissipation @ TA = 25°C

Derate above 25°C
Lead Temperature T
Operating and Storage Junction

T emperature Range

P

TJ, T

DG
GS

G

D

L

stg

–65 to +150 °C

1 DRAIN

3

2 SOURCE

–35 Vdc
–35 Vdc

50 mAdc

350

2.8

300 °C

mW

mW/°C

Order this document

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1

2

3

CASE 29–04, STYLE 5

TO–92 (TO–226AA)

by J112/D

ELECTRICAL CHARACTERISTICS (T

Characteristic

OFF CHARACTERISTICS

Gate–Source Breakdown Voltage

(IG = –1.0 µAdc)
Gate Reverse Current

(VGS = –15 Vdc)
Gate Source Cutoff Voltage

(VDS = 5.0 Vdc, ID = 1.0 µAdc)
Drain–Cutoff Current

(VDS = 5.0 Vdc, VGS = –10 Vdc)

ON CHARACTERISTICS

Zero–Gate–Voltage Drain Current

(VDS = 15 Vdc)
Static Drain–Source On Resistance

(VDS = 0.1 Vdc)
Drain Gate and Source Gate On–Capacitance

(VDS = VGS = 0, f = 1.0 MHz)

Drain Gate Off–Capacitance

(VGS = –10 Vdc, f = 1.0 MHz)
Source Gate Off–Capacitance

(VGS = –10 Vdc, f = 1.0 MHz)

1. Pulse Width = 300 µs, Duty Cycle = 3.0%.

(1)

= 25°C unless otherwise noted)

A

Symbol Min Max Unit

V

(BR)GSS

I

GSS

V

GS(off)

I

D(off)

I

DSS

r

DS(on)

C

dg(on)

+

C

sg(on)

C

dg(off)

C

sg(off)

35 — Vdc

— –1.0 nAdc

–1.0 –5.0 Vdc

— 1.0 nAdc

5.0 — mAdc

— 50 Ω

— 28 pF

— 5.0 pF

— 5.0 pF

(Replaces J111/D)

Motorola Small–Signal Transistors, FETs and Diodes Device Data

 Motorola, Inc. 1997

1

J112

TYPICAL SWITCHING CHARACTERISTICS

1000

500
200

100

RK = RD′

TJ = 25°C

V

GS(off)

= 7.0 V

50

20

10
, TURN–ON DELAY TIME (ns)

5.0

d(on)

t

RK = 0

2.0

1.0

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)

Figure 1. T urn–On Delay Time

1000

500
200

100

50

RK = RD′

20
10

, TURN–OFF DELAY TIME (ns)

5.0

d(off)

t

2.0

1.0

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

RK = 0

ID, DRAIN CURRENT (mA)

V

GS(off)

TJ = 25°C

= 7.0 V

1000

500
200

RK = RD′

V

GS(off)

TJ = 25°C

= 7.0 V

100

50
20

, RISE TIME (ns)

r

10

5.0

RK = 0

2.0

1.0

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)

Figure 2. Rise Time

1000

500

V

= 7.0 V

200

RK = RD′

100

50
20

, FALL TIME (ns) t

f

10

t

RK = 0

5.0

2.0

1.0

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)

GS(off)

TJ = 25°C

Figure 3. Turn–Off Delay Time

R

GEN

50

Ω

V

GEN

INPUT PULSE

t

r

t

PULSE WIDTH

DUTY CYCLE

f

INPUT

≤

0.25 ns

≤

0.5 ns

= 2.0

≤

2.0%

SET V

R

K

50

Ω

RGG

µ

s

DS(off)

&

R

Ȁ+

D

R

R

= 10 V

GG

V

GG

K

RD(RT)

R

D

Figure 5. Switching Time Test Circuit

Figure 4. Fall Time

NOTE 1

The switching characteristics shown above were measured using a

+V

DD

R

D

R

T

OUTPUT

50

Ω

50)

)

RT)

50

test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (–VGG). The
Drain–Source Voltage (VDS) is slightly lower than Drain Supply
Voltage (VDD) due to the voltage divider. Thus Reverse Transfer
Capacitance (C
VGG + VDS.

) or Gate–Drain Capacitance (Cgd) is charged to

rss

During the turn–on interval, Gate–Source Capacitance (Cgs)
discharges through the series combination of R
must discharge to V
parallel combination of effective load impedance (R′D) an d

through RG and RK in series with the

DS(on)

and RK. C

Gen

gd

Drain–Source Resistance (rds). During the turn–off, this charge flow
is reversed.

Predicting turn–on time is somewhat difficult as the channel
resistance rds is a function of the gate–source voltage. While C
discharges, VGS approaches zero and rds decreases. Since C
discharges through rds, turn–on time is non–linear. During turn–off,

gs
gd

the situation is reversed with rds increasing as Cgd charges.

The above switching curves show two impedance conditions;

1) RK is equal to RD, which simulates the switching behavior of
cascaded stages where the driving source impedance is normally
the load impedance of the previous stage, and 2) RK = 0 (low
impedance) the driving source impedance is that of the generator.

2

Motorola Small–Signal Transistors, FETs and Diodes Device Data

20

10

15

10

7.0

J112

C

gs

7.0

5.0

3.0

, FORWARD TRANSFER ADMITTANCE (mmhos)

fs

2.0

y

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

T

= 25°C

channel

VDS = 15 V

ID, DRAIN CURRENT (mA)

Figure 6. T ypical Forward Transfer Admittance

200

I

25mA50 mA 75 mA 100 mA 125 mA

DSS
= 10

mA

160

120

80

RESISTANCE (OHMS)

, DRAIN–SOURCE ON–STATE

ds(on)

r

40

T

channel

= 25°C

5.0

3.0

C, CAPACITANCE (pF)

2.0

1.5

1.0

0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30

T

channel

(Cds IS NEGLIGIBLE)

VR, REVERSE VOLTAGE (VOLTS)

= 25°C

C

gd

Figure 7. T ypical Capacitance

2.0
ID = 1.0 mA

1.8

VGS = 0

1.6

1.4

1.2

1.0

, DRAIN–SOURCE ON–STATE

0.8

RESISTANCE (NORMALIZED)

ds(on)

r

0.6

0

0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, GATE–SOURCE VOLTAGE (VOLTS)

Figure 8. Effect of Gate–Source Voltage

On Drain–Source Resistance

100

90
80
70
60
50
40

RESISTANCE (OHMS)

, DRAIN–SOURCE ON–STATE

30
20

ds(on)

r

10

0

10

T

= 25°C

channel

r

@ VGS = 0

DS(on)

20 30 40 50 60

I

, ZERO–GATE–VOLTAGE DRAIN CURRENT (mA)

DSS

708090

Figure 10. Effect of I

100

110 120 130 140 150

On Drain–Source

DSS

V

GS(off)

Resistance and Gate–Source V oltage

10

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0
0

0.4

–70 –40 –10 20 50 80 110 140 170

T

, CHANNEL TEMPERATURE (

channel

°

C)

Figure 9. Effect of Temperature On

Drain–Source On–State Resistance

NOTE 2

The Zero–Gate–Voltage Drain Current (I
determinant of other J-FET characteristics. Figure 10 shows
the relationship of Gate–Source Off Voltage (V
Drain–Source On Resistance (r
devices will be within ±10% of the values shown in Figure 10.
This data will be useful in predicting the characteristic
variations for a given part number.

For example:

Unknown
r

and VGS range for an J112

, GATE–SOURCE VOLTAGE (VOLTS)

GS

V

ds(on)

The electrical characteristics table indicates that an J112
has an I
52 Ohms for I
The corresponding VGS values are 2.2 volts and 4.8 volts.

range of 25 to 75 mA. Figure 10, shows r

DSS

= 25 mA and 30 Ohms for I

DSS

ds(on)

), is the principle

DSS

) to I

DSS

DSS

. Most of the

GS(off)

ds(on)

= 75 mA.

and

=

Motorola Small–Signal Transistors, FETs and Diodes Device Data

3

J112

SEATING
PLANE

P ACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

A

B

R

P

L

XX

V

1

F

G

H

K

D

J

C

SECTION X–X

N

N

CASE 029–04

(TO–226AA)

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSION D AND J APPLY BETWEEN L AND K
MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.

DIM MIN MAX MIN MAX

A 0.175 0.205 4.45 5.20
B 0.170 0.210 4.32 5.33
C 0.125 0.165 3.18 4.19
D 0.016 0.022 0.41 0.55
F 0.016 0.019 0.41 0.48

G 0.045 0.055 1.15 1.39

H 0.095 0.105 2.42 2.66
J 0.015 0.020 0.39 0.50
K 0.500 ––– 12.70 –––
L 0.250 ––– 6.35 –––
N 0.080 0.105 2.04 2.66
P ––– 0.100 ––– 2.54
R 0.115 ––– 2.93 –––
V 0.135 ––– 3.43 –––

STYLE 5:

MILLIMETERSINCHES

PIN 1. DRAIN

2. SOURCE

3. GATE

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Motorola Small–Signal Transistors, FETs and Diodes Device Data

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J112/D