February 2002
ISL9N307AD3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
ISL9N307AD3ST
General Description
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
DRAIN (FLANGE)
GATE
SOURCE
Features
• Fast switching
•r
•r
•Q
•Q
•C
= 0.006Ω (Typ), VGS = 10V
DS(ON)
= 0.010Ω (Typ), VGS = 4.5V
DS(ON)
(Typ) = 28nC, VGS = 5V
g
(Typ) = 10nC
gd
(Typ) = 3000pF
ISS
D
G
S
TO-252
MOSFET Maximum Ratings
Symbol Parameter Ratings Units
V
DSS
V
GS
I
D
P
D
Drain to Source Voltage 30 V
Gate to Source Voltage ±20 V
Drain Current
Continuous (T
Continuous (T
Continuous (T
Pulsed Figure 4 A
Power dissipation
Derate above 25
= 25oC, VGS = 10V)
C
= 100oC, VGS = 4.5V) 50 A
C
= 25oC, VGS = 10V, R
C
o
C
TA = 25°C unless otherwise noted
= 52oC/W) 15 A
θJA
50 A
100
0.67
W
W/oC
Thermal Characteristics
R
θJC
R
θJA
R
θJA
Thermal Resistance Junction to Case TO-252 1.36
Thermal Resistance Junction to Ambient TO-252 100
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
N307AD ISL9N307AD3ST TO-252AA 330mm 16mm 2500 units
©2002 Fairchild Semiconductor Corporation
o
C/W
o
C/W
o
C/W
Rev. B, February 2002
ISL9N307AD3ST
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
B
I
DSS
I
GSS
VDSS
Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V
V
= 25V - - 1
Zero Gate Voltage Drain Current
DS
= 0V TC = 150
V
GS
o
- - 250
Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
V
GS(TH)
r
DS(ON)
Gate to Source Threshold Voltage VGS = VDS, ID = 250µA1-3V
I
= 50A, VGS = 10V - 0.006 0.007
Drain to Source On Resistance
D
I
= 50A, VGS = 4.5V - 0.010 0.0115
D
Dynamic Characteristics
C
ISS
C
OSS
C
RSS
Q
g(TOT)
Q
g(5)
Q
g(TH)
Q
gs
Q
gd
Input Capacitance
Output Capacitance - 580 - pF
Reverse Transfer Capacitance - 250 - pF
Total Gate Charge at 10V VGS = 0V to 10V
Total Gate Charge at 5V VGS = 0V to 5V - 28 42 nC
Threshold Gate Charge VGS = 0V to 1V - 3.0 4.5 nC
Gate to Source Gate Charge - 11 - nC
Gate to Drain “Miller” Charge - 10 - nC
Switching Characteristics
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Turn-On Time
Turn-On Delay Time - 20 - ns
Rise Time - 70 - ns
Turn-Off Delay Time - 40 - ns
Fall Time - 40 - ns
Turn-Off Time - - 120 ns
(VGS = 4.5V)
= 15V, VGS = 0V,
V
DS
f = 1MHz
V
= 15V, ID = 15A
DD
V
= 4.5V, RGS = 5.0Ω
GS
= 15V
V
DD
I
= 50A
D
= 1.0mA
I
g
-3000- pF
-5075nC
- - 135 ns
µA
Ω
Switching Characteristics
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Turn-On Time
Turn-On Delay Time - 10 - ns
Rise Time - 45 - ns
Turn-Off Delay Time - 60 - ns
Fall Time - 35 - ns
Turn-Off Time - - 143 ns
(VGS = 10V)
= 15V, ID = 15A
V
DD
= 10V, RGS = 5.0Ω
V
GS
- - 83 ns
Unclamped Inductive Switching
t
AV
Avalanche Time ID = 3.3A, L = 3mH 220 - - µs
Drain-Source Diode Characteristics
I
= 50A - - 1. 25 V
V
SD
t
rr
Q
RR
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
Source to Drain Diode Voltage
Reverse Recovery Time ISD = 50A, dISD/dt = 100A/µs- - 26 ns
Reverse Recovered Charge ISD = 50A, dISD/dt = 100A/µs- - 13 nC
SD
= 25A - - 1.0 V
I
SD
Typical Characteristic
ISL9N307AD3ST
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
125
150
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
θJC
Z
THERMAL IMPEDANCE
0.01
-5
10
-4
10
SINGLE PULSE
-3
10
t, RECTANGULAR PULSE DURATION (s)
60
V
= 10V
40
20
, DRAIN CURRENT (A)
D
I
GS
V
= 4.5V
GS
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
Figure 2. Maximum Contin uous Drain Current vs
Case Temperature
P
DM
t
1
t
x R
2
2
+ T
θJC
C
1
10
NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
-2
10
-1
10
θJC
10
0
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
1000
VGS = 10V
, PEAK CURRENT (A)
DM
I
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
40
-5
10
VGS = 5V
-4
10
-3
10
-2
10
-1
10
t, PULSE WIDTH (s)
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
I = I
25
10
C
150
0
1
10
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
ISL9N307AD3ST
Typical Characteristic
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 15V
DD
75
50
25
, DRAIN CURRENT (A)
D
I
0
TJ = 25oC
TJ = 175oC
12345
VGS, GATE TO SOURCE VOLTAGE (V)
(Continued)
TJ = -55oC
Figure 5. Transfer Ch aracteri stics Figure 6. Saturation Characteristics
20
15
ID = 28A
ID = 50A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
100
TC = 25oC
VGS = 10V
75
50
25
, DRAIN CURRENT (A)
D
I
0
00.511.52
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
VGS = 4.5V
VGS = 3.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 3V
10
, DRAIN TO SOURCE
ON RESISTANCE (mΩ)
DS(ON)
r
5
246810
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Drain to Source On Resis tanc e vs Ga te
Voltage and Drain Current
1.4
1.2
1.0
0.8
0.6
NORMALIZED GATE
THRESHOLD VOLTAGE
0.4
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
Figure 9. Normalized Gate Thres hold Volta ge v s
Junction Temperature
1.0
ON RESISTANCE
NORMALIZED DRAIN TO SOURCE
0.5
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
VGS = 10V, ID =50A
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.2
ID = 250µA
1.1
1.0
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0.9
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temp er atu re
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
ISL9N307AD3ST
Typical Characteristic
5000
C
= CGS + C
ISS
C
1000
C, CAPACITANCE (pF)
OSS
C
RSS
V
GS
100
0.1 1 10
GD
≅ C
+ C
DS
GD
= C
GD
= 0V, f = 1MHz
VDS, DRAIN TO SOURCE VOLTAGE (V)
(Continued)
Figure 11. Capacitance vs Drain to Source
Voltage
250
VGS = 4.5V, VDD = 15V, ID = 15A
200
t
150
100
SWITCHING TIME (ns)
50
0
0 1020304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
d(OFF)
t
d(ON)
10
VDD = 15V
8
6
4
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
30
0
010203040
Qg, GATE CHARGE (nC)
WAVEFORMS IN
DESCENDING ORDER:
ID = 50A
ID = 28A
50
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
350
t
r
t
f
SWITCHING TIME (ns)
VGS = 10V, VDD = 15V, ID = 15A
300
250
200
150
100
50
0
0 1020304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
t
d(OFF)
t
f
t
r
t
d(ON)
Figure 13. Switchin g Time vs Gate R esi stan ce Figure 14. Switching Tim e vs Gate R esistanc e
Test Circuits and Waveforms
V
DS
VARY tP TO OBTAIN
REQUIRED PEAK I
V
GS
t
0V
P
L
0.01Ω
+
V
DD
-
0
R
AS
G
DUT
I
AS
I
AS
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
BV
DSS
t
P
t
AV
V
DS
V
DD
ISL9N307AD3ST
R
DUT
(Continued)
L
V
DD
+
V
DD
V
0
I
g(REF)
GS
V
GS
= 1V
Q
g(TH)
Q
gs
Q
g(TOT)
V
DS
Q
g(5)
Q
gd
Test Circuits and Waveforms
V
DS
V
GS
I
g(REF)
0
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Wavef orms
V
DS
R
L
V
GS
R
GS
V
GS
DUT
+
V
DD
-
V
DS
0
V
GS
10%
0
t
d(ON)
90%
t
ON
50%
10%
t
r
PULSE WIDTH
VGS = 5V
t
d(OFF)
90%
t
OFF
50%
t
V
f
10%
GS
= 10V
90%
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
Thermal Resistance vs. Mounting Pad Area
)
)
125
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and
(oC), and thermal resistance R
A
is never exceeded.
JM
serves as the basis for establishing the rating of the part.
TJMT
–()
P
DM
A
------------------- ----------- -=
Z
θJA
DM
θJA
(EQ. 1
, in an
(oC/W)
C/W)
o
(
θJA
R
100
ISL9N307AD3ST
R
= 33.32 + 23.84/(0.268+Area)
θJA
75
50
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
DM
is
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of t he
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally
for the device as a function of the top
θJA
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
25
0.01 0.1 1 10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
Displayed on the curve are R
Electrical Specifications table. The points were chosen to
values listed in the
θJA
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
.
DM
Thermal resistances corresponding to other copper area s
can be obtained from Figure 21 or by calculation using
Equation 2. R
times a coefficient added to a constant. The area, in square
is defined as the natural log of the area
θJA
inches is the top copper area including the gate and source
pads.
=
R
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
33.32
θ
JA
23.84
-------------------------------------+
0.268 Area+()
(EQ. 2
PSPICE Electrical Model
.SUBCKT ISL9N307AD3ST 2 1 3 ; rev May 2001
CA 12 8 1.2e-9
CB 15 14 1.4e-9
CIN 6 8 2.8e-9
ISL9N307AD3ST
DBODY 7 5 DBODYMOD
DBREAK 5 11 D B REAK MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 31.6
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.48e-9
GATE
1
LSOURCE 3 7 2.13e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTR OMOD
MWEAK 16 21 8 8 MWEAK MOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.1e-3
RGATE 9 20 2.82
RLDRAIN 2 5 10
RLGATE 1 9 54.8
RLSOURCE 3 7 21.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
LGATE
RLGATE
RGATE
9
CA
ESG
EVTEMP
+
18
22
20
S1A
12
13814
S1B
EGS EDS
+
-
6
8
13
10
RSLC2
6
13
+
+
6
8
-
-
DPLCAP
EVTHRES
+
19
8
S2A
S2B
+
17
18
-
RLDRAIN
DBODY
LSOURCE
7
RLSOURCE
RVTEMP
19
VBAT
+
22
LDRAIN
5
RSLC1
51
+
5
ESLC
51
50
RDRAIN
16
21
-
MSTRO
CIN
15
CB
14
+
5
8
-
8
MMED
8
DBREAK
11
EBREAK
MWEAK
RSOURCE
RBREAK
17 18
IT
RVTHRES
DRAIN
2
SOURCE
3
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*225),5))}
.MODEL DBODYMOD D (IS = 1.6e- 11 N= 1.075 RS = 3.18e-3 TRS1 = 16e-4 TRS2 = 3e-6 CJO = 12.9e-10 TT = 8e-11 M = 0.49)
.MODEL DBREAKMOD D (RS = 0.2 2TRS1 = 8e-4 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 7.8e-1 0IS = 1e-3 0N = 10 M = 0.45)
.MODEL MMEDMOD NMOS (VTO = 2.05 KP = 7 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.83)
.MODEL MSTROMOD NMOS (VTO = 2.55 KP = 108 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKM OD NMOS (VTO = 1.7 KP = 0.05 IS = 1e-30 N = 10 T OX = 1 L = 1u W = 1u RG = 28.3 RS = .1)
.MODEL RBREAKMOD RES (TC1 = 9e-4 TC2 = -8e-8)
.MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 1e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -8e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.8e- 3TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2 VOFF= -1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF= -2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.2 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1 e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.2)
.ENDS
NOTE: For further discussion of the PSPICE mo del, consult A Ne w PSPICE Sub-Circuit for the P ower MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Special ist Con f e rence Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
SABER Electrical Model
E
REV May 20001
template ISL9N307AD3ST n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.6e-11, nl=1.075 , rs = 3.18e-3, trs1 = 16e-4, trs2 = 3e-6, cjo = 12.9e-9, tt = 8e-11, m = 0.49,)
dp..model dbreakmod = (rs =0.22, trs1 = 8e-4, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 7.8e-10, isl=10e-30, nl=10, m=0.45)
m..model mmedmod = (type=_n, vto = 2.05, kp=7, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.55, kp = 108, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.7, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -2, voff = -1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -2)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.2)
c.ca n12 n8 = 1.2e-9
c.cb n15 n14 = 1.4e-9
c.cin n6 n8 = 2.8e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
ESG
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.48e-9
l.lsource n3 n7 = 2.13e-9
GATE
1
LGATE
RLGATE
RGATE
9
EVTEMP
+
18
22
20
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u , w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9e-4, tc2 = -8e-8
res.rdrain n50 n16 = 1.1e-3, tc1 = 1.6e - 2, t c2 = 1e-5
res.rgate n9 n20 = 2.83
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.8
res.rlsource n3 n7 = 21.3
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-5
12
CA
S1A
13814
S1B
EGS EDS
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -2e-3, tc2 = -8e-6
DPLCAP
10
RSLC2
6
8
+
6
-
S2A
13
S2B
13
+
+
6
8
-
-
EVTHRES
+
19
8
CIN
15
CB
-
+
5
8
-
5
RSLC1
51
50
RDRAIN
21
MSTRO
14
ISCL
16
8
MMED
8
DBREAK
11
MWEAK
EBREAK
RSOURCE
RBREAK
17 18
IT
RVTHRES
+
17
18
-
RLDRAIN
LSOURCE
7
RLSOURCE
RVTEMP
19
VBAT
+
22
LDRAIN
DBODY
DRAIN
2
SOURC
3
ISL9N307AD3ST
spe.ebreak n11 n7 n17 n18 = 31.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc =1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/225))** 5))
}
}
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
ISL9N307AD3ST
SPICE Thermal Model
REV May 2001
ISL9N307AD3STT
CTHERM1 th 6 2.4e-3
CTHERM2 6 5 4.8e-3
CTHERM3 5 4 6.9e-3
CTHERM4 4 3 7e-3
CTHERM5 3 2 7.4e-3
CTHERM6 2 tl 2.4e-2
RTHERM1 th 6 4.6e-3
RTHERM2 6 5 1e-2
RTHERM3 5 4 3.4e-2
RTHERM4 4 3 2.2e-1
RTHERM5 3 2 3e-1
RTHERM6 2 tl 5.1e-1
SABER Thermal Model
SABER thermal model ISL9N307AD3STT
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.4e-3
ctherm.cth er m 2 6 5 = 4.8e-3
ctherm.cth er m 3 5 4 = 6.9e-3
ctherm.ctherm4 4 3 = 7e-3
ctherm.cth er m 5 3 2 = 7.4e-3
ctherm.ctherm6 2 tl = 2.4e-2
rtherm.rtherm1 th 6 = 4.6e-3
rtherm.rtherm2 6 5 = 1e-2
rtherm.rtherm3 5 4 = 3.4e-2
rtherm.rtherm4 4 3 = 2.2e-1
rtherm.rtherm5 3 2 = 3e-1
rtherm.rtherm6 2 tl = 5.1e-1
}
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
JUNCTION
th
CTHERM1
6
CTHERM2
5
CTHERM3
4
CTHERM4
3
CTHERM5
2
RTHERM6
tl
©2002 Fairchild Semiconductor Corporation Rev. B, February 2002
CTHERM6
CASE
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