Datasheet ISL95710 Datasheet (intersil)

®

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ISL95710

Digitally Controlled Potentiometer (XDCP™)

Data Sheet August 31, 2006

Terminal Voltage ±2.7V to ±5V, 128 Taps,
Up/Down Interface

The Intersil ISL95710 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a Up/Down interface.

The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS

, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile memory
and then be recalled upon a subsequent power-up operation.

The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:

• Industrial and automotive control

• Parameter and bias adjustments

• Amplifier bias and control

Pinout

ISL95710

(10 LD MSOP)

TOP VIEW

Features

• Non-V ol a ti l e So li d - State Po te ntiometer

• Up/Down Interface with Chip Select Enable

• DCP Terminal Voltage ±2.7V to ±5.5V

• 128 Wiper Tap Poin ts

- Wiper position stored in nonvolatile memory and
recalled on power-up

• 127 Resistive Elements

- Typical R

- End to end resistance range ±20%

• Low Power CMOS

- Standby current, 1µA

- Active current, 3mA max

= 2.7V to 5.5V

-V

CC

- V- = -2.7V to -5.5V

• High Reliability

- Endurance, 200,000 data changes per bit

- Register data retention, 50 years

•R

Values = 10kΩ, 50kΩ

TOTAL

• Package

-10 Ld MSOP

- Pb-free plus anneal (RoHS compliant)

tempco = ±50ppm/°C

TOTAL

FN8240.3

U/D

GND

CS

NC

1

V-

2

3

4

5

INC

10

VCC

9

R

8

L

R

W

7

R

6

H

Ordering Information

PART NUMBER

(Notes 1, 2) PART MARKING

ISL95710WIU10Z AKR 10k -40 to +85 10 Ld MSOP M10.118
ISL95710UIU10Z AKP 50k -40 to +85 10 Ld MSOP M10.118

NOTES:

1. Add “-T” suffix for tape and reel.

2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

RESISTANCE OPTION

(Ω)

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free) PKG. DWG. #

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

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ISL95710

V- (ANALOG VOLTAGE)

UP/DOWN

(U/D

INCREMENT

(INC

DEVICE SELECT

(CS

)

CONTROL

)

MEMORY

)

GND (GROUND)

GENERAL

AND

U/D

V

CC

R

H

R

W

R

L

INC

CS

V­GND

7-BIT
UP/DOWN
COUNTER

7-BIT

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

DECODER

Pin Descriptions

PIN NUMBER SYMBOL DESCRIPTION

1U/DControls the direction of wiper movement and whether the counter is incremented or decremented
2 V- Negative bias voltage for the potentiometer wiper control
3 GND Ground
4CS
5 NC No Connect. Pin is to be left unconnected
6R
7R
8R

H
W

L

9 VCC Positive logic supply voltage

10 INC

Chip select. The device is selected when the CS input is LOW. Also used to initiate a nonvolatile store

A fixed terminal for one end of the potentiometer resistor
The wiper terminal which is equivalent to the movable terminal of a potentiometer
A fixed terminal for one end of the potentiometer resistor

Increment input; negative edge triggered

ONE

OF

128

127

126

125

124

2

1

0

DETAILED

TRANSFER

GATES

RESISTOR

ARRAY

R

H

R

L

R

W

2

FN8240.3

August 31, 2006

ISL95710

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Absolute Maximum Ratings Thermal Information

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS

with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V

Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V

∆V = |V

Lead temperature (soldering 10 seconds). . . . . . . . . . . . . . . .300°C

(10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

ESD (Mil-Std 883, Method 3015). . . . . . . . . . . . . . . . . . . . . . . .>2kV

ESD Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

NOTE:

3. θ

JA

Analog Specifications Over recommended operating conditions unless otherwise stated.

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

TC

(Note 12, 13)

V

RH,VRLRH,RL

R

C

H/CL/CW

(Note 13)

I

LkgDCP

VOLTAGE DIVIDER MODE (V- @ R

INL

(Note 6)

DNL

(Note 5)
ZSerror

(Note 3)

FSerror
(Note 4)

TC

(Notes 7, 13)

RESISTOR MODE (Measurements between R

RINL

(Note 11)

RDNL

(Note 10)

Roffset

(Note 9)

, INC, U/D and VCC

(RH)-V(RL)

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

R

W

V

| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

RH to RL resistance W option 10 kΩ

U option 50 kΩ

to RL resistance tolerance -20 +20 %

R

H

Resistance Temperature Coefficient I

terminal voltage V- V

Wiper resistance V- = -5.5V; VCC = +5.5V,

Potentiometer Capacitance 10/10/25 pF

Leakage on DCP pins Voltage at pins; V- to V

; VCC @ RH; Voltage at RW = V

L

Integral non-linearity -1 1 LSB

Differential non-linearity W, U options -0.5 0.5 LSB

Zero-scale error W option 0 1 4 LSB

Full-scale error W option -4 -1 0 LSB

Ratiometric Temperature Coefficient DCP Register set at 63d,

and RL with RH not connected, or between RW and RH with RL not connected)

W

Integral non-linearity DCP register set between 20 hex and 5F hex.

Differential non-linearity W, U options -0.5 0.5 MI

Offset DCP Register set to 00 hex, W option 0 2 5 MI

= 1mA

DCP

T = -40°C to +85°C

wiper current = (V

U option 0 0.5 2

U option -2 -0.5 0

T = -40°C to +85°C

Monotonic over all tap positions

DCP Register set to 00 hex, U option 0 0.5 2

Thermal Resistance (Typical, Note 3) θ

MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . +170

Recommended Operating Conditions

Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.7V to -5.5V

TYP

(Note 1) MAX UNIT

±50 ppm/°C

70 200 Ω

±4 ppm/°C

RW

-V-)/R

CC

CC

unloaded)

TOTAL

-1 0.1 1 µA

-1 1 MI

CC

(°C/W)

JA

V

(Note 2)

(Note 2)

(Note 2)

(Note 2)

(Note 8)

(Note 8)

(Note 8)

3

FN8240.3

August 31, 2006

ISL95710

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Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

V-1

I

CC2

I

V-2

I

CCSB

I

V-SB

I

LkgDig

I

IL_CS

Vpor Power-on recall for both V- and V

V- Ramp V- ramp rate -0.2 V/ms

EEPROM SPECS

3-WIRE INTERFACE SPECS

V

V

Hysteresis

(Note 13)

Cpin INC

VCC supply current, volatile write/read CS = VIL, U/D = VIL or VIH and INC = VIL or VIH,

, RH, RW not connected

R

L

V- supply current, volatile write/read CS = VIL, U/D = VIL or VIH and INC = VIL or VIH,

VCC supply current, nonvolatile write U/D = VIL or VIH and INC = VIH, CS = transitions

V- supply current, nonvolatile write U/D = VIL or VIH and INC = VIH, CS = transitions

VCC current (standby) V

V- current (standby) V- = -5.5V, CS = V

Leakage current, at pins INC, CS, and
U/D

Leakage at CS, input low VIL = 0V -300 µA

EEPROM Endurance 200,000 Cycles
EEPROM Retention Temperature ≤ +75°C 50 Years

INC, CS, and U/D input buffer LOW

IL

voltage
INC, CS, and U/D input buffer HIGH

IH

voltage

, CS, and U/D input buffer

INC
hysteresis

, CS, and U/D pin capacitance 10 pF

R

, RH, RW not connected

L

to VIH. RL, RH, RW not connected

from V

IL

to VIH. RL, RH, RW not connected

from V

IL

= +5.5V, I2C Interface in Standby State 1 µA

CC

V

= +3.6V, I2C Interface in Standby State 1 µA

CC

IH

= -3.6V, CS = V

V­VIL or V

IH

V- -2.5 V

CC

V

CC

IH

applied at pin -10 10 µA

0.7*V

(Note 1) MAX UNIT

500 µA

-100 µA

500 µA

-3 mA

-5 µA

-2 µA

2.5 V

-0.3 0.3*V

CC

0.15*
V

CC

CC

VCC+

0.3

V

V

V

AC Electrical Specifications V

SYMBOL PARAMETER MIN TYP (Note 1) MAX UNIT

t

Cl

t

lD

t

DI

t

lL

t

lH

t

lC

t

CPHS

(Note 14)

t

CPHNS

CS to INC setup 100 ns
INC HIGH to U/D change 100 ns
U/D to INC setup 1 µs
INC LOW period 1 µs
INC HIGH period 1 µs
INC inactive to CS inactive 1 µs
CS

deselect time (STORE) 20 ms

CS deselect time (NO STORE) 1 µs

= 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated

CC

4

FN8240.3

August 31, 2006

ISL95710

www.BDTIC.com/Intersil

AC Electrical Specifications V

SYMBOL PARAMETER MIN TYP (Note 1) MAX UNIT

tIW INC to RW change 100 500 µs

t

CYC

INC input rise and fall time 500 µs

t

R, tF

NOTES:

1. Typical values are for T

2. LSB: [V(R
incremental voltage when changing from one tap to an adjacent tap.

3. ZS error = (V(R

4. FS error = [V(R

5. DNL = [V(R

6. INL = V(R

TC

7.

for i = 16 to 120 decimal. Max ( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the
temperature range.

8. MI =

9. Roffset = R
Roffset = R

10. RDNL = (R

11. RINL = [R

12.

for i = 16 to 127, T = -40°C to +85°C. Max ( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over
the temperature range.

13. This parameter is not 100% tested.

14. t

CPHS

the self-timed internal non-volatile write cycle. No CS

---------------------------------------------------------------------------------------------- x

V

|R

127

TC

R

is the minimum cycle time to be allowed for any non-volatile Write by the user. It is the time from a valid STORE condition to the end of

INC cycle time 2 µs

= +25°C and 3.3V supply voltage.

A

– V(RW)0]/127. V(RW)

W)127

– V-)/LSB.

W)0

– V+]/LSB.

W)127

– V(RW)

W)i

– (i • LSB – V(RW)0)/LSB for i = 1 to 127.

W)i

Max V RW()

()Min V RW()

Max V RW()

()Min V RW()

– R

| /127. R

0

/MI, when measuring between RW and RL.

0

/MI, when measuring between RW and RH.

127

– R

i

i-1

– (MI • i) – R0]/MI, for i = 16 to 127.

i

Max Ri()Min Ri()–[]

--------------------------------------------------------------- ­Max Ri()Min Ri()+[]2⁄

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

i

()+[]2⁄

i

and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.

127

)/MI -1, for i = 16 to 127.

= 5V ±10%, TA = Full Operating Temperature Range unless otherwise stated (Continued)

CC

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively . LSB is the

127

()–

---------------- -

×=

125°C

10

i

i

6

6

10

---------------- -=
125°C

or INC changes should be allowed.

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be steady Will be steady

May change from Low to High Will change from Low to High

May change from High to Low

Don’t Care: Changes Allowed Changing: State Not Known

N/A

5

Will change from High to Low

Center Line is High Impedance

FN8240.3

August 31, 2006

A.C. Timing

C

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CS

t

CI

INC

ISL95710

t

CYC

t

IL

t

IH

t

IC

t

CPHS

90% 90%

10%

t

CPHNS

t

ID

U/D

t

IW

R

W

NOTE (1): MI IN THE TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE WIPER POSITION.

Typical Performance Curves

120

Irw=0.6mA

100

80

60

40

WIPER RESISTANCE (Ω)

20

0

020406080100120

TAP POS I TI O N (D E CI MAL)

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

[I(RW) = V

CC/RTOTAL

] for 10kΩ (W)

T= 85ºC

T=25ºC

T= -40ºC

t

DI

(1)

MI

0.6

t

F

t

R

T = 85ºC

0.5
T = 25ºC

Isb (µA)

0.4

T = -40º

0.3

2.7 3.2 3.7 4.2 4.7 5.2

Vcc, V

FIGURE 2. STANDBY I

CC

vs V

CC

0.2

0.2

Vrh=5.5V, Vrl=-5.5V

0.1

0

DNL (LSB)

-0. 1

Vrh=2.7V, Vrl=-2.7V

-0. 2
0 20 40 60 80 100 120

TAP PO S I T I O N (D E C I MAL)

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

0.1

0

INL (LSB)

-0. 1

-0. 2
0 20406080100120

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

6

Vrh=2.7V, Vrl=-2.7V

TAP POSITION (DECIM AL)

MODE FOR 10kΩ (W)

Vrh=5.5V, Vrl=-5.5V

August 31, 2006

FN8240.3

Typical Performance Curves (Continued)

k

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ISL95710

1.6
Vrh= 2.7V, Vrl= -2 . 7 V, 1 0 k

1.2

0.8

Vrh=5.5V, Vrl=-5.5V, 10k

ZSerror (LSB)

0.4

0

-40-200 20406080

TEMPERATURE ( C)

FIGURE 5. ZSerror vs TEMPERATURE

0.1
T=25ºC

0.05

Vcc=2.7V, V-= -2 . 7 V

0

-0. 4
Vrh=5.5V, Vrl=-5.5V, 10

-0. 8

-1. 2

FSerror (LSB)

-1. 6

-2

-40 -20 0 20 40 60 8 0

TEMPERATURE (C)

FIGURE 6. FSerror vs TEMPERATURE

1

T=25º

0.8

0.6

Vrh=2.7V, Vrl=-2.7V, 10k

Vcc=2.7V, V-=-

0

RDNL (LSB)

-0.05
Vcc=5.5V, V-= -5 . 5 V

-0.1
0 20406080100120

TAP PO SIT I ON (D E C I MAL )

FIGURE 7. DNL vs TAP POSITION IN RHEOST A T MODE FOR

1

0.5

CHANGE (%)

0

TOTAL

-0. 5

-1

END TO END R

FIGURE 9. END TO END R

10kΩ (W)

Idcp= 0.57m A

Idcp= 1.16m A

-40 -2 0 0 20 40 60 80

TEMPERATURE (ºC)

% CHANGE vs

TEMPERATURE

TOTAL

0.4

0.2

RINL (LSB)

0

-0.2
0 50 100

TAP POSITION (DECIM AL)

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

10kΩ (W)

100

80

60

40

TCv (ppm/°C)

20

0

16 36 56 76 96 116

TAP PO SIT ION ( D E C I MAL )

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

Vcc=5.5V, V-=-

10k

50k

7

FN8240.3

August 31, 2006

Typical Performance Curves (Continued)

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200

10k

150

100

TCr (ppm/°C)

50

50k

0

16 36 56 76 96

TAP PO S IT IO N (D E CI MAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

ISL95710

FIGURE 12. FREQUENCY RESPONSE (1.8MHz)

FIGURE 13. WIPER MOVEMENT

Power Up and Down Requirements

In order to prevent unwanted tap position changes, or an
inadvertent store, bring the CS
concurrently with the V
potentiometer voltages must be applied after this sequence
is completed. During power-up, the data sheet parameters
for the DCP do not fully apply until 1ms after V
final value. The V

CC

ramp spec is always in effect.

CC

and INC high before or

pin on power-up. The

CC

reaches its

Pin Descriptions

RH and R

The high (R
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of R
relative position of the terminal in relation to wiper movement
direction selected by the U/D
potential on the terminal.

L

) and low (RL) terminals of the ISL95710 are

H

and RH references the

L

input and not the voltage

8

FIGURE 14. LARGE SIGNAL SETTLING TIME

R

W

Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the wiper counter.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement and
whether the wiper counter is incriminated or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the wiper
counter in the direction indicated by the logic level on the
U/D

input.

Chip Select (CS)

The device is selected when the CS input is LOW. The
current wiper counter value is stored in nonvolatile memory
when CS
After the store operation is complete the ISL95710 will be

is returned HIGH while the INC input is also HIGH.

FN8240.3

August 31, 2006

ISL95710

www.BDTIC.com/Intersil

placed in the low power standby mode until the device is
selected once again.

Principles of Operation

There are three sections of the ISL95710: the input control,
wiper counter and decode section; the nonvolatile memory;
and the resistor array. The input control section operates as
an up/down counter. The output of this wiper counter is
decoded to turn on a electronic switch connecting a point on
the resistor array to the wiper output. The contents of the
wiper counter can be stored in nonvolatile memory and
retained for future use. The resistor array is comprised of
individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the potential at that point to the wiper.

The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. The wiper counter does not wrap around when
clocked to either extreme.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for t
R
a significant amount if the wiper is moved several positions.

value for the device can temporarily be reduced by

TOTAL

(INC to RW change). The

IW

adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.

The state of U/D
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
During initial power-up CS
V

to avoid an accidental store generation.

CC

CS INC U/D MODE

L H Wiper up
L L Wiper down

H X X Standby current

H H X Standby

may be changed while CS remains LOW.

must go high along with or before

TABLE 1. MODE SELECTION

H X Store wiper position

L X No store, return to standby

L H Wiper up one position

(not recommended)

L L Wiper down one position

(not recommended)

When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.

Instructions and Programming

The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS
is selected and enabled to respond to the U/D
inputs. HIGH to LOW transitions on INC
decrement (depending on the state of the U/D
bit wiper counter. The output of this wiper counter is decoded
to select one of 128 wiper positions along the resistive array.

The value of the wiper counter is stored in nonvolatile
memory whenever CS
is also HIGH.

The system may select the ISL95710, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC
HIGH. The new wiper position will be maintained until
changed by the system or until a power-up/down cycle
recalls the previously stored data.

transitions HIGH while the INC input

set LOW the device

and INC

will increment or

input) a seven

LOW while taking CS

This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The

9

FN8240.3

August 31, 2006

ISL95710

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Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

TOP VIEW

-H-

SIDE VIEW

12

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o

θ

α

5

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 0 12/02

NOTESMIN MAX MIN MAX

-

-

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

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10

FN8240.3

August 31, 2006