®
www.BDTIC.com/Intersil
ISL9000A
Data Sheet March 11, 2008
Dual LDO with Low Noise, Very High
PSRR and Low I
ISL9000A is a high performance dual LDO capable of
sourcing 300mA current from each output. It has a low
standby current and very high PSRR and is stable with
output capacitance of 1µF to 10µF with ESR of up to 200mΩ.
The device integrates an individual Power-On-Reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to
the CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided
for connecting a noise filtering capacitor for low noise and
high-PSRR applications.
The quiescent current is typically only 42µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
Several combinations of voltage outputs are standard.
Output voltage options for each LDO range from 1.5V to
3.3V. Other output voltage options may be available upon
request.
Q
Pinout
ISL9000A
(10 LD 3X3 DFN)
TOP VIEW
VIN
EN1
EN2
CBYP
CPOR
1
2
3
4
5
VO1
10
9
VO2
8
POR2
7
POR1
6
GND
FN6391.1
Features
• Integrates two 300mA high performance LDOs
• Excellent transient response to large current steps
• ±1.8% accuracy over all operating conditions
• Excellent load regulation: < 0.1% voltage change across
full range of load current
• Low output noise: typically 30µV
@ 100µA (1.5V)
RMS
• Very high PSRR: 90dB @ 1kHz
• Extremely low quiescent current: 42µA (both LDOs active)
• Wide input voltage capability: 2.3V to 6.5V
• Low dropout voltage: typically 200mV @ 300mA
• Stable with 1µF to 10µF ceramic capacitors
• Separate enable and POR pins for each LDO
• Soft-start and staged turn-on to limit input current surge
during enable
• Current limit and overheat protection
• Tiny 10 Ld 3mmx3mm DFN package
• -40°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3 Players
• Handheld Devices including Medical Handheld
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved.
Ordering Information
www.BDTIC.com/Intersil
ISL9000A
PART NUMBER
(Notes 1, 3) PART MARKING
ISL9000AIRNNZ DEYA 3.3 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRNJZ DEWA 3.3 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRNFZ DEVA 3.3 2.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRNCZ DETA 3.3 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRMNZ DESA 3.0 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRMMZ DERA 3.0 3.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRMGZ DEPA 3.0 2.7 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRLLZ DENA 2.9 2.9 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRKNZ DELA 2.85 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRKKZ DEKA 2.85 2.85 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRKJZ DEJA 2.85 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRKFZ DEHA 2.85 2.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRKPZ DEMA 2.85 1.85 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRKCZ DEGA 2.85 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRJNZ DEEA 2.8 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRJMZ DEDA 2.8 3.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRJRZ DEFA 2.8 2.6 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRJCZ DECA 2.8 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRJBZ DEBA 2.8 1.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRGPZ DDYA 2.7 1.85 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRGCZ DDWA 2.7 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRFJZ DDVA 2.5 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRFDZ DDTA 2.5 2.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRFCZ DDSA 2.5 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRPLZ DFBA 1.85 2.9 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRPPZ DFCA 1.85 1.85 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRCJZ DDRA 1.8 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRCCZ DDPA 1.8 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRBLZ DDNA 1.5 2.9 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRBJZ DDMA 1.5 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRBCZ DDLA 1.5 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9000AIRBBZ DDKA 1.5 1.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
VO1 VOLTAGE
(V) (Note 2)
VO2 VOLTAGE
(V) (Note 2) TEMP RANGE (°C)
PACKAGE
(Pb-Free) PKG DWG. #
2
FN6391.1
March 11, 2008
ISL9000A
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
V
1, VO2 Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
O
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V
IN
+ 0.3)V
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
4. θ
JA
Tech Brief TB379.
5. For θ
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Thermal Resistance (Notes 4, 5) θ
10 Ld 3x3 DFN Package . . . . . . . . . . . 50 10
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
= -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
T
A
= 0.01µF; C
C
BYP
PARAMETER SYMBOL TEST CONDITIONS
DC CHARACTERISTICS
Supply Voltage V
Ground Current Quiescent condition: I
Shutdown Current I
UVLO Threshold V
Regulation Voltage Accuracy Initial accuracy at V
Maximum Output Current I
Internal Current Limit I
Dropout Voltage (Note 7) V
Thermal Shutdown
Temperature
AC CHARACTERISTICS
Ripple Rejection (Note 6) I
Output Noise Voltage (Note 6) I
IN
I
DD1
I
DD2
DDS
UV+
V
UV-
MAX
LIM
DO1IO
V
DO2IO
V
DO3IO
T
SD+
T
SD-
One LDO active 25 32 µA
Both LDO active 42 52 µA
@ +25°C 0.1 1.0 µA
= VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C -0.8 +0.8 %
V
IN
= VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C to
V
IN
+125°C
Continuous 300 mA
= 300mA; VO < 2.5V 300 500 mV
= 300mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV
= 300mA; VO > 2.8V 200 325 mV
= 10mA, VIN = 2.8V(min), VO = 1.8V, C
O
@ 1kHz 90 dB
@ 10kHz 70 dB
@ 100kHz 50 dB
= 100µA, VO = 1.5V, TA = +25°C, C
O
BW = 10Hz to 100kHz
POR
= 0.01µF.
IN
MIN
(Note 8) TYP
2.3 6.5 V
= 0µA; IO2 = 0µA
O1
1.9 2.1 2.3 V
1.6 1.8 2.0 V
= VO + 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 %
-1.8 +1.8 %
350 475 600 mA
= 0.1µF
BYP
= 0.1µF
BYP
(°C/W) θJC (°C/W)
JA
MAX
(Note 8) UNITS
145 °C
110 °C
30 µV
RMS
3
FN6391.1
March 11, 2008
ISL9000A
www.BDTIC.com/Intersil
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
= -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
T
A
= 0.01µF; C
C
BYP
PARAMETER SYMBOL TEST CONDITIONS
DEVICE START-UP CHARACTERISTICS
Device Enable Time t
LDO Soft-Start Ramp Rate t
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Pin Capacitance C
, POR2 PIN CHARACTERISTICS
POR1
, POR2 Thresholds V
POR1
POR1
Delay t
Delay t
POR2
, POR2 Pin Output Low
POR1
Voltage
, POR2 Pin Internal
POR1
Pull-Up Resistance
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
IL
POR+
V
P1LH
t
P1HL
P2LHCPOR
t
P2HL
V
R
Time from assertion of the ENx pin to when the output voltage
EN
reaches 95% of the VO(nom)
Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V
SSR
IL
IH
, I
IH
Informative 5 pF
PIN
As a percentage of nominal output voltage 91 94 97 %
POR-
@ IOL = 1.0mA 0.2 V
OL
POR
= 0.01µF. (Continued)
POR
MIN
(Note 8) TYP
-0.3 0.5 V
1.4 V
87 90 93 %
1.0 2.0 3.0 ms
= 0.01µF 100 200 300 ms
78 100 180 kΩ
MAX
(Note 8) UNITS
250 500 µs
+
IN
0.3
0.1 µA
25 µs
25 µs
V
4
FN6391.1
March 11, 2008
EN1
www.BDTIC.com/Intersil
EN2
t
EN
V
POR+
VO1
VO2
POR1
POR2
t
P1LH
t
P2LH
Typical Performance Curves
ISL9000A
V
V
POR-
FIGURE 1. TIMING PARAMETER DEFINITION
POR+
<t
<t
P1HL
P2HL
t
P1HL
t
P2HL
V
POR-
0.8
VO = 3.3V
I
0.6
0.4
0.2
0.0
-0.2
OUTPUT VOLTAGE, VO (%)
-0.4
-0.6
-0.8
-40°C
+25°C
+85°C
3.8 4.2 6.25.8
INPUT VOLTAGE (V)
LOAD
= 0mA
FIGURE 2. OUTPUT VOLTAGE vs INPUT VOL TAGE (3.3V
OUTPUT)
0.10
+25°C
(mA)
O
VIN = 3.8V
V
= 3.3V
O
-40°C
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
OUTPUT VOLTAGE CHANGE (%)
-0.08
6.63.4 4.6 5.0 5.4
-0.10
50 150 250 350
100 200 300 4000
LOAD CURRENT - I
+85°C
FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
5
FN6391.1
March 11, 2008
Typical Performance Curves (Continued)
www.BDTIC.com/Intersil
ISL9000A
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
OUTPUT VOLTAGE CHANGE (%)
-0.08
-0.10
VIN = 3.8V
V
= 3.3V
O
= 0mA
I
LOAD
-25 5 35 8065 95 125
-10 20 50 110-40
TEMPERATURE (°C)
3.4
IO = 0mA
3.3
(V)
O
3.2
3.1
3.0
OUTPUT VOLTAGE, V
2.9
2.8
3.1 3.6 4.1 4.6 5.1 6.15.6
IO = 150mA
IO = 300mA
INPUT VOLTAGE (V)
VO = 3.3V
FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE FIGURE 5. OUTPUT VOLT AGE vs INPUT VOLT AGE
(3.3V OUTPUT)
2.9
2.8
(V)
O
2.7
2.6
2.5
OUTPUT VOLTAGE, V
2.4
IO = 0mA
IO = 300mA
VO = 2.8V
IO = 150mA
350
300
(mV)
250
DO
200
150
100
DROPOUT VOLTAGE, V
50
VO = 2.8V
VO = 3.3V
6.5
2.3
2.63.13.64.14.65.1 6.1
INPUT VOLTAGE (V)
5.6
FIGURE 6. OUTPUT VOLT AGE vs INPUT VOL T AGE
6.5
0
50 100 150 200 250 300 350 4000
OUTPUT LOAD (mA)
FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT
(2.8V OUTPUT)
350
300
(mV)
250
DO
200
150
100
DROPOUT VOLTAGE, V
50
0
VO = 3.3V
50 100 150 200 250 300 350 4000
+85°C
OUTPUT LOAD (mA)
+25°C
-40°C
55
50
+125°C
45
40
35
GROUND CURRENT (µA)
30
25
3.0 3.5 4.58 5.5 6.0
4.0 5.0 6.5
INPUT VOLTAGE (V)
VO1 = 3.3V
V
O
IO(BOTH CHANNELS) = 0µA
+25°C
2 = 2.8V
FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
6
-40°C
FN6391.1
March 11, 2008
Typical Performance Curves (Continued)
www.BDTIC.com/Intersil
ISL9000A
200
180
160
140
120
100
GROUND CURRENT (µA)
55
50
+85°C
+25°C
-40°C
80
60
40
20
0
50 100 150 200 250 4000
LOAD CURRENT (mA)
= 3.8V
V
IN
VO1 = 3.3V
VO2 = 2.8V
350300
GROUND CURRENT (µA)
45
40
35
VIN = 3.8V
30
25
-25 5 35 8065 95 125
-10 20 50 110-40
TEMPERATURE (°C)
V
I
LOAD
BOTH OUTPUTS ON
FIGURE 10. GROUND CURRENT vs LOAD FIGURE 11. GROUND CURRENT vs TEMPERATURE
VO1 = 3.3V
V
2 = 2.8V
5
4
3
VO1
V
IN
O
I
1 = 300mA
L
I
2 = 300mA
L
3.5
3.0
2.5
2.0
POR1
POR2
= 3.3V
O
= 0µA
VO1 = 3.3V
2 = 2.8V
V
O
I
1 = 300mA
L
2 = 300mA
I
L
CPOR = 0.1µF
2
VOLTAGE (V)
1
0
1 (V)V
O
V
(V)
EN
0
3
2
1
0
5
0
VO2
1234567 10
TIME (s)
89
1.5
VOLTAGE (V)
1.0
0.5
VO1
VO2
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.00
TIME (s)
4.0 4.5
FIGURE 12. POWER-UP/POWER-DOWN FIGURE 13. POWER-UP/POWER-DOWN WITH POR SIGNALS
VO2 (10mV/DIV)
VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
IL2 = 300mA
C
1, CL2 = 1µF
L
C
= 0.01µF
BYP
4.3V
3.6V
10mV/DIV
VO = 3.3V
I
= 300mA
LOAD
C
= 1µF
LOAD
C
= 0.01µF
BYP
100 200 300 400 500 600 700 8000
TIME (µs)
FIGURE 14. TURN-ON/TURN-OFF RESPONSE
900 1000
FIGURE 15. LINE TRANSIENT RESPONSE (3.3V OUTPUT)
7
400µs/DIV
FN6391.1
March 11, 2008
Typical Performance Curves (Continued)
www.BDTIC.com/Intersil
VO = 2.8V
= 300mA
I
LOAD
= 1µF
C
LOAD
C
= 0.01µF
BYP
4.2V
3.5V
ISL9000A
VO (25mV/DIV)
= 1.8V
V
O
VIN = 2.8V
10mV/DIV
400µs/DIV
300mA
100µA
I
LOAD
100µs/DIV
FIGURE 16. LINE TRANSIENT RESPONSE (2.8V OUTPUT) FIGURE 17. LOAD TRANSIENT RESPONSE
100
90
80
70
60
50
PSRR (dB)
40
30
20
10
0
0.1 1k 10k 100k 1M
FREQUENCY (Hz)
VIN = 3.6V
= 1.8V
V
O
I
= 10mA
O
= 0.1µF
C
BYP
= 1µF
C
LOAD
1000
100
10
VIN = 3.6V
V
= 1.8V
O
I
= 10mA
LOAD
= 0.1µF
C
BYP
1
C
= 1µF
IN
= 1µF
SPECTRAL NOISE DENSITY (nV/√Hz)
C
LOAD
0.1
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
FIGURE 18. PSRR vs FREQUENCY FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY
8
FN6391.1
March 11, 2008
Pin Description
www.BDTIC.com/Intersil
ISL9000A
PIN
NUMBER
PIN
NAME TYPE DESCRIPTION
1 VIN Analog I/O Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
2 EN1 Low Voltage Compatible
LDO-1 Enable.
CMOS Input
3 EN2 Low Voltage Compatible
LDO-2 Enable.
CMOS Input
4 CBYP Analog I/O Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in
the desired noise and PSRR performance.
5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR2
LDO-2 output reaches 94% of its specified voltage level. (200ms delay per 0.01µF).
6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane.
7POR1
Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low):
Internally connected to VO1 through 100kΩ resistor.
8POR2
Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low):
Internally connected to VO2 through 100kΩ resistor.
9VO2
Analog I/O LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10 VO1 Analog I/O LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
output release after
Typical Application
VIN (2.3 TO 6.5V)
ENABLE1
ENABLE2
OFF
OFF
ON
ON
ISL9000A
1
VIN
2
EN1
3
EN2
4
CBYP
5
CPOR
C1 C2 C3 C4 C5
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
VO1
VO2
POR2
POR1
GND
10
9
8
7
6
V
V
OUT2
OUT1
V
OK
OUT2
TOO LOW
V
OK
OUT1
TOO LOW
V
OUT1
V
OUT2
RESET2
(200ms DELAY ,
C3 = 0.01µF)
RESET1
(2ms DELAY)
9
FN6391.1
March 11, 2008
Block Diagram
www.BDTIC.com/Intersil
ISL9000A
VIN
EN1
EN2
CBYP
LDO-1
UVLO
ERROR
AMPLIFIER
VREF
TRIM
IS1 1VQEN1
LDO-2
IS1
IS2
CONTROL
LOGIC
BANDGAP AND
TEMPERATURE
SENSOR
LDO
QEN1
QEN2
POR
COMPARATOR
VOK2
~1.0V
VO1
VOK1
POR1
POR2
DELAY
VO2
VO1
VO2
VOK2
POR2
VO1
100k100k
POR2
VO2
VOLTAGE
REFERENCE
GENERATOR
1.00V
0.94V
0.90V
Functional Description
The ISL9000A contains two high performance LDO’s. High
performance is achieved through a circuit that delivers fast
transient response to varying load conditions. In a quiescent
condition, the ISL9000A adjusts its biasing to achieve the
lowest standby current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
Power Control
The ISL9000A has two separate enable pins (EN1 and EN2)
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
POR1
CPOR
VOK1
POR1
DELAY
GND
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power-up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDOs power-up in their specified
sequence.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge.
10
FN6391.1
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ISL9000A
www.BDTIC.com/Intersil
If EN1 is brought high, and EN2 goes high before the VO1
output stabilizes, the ISL9000A delays the VO2 turn-on until
the VO1 output reaches its target level.
If EN2 is brought high, and EN1 goes high before VO2 starts
its output ramp, then VO1 turns on first and, the ISL9000A
delays the VO2 turn-on until the VO1 output reaches its
target level.
If EN2 is brought high, and EN1 goes high after VO2 starts
its output ramp, then the ISL9000A immediately starts to
ramp up the VO1 output.
If both EN1 and EN2 are brought high at the same time, the
VO1 output has priority, and is always powered up first.
During operation, whenever the VIN voltage drops below
about 1.8V, the ISL9000A immediately disables both LDO
outputs. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.
Reference Generation
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a
0.1µF or greater CBYP capacitor should be used. This filters
the reference noise below the 10Hz to 1kHz frequency band,
which is crucial in many noise-sensitive applications.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.
The current generator provides the references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9000A provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200mΩ. The design is performance-optimized for a 1μF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not normally needed as LDO
performance improvement is minimal.
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down
to 1V. This is compared to the 1V reference for regulation.
The resistor division ratio is programmed in the factory to
one of the following output voltages: 1.5V, 1.8V, 1.85V, 2.5V,
2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, and 3.3V.
Power-On Reset Generation
Each LDO has a separate Power-on Reset signal generation
circuit which outputs to the respective POR
signal is generated as follows:
A POR comparator continuously monitors the output of each
LDO. The LDO enters a power-good state when the output
voltage is above 94% of the expected output voltage for a
period exceeding the LDO PGOOD entry delay time (see the
following). In the power-good state, the open-drain PORx
output is in a high-impedance state. An internal 100kΩ
pull-up resistor pulls the pin up to the respective LDO output
voltage. An external resistor can be added between the
PORx
output and the LDO output for a faster rise time,
however, the PORx
external resistor to a supply greater than the associated
LDO voltage.
The power-good state is exited when the LDO output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9000A pulls the respective POR
For LDO-1, the PGOOD entry delay time is fixed at about
2ms while the PGOOD exit delay is about 25µs. For LDO-2,
the PGOOD entry and exit delays are determined by the
value of the external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.
output should not connect through an
pins. The POR
pin low .
Overheat Detection
The bandgap provides a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +145°C, one or both of the
LDO’s momentarily shut down until the die cools sufficiently.
In the overheat condition, only the LDO sourcing more than
50mA will be shut off. This does not affect the operation of
the other LDO. If both LDOs source more than 50mA and an
overheat condition occurs, both LDO outputs are disabled.
Once the die temperature falls back below about +110°C,
the disabled LDO(s) are re-enabled and soft-start
automatically takes place.
The ISL9000A provides short-circuit protection by limiting
the output current to about 475mA. If short circuited, an
output current of 475mA will cause die heating. If the short
circuit lasts long enough, the overheat detection circuit will
turn off the output.
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FN6391.1
March 11, 2008
Dual Flat No-Lead Plastic Package (DFN)
www.BDTIC.com/Intersil
ISL9000A
(DAT UM B )
6
INDEX
AREA
(DATUM A)
NX (b)
5
SECTION "C-C"
6
INDEX
AREA
SEATING
PLANE
NX L
8
A
C
D
TOP
VIEW
SIDE VIEW
D2
D2/2
12
N
N-1
e
(Nd-1)Xe
REF .
BOTTOM VIEW
(A1)
2X
A3
E2/2
NX b
5
C
L
e
CC
FOR ODD TERMINAL/SIDE
E
87
0.10
ABC0.10
2X
0.10
//
A
NX k
E2
M
9
TERMINAL TIP
0.10
0.08
L
CB
BAC
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
A 0.85 0.90 0.95 -
A1 - - 0.05 A3 0.20 REF -
b 0.20 0.25 0.30 5, 8
D 3.00 BSC -
D2 2.33 2.38 2.43 7, 8
C
E 3.00 BSC -
E2 1.59 1.64 1.69 7, 8
C
e 0.50 BSC k0.20- - L 0.35 0.40 0.45 8
N102
Nd 5 3
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
NOTESMIN NOMINAL MAX
Rev. 1 4/06
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subs idi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6391.1
March 11, 2008
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