This HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating. These features combine
to make this design an extremely efficient and
reliable device for use in a wide variety of
applications.
G
TO-220AB
IRLZ44ZPbF
PD - 95539A
IRLZ44ZPbF
IRLZ44ZSPbF
IRLZ44ZLPbF
HEXFET® Power MOSFET
D
V
= 55V
DSS
R
S
D2Pak
IRLZ44ZSPbF
DS(on)
ID = 51A
= 13.5mΩ
TO-262
IRLZ44ZLPbF
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
I
DM
PD @TC = 25°C
V
GS
E
AS (Thermally limited)
(Tested )
E
AS
I
AR
E
AR
T
J
T
STG
ParameterUnits
Continuous Drain Current, V
Continuous Drain Current, V
urren
Power Dissipation W
Linear Derating Factor W/°C
Gate-to-Source VoltageV
anche Curren
epe
Operating Junction and
Storage Temperature Range°C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com5
IRLZ44Z/S/LPbF
A
15V
L
D.U.T
I
AS
Ω
0.01
t
p
R
20V
V
V
DS
G
GS
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
DRIVER
+
V
-
DD
320
)
J
m
(
y
g
r
e
240
n
E
e
h
c
n
a
l
a
v
160
A
e
s
l
u
P
e
l
g
80
n
i
S
,
S
A
E
0
255075100125150175
I
TOP
5.7A
BOTTOM
Starting TJ, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
D
3.7A
31A
10 V
Q
GS
V
G
Fig 13a. Basic Gate Charge Waveform
0
1K
Fig 13b. Gate Charge Test Circuit
Q
GD
Charge
DUT
3.0
)
V
(
2.5
e
g
a
t
l
o
V
d
l
2.0
o
h
s
e
r
h
t
1.5
e
t
a
G
)
h
t
(
1.0
S
L
VCC
G
V
0.5
-75 -50 -25 025 50 75 100 125 150 175
ID = 250µA
TJ , Temperature ( °C )
Fig 14. Threshold Voltage Vs. Temperature
6www.irf.com
IRLZ44Z/S/LPbF
1000
Duty Cycle = Single Pulse
100
)
A
(
t
n
e
r
r
u
C
10
e
h
c
n
a
l
a
v
A
1
0.1
1.0E-061.0E-051.0E-041.0E-031.0E-021.0E-01
0.01
0.05
0.10
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
100
TOP Single Pulse
)
J
80
m
(
y
g
r
e
n
60
E
e
h
c
n
a
l
40
a
v
A
,
R
A
20
E
BOTTOM 1% Duty Cycle
ID = 31A
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
every part type.
2. Safe operation in Avalanche is allowed as long asT
not exceeded.
. This is validated for
jmax
jmax
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
avalanche pulse.
= Average power dissipation per single
D (ave)
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
= Allowable avalanche current.
av
7. ∆T = Allowable rise in junction temperature, not to exceed
T
(assumed as 25°C in Figure 15, 16).
0
255075100125150175
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
jmax
t
Average time in avalanche.
av =
D = Duty cycle in avalanche = t
Z
(D, tav) = Transient thermal resistance, see figure 11)
thJC
P
= 1/2 ( 1.3·BV·Iav) = DT/ Z
D (ave)
I
2DT/ [1.3·BV·Zth]
av =
E
AS (AR)
= P
·f
av
D (ave)·tav
thJC
www.irf.com7
is
IRLZ44Z/S/LPbF
Reverse
Recovery
Current
Driver Gate Drive
D.U.T. ISDWaveform
D.U.T. VDSWaveform
Inductor Current
Inductor Curent
* V
GS
D.U.T
+
-
R
G
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-
• di/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
+
V
DD
Re-Applied
Voltage
+
-
Period
P.W.
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P. W .
Period
VGS=10V
V
DD
I
SD
*
Fig 17. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
R
D.U.T.
D
+
V
DD
-
V
DS
V
GS
R
G
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 18b. Switching Time Waveforms
8www.irf.com
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
IRLZ44Z/S/LPbF
TO-220AB Part Marking Information
TH IS IS AN IRF1010 EXAMPLE:
LOT CODE 1789
ASS EMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
Note: "P" inass embly line position
indicates "Lead - Free"
INTERNAT IONAL
RECTIFIER
LOGO
AS S E MB L Y
LOT CODE
TO-220AB packages are not recommended for Surface Mount Application.
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com9
PAR T NUMBER
DATE CODE
YE AR 7 = 1997
WE EK 19
LINE C
IRLZ44Z/S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
THIS IS AN IRF530S WITH
LOT CODE 8024
ASS EMBL ED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
INTER NATIONAL
RECTIF IER
LOGO
ASSEMBLY
LOT CODE
F530S
OR
INTER NATIONAL
RECTIFIE R
LOGO
AS S E MB L Y
LOT CODE
F5 30S
PART NUMBER
DATE CODE
P = DESIGNATES LEAD - FREE
PRODUCT (OPTIONAL )
YEAR 0 = 2000
WEE K 02
A = AS S E MBL Y S I T E CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10www.irf.com
PART NUMBER
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
IRLZ44Z/S/LPbF
TO-262 Part Marking Information
EXAMPLE : T HIS IS AN IR L3103L
LOT CODE 1789
ASS EMBL ED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
INTE RNATIONAL
RECTIFIER
LOGO
AS S E MB L Y
LOT CODE
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com11
PART NUMBER
DATE CODE
YEAR 7 = 1 997
WEEK 19
LINE C
PART NU MBE R
DAT E CODE
P = DE S IGNAT E S L EAD -F RE E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEE K 19
A = ASSEMBLY SITE CODE
IRLZ44Z/S/LPbF
D2Pak Tape & Reel Infomation
TRR
FEED DIRECTION
TRL
FEED DIRECTION
1.85 (.073)
1.65 (.065)
10.90 (.429)
10.70 (.421)
4.10 (.161)
3.90 (.153)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
16.10 (.634)
15.90 (.626)
1.60 (.063)
1.50 (.059)
1.75 (.069)
1.25 (.049)
15.42 (.609)
15.22 (.601)
0.368 (.0145)
0.342 (.0135)
24.30 (.957)
23.90 (.941)
4.72 (.136)
4.52 (.178)
330.00
(14.173)
MAX.
NOTES :
1. CO MFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by T
RG = 25Ω, I
, starting TJ = 25°C, L = 0.166mH
Jmax
= 31A, VGS =10V. Part not
AS
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
C
eff. is a fixed capacitance that gives the
oss
same charging time as C
from 0 to 80% V
DSS
.
oss
while V
is rising
DS
This product has been designed and qualified for the Industrial market.
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
60.00 (2 .362)
MIN.
30.40 (1.197)
MAX.
4
3
Limited by T
26.40 (1.039)
24.40 (.961)
, see Fig.12a, 12b, 15, 16 for typical repetitive
Jmax
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is only applied to TO-220AB pakcage.
This is applied to D
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
R
is measured at TJ approximately 90°C
θ
2
Pak, when mounted on 1" square PCB (FR-
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2010
12www.irf.com
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