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PD- 95081A
IRLR024NPbF
IRLU024NPbF
HEXFET® Power MOSFET
l Logic-Level Gate Drive
l Surface Mount (IRLR024N)
l Straight Lead (IRLU024N)
l Advanced Process Technology
l Fast Switching
l Fully Avalanche Rated
l Lead-Free
G
D
V
= 55V
DSS
R
S
DS(on)
ID = 17A
= 0.065Ω
Description
Fifth Generation HEXFET® Power MOSFETs from International Rectifier
utilize advanced processing techniques to achieve the lowest possible onresistance per silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely efficient device for use in
a wide variety of applications.
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
D-Pak I-Pak
IRLR024NPbF IRLU024NPbF
are possible in typical surface mount applications.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 17
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 12 A
I
DM
PD @TC = 25°C Power Dissipation 45 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
T
J
T
STG
Pulsed Drain Current 72
Linear Derating Factor 0.3 W/°C
Gate-to-Source Voltage ± 16 V
Single Pulse Avalanche Energy 68 mJ
Avalanche Current 11 A
Repetitive Avalanche Energy 4.5 mJ
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θJA
R
θJA
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
Junction-to-Case ––– 3.3
Case-to-Ambient (PCB mount)** ––– 50 °C/W
Junction-to-Ambient ––– 110
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IRLR/U024NPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.061 ––– V/°C Reference to 25°C, ID = 1mA
J
––– ––– 0.065 VGS = 10V, ID = 10A
Static Drain-to-Source On-Resistance
––– ––– 0.080 Ω VGS = 5.0V, ID = 10A
––– ––– 0.110 VGS = 4.0V, ID = 9.0A
Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
Forward Transconductance 8.3 ––– ––– S VDS = 25V, ID = 11A
Drain-to-Source Leakage Current
––– ––– 25
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
VDS = 55V, VGS = 0V
µA
VGS = 16V
nA
Total Gate Charge ––– ––– 15 ID = 11A
Gate-to-Source Charge ––– ––– 3.7 nC VDS = 44V
Gate-to-Drain ("Miller") Charge ––– ––– 8.5 VGS = 5.0V, See Fig. 6 and 13
Turn-On Delay Time ––– 7.1 ––– VDD = 28V
Rise Time ––– 74 –––
Turn-Off Delay Time ––– 20 ––– RG = 12Ω, VGS = 5.0V
ns
ID = 11A
Fall Time ––– 29 ––– RD = 2.4Ω, See Fig. 10
Internal Drain Inductance 4.5
Internal Source Inductance ––– 7.5 –––
Between lead,
nH
6mm (0.25in.)
from package
and center of die contact
Input Capacitance ––– 480 ––– VGS = 0V
Output Capacitance ––– 130 ––– pF VDS = 25V
Reverse Transfer Capacitance ––– 61 ––– ƒ = 1.0MHz, See Fig. 5
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
17
72
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 11A, VGS = 0V
Reverse Recovery Time ––– 60 90 ns TJ = 25°C, IF = 11A
Reverse RecoveryCharge ––– 130 200 nC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11)
V
= 25V, starting TJ = 25°C, L = 790µH
DD
RG = 25Ω, I
I
≤ 11A, di/dt ≤ 290A/µs, V
SD
= 11A. (See Figure 12)
AS
DD
≤ V
(BR)DSS
,
This is applied for I-PAK, L
of D-PAK is measured between
S
lead and center of die contact
Uses IRLZ24N data and test conditions.
TJ ≤ 175°C
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D
S
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IRLR/U024NPbF
A
A
A
A
100
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
10
1
D
I , Drain-to-Source Current (A)
2.5V
20µs PULSE WIDTH
T = 25°C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
100
T = 25°C
J
10
J
T = 175°C
J
100
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
10
2.5V
1
D
I , Drain-to-Source Current (A)
20µs PULSE WIDTH
T = 175°C
0.1
0.1 1 10 100
V , Drain-to-Source Voltage (V)
DS
J
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
3.0
I = 18A
17 A
D
2.5
2.0
1.5
1
D
I , Drain-to-Source Current (A)
0.1
2345678910
V , Gate-to-Source Voltage (V)
GS
V = 15V
DS
20µs PULSE WIDTH
Fig 3. Typical Transfer Characteristics
(Normalized)
1.0
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperat ure (°C)
J
Fig 4. Normalized On-Resistance
V = 10V
GS
Vs. Temperature
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IRLR/U024NPbF
A
A
A
A
800
600
400
V = 0V, f = 1MHz
GS
C = C + C , C SHORTED
iss gs gd ds
C = C
rss gd
C = C + C
oss ds gd
C
iss
C
oss
C, Capacitance (pF)
200
C
rss
0
1 10 100
V , Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
15
I = 11A
D
12
9
6
3
GS
V , Gate-to-Source Voltage (V)
V = 44V
DS
V = 28V
DS
FOR TEST CIRCUIT
0
0 4 8 12 16 20
Q , Total Gate Charge (nC)
G
SEE FIGURE 13
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
T = 175°C
J
10
SD
I , Reverse Drain Current (A)
1
0.4 0.8 1.2 1.6 2.0
V , Source-to-Drain Voltage (V)
SD
T = 25°C
J
V = 0V
Fig 7. Typical Source-Drain Diode
GS
100
10
D
I , Drain Current (A)
T = 25°C
C
T = 175°C
J
Single Pulse
1
1 10 100
V , Drain-to-Source Voltage (V)
DS
Fig 8. Maximum Safe Operating Area
10µs
100µs
1ms
10ms
Forward Voltage
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IRLR/U024NPbF
R
D.U.T.
D
+
V
DD
-
20
15
R
V
DS
V
GS
G
5V
10
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
D
I , Drain Current (A)
5
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25 50 75 100 125 150 175
T , Case Temperature ( C)
C
Fig 9. Maximum Drain Current Vs.
°
10%
V
GS
t
d(on)tr
t
d(off)tf
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
thJC
1
0.20
0.10
0.05
0.02
0.01
0.1
Thermal Response (Z )
0.01
0.00001 0.0001 0.001 0.01 0.1 1
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
t , Rectangular Pulse Duration (sec)
1
J
DM
12
thJC
P
DM
t
1
C
t
2
A
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U024NPbF
A
A
15V
DRIVER
+
-
R
G
20V
V
DS
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
140
120
100
80
V
DD
60
40
20
AS
V = 25V
E , Single Pulse Avalanc he Energy (mJ)
DD
0
25 50 75 100 125 150 175
Starting T , Junction Temperature (°C)
J
I
TOP 4.5A
7.8A
BOTTOM 11A
D
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
I
+
V
-
D
Fig 13b. Gate Charge Test Circuit
DS
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IRLR/U024NPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
Period
P. W .
+
+
V
DD
-
VGS=10V
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
Fig 14. For N-Channel HEXFET
V
I
SD
®
MOSFETs
DD
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IRLR/U024NPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE:
Note: "P" in as sembly line position
8 www.irf.com
T HIS IS AN IRF R120
WIT H AS S EMBL Y
LOT CODE 1234
ASS EMBLE D ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
i ndi cates "L ead-F r ee"
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
IRFU120
12 34
PART NUMBER
IRF U120
916A
12
34
PART NUMBER
DATE CODE
P = DE S I GN AT E S LE AD- F R E E
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WE E K 1 6
A = ASSEMBLY SITE CODE
DATE CODE
YEAR 9 = 1999
WE E K 1 6
LINE A
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I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
IRLR/U024NPbF
I-Pak (TO-251AA) Part Marking Information
EXAMPLE:
THIS IS AN IRFU120
WITH ASSEMBLY
LOT CODE 5678
ASS E MBLE D ON WW 19, 1999
IN THE ASSEMBLY LINE "A"
Note: "P" in as sembl y line
position indicates "Lead-Free"
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
IRF U120
56
919A
OR
INTE RNATIONAL
RECTIF IER
LOGO
ASSEMBLY
LOT CODE
IRFU 120
56 78
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PART NUMBER
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL )
YEAR 9 = 1999
WEEK 19
A = ASSEMBLY SITE CODE
PART NUMBER
DATE CODE
78
YEAR 9 = 1999
WEEK 19
LINE A
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IRLR/U024NPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .47 6 )
11.9 ( .46 9 )
NOTES :
1. CONTROLL ING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OU TLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
FEED DIRECTION
8.1 ( .318 )
7.9 ( .312 )
16 mm
16.3 ( .641 )
15.7 ( .619 )
FEED DIRECTION
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
10 www.irf.com
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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