Datasheet IRF9143, IRF9140, IRF9141 Datasheet (Intersil)

Page 1
IRF9140
Data Sheet February 1999
-19A, -100V, 0.200 Ohm, P-Channel Power MOSFET
These are P-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits.
Formerly developmental type TA17521.
Ordering Information
PART NUMBER PACKAGE BRAND
IRF9140 TO-204AA IRF9140
NOTE: When ordering, include the entire part number.
File Number
Features
• -19A, -100V
•r
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
= 0.200
Components to PC Boards”
Symbol
D
G
2278.3
Packaging
DRAIN (FLANGE)
JEDEC TO-204AA
GATE (PIN 1)
S
SOURCE (PIN 2)
5-14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
Page 2
IRF9140
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
IRF9140 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
Maximum Power Dissipation (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
DS
D D
DM
GS
D
-100 V
-100 V
-19
-12
-76 A ±20 V 125 W
A A
Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T
AS
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
960 mJ
-55 to 150
300 260
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate to Threshold Voltage V Zero Gate Voltage Drain Current I
On-State Drain Current (Note 2) I
DSSVGS
GS(TH)VGS
DSS
D(ON)VDS
= 0V, ID = -250µA (Figure 10) -100 - - V
= VDS, ID = -250µA -2.0 - -4.0 V VDS = Rated BV VDS = 0.8 x Rated BV
> I
D(ON) xrDS(ON) Max
, VGS = 0V - - -25 µA
DSS
, VGS = 0V, TC = 125oC - - -250 µA
DSS
, VGS = -10V
-19 - - A
(Figure 7)
Gate to Source Leakage I Drain to Source On Resistance (Note 2) r
DS(ON)VGS
Forward Transconductance (Note 2) g Turn-On Delay Time t
d(ON)VDD
Rise Time t Turn-Off Delay Time t
d(OFF)
Fall Time t Total Gate Charge
Q
g(TOT)VGS
(Gate to Source + Gate to Drain) Gate to Source Charge Q Gate to Drain “Miller” Charge Q Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C Internal Drain Inductance L
Internal Source Inductance L
GSS
VGS = ±20V - - ±100 nA
= -10V, ID = -10A (Figures 8, 9) - 0.15 0.20 VDS>I
fs
D(ON) xrDS(ON) Max
= -50V, ID≈ −19A, RG = 9.1, RL = 2.3
(Figures 17, 18) MOSFET Switching Times are
r
Essentially Independent of Operating Temperature
, ID = -10A 5.0 7.0 - S
-1620ns
- 65 100 ns
-4770ns
f
= -10V, ID = -19A, VDS = 0.8 x Rated BV I
= -1.5mA (Figures 14, 19, 20)
g (REF)
Gate Charge is Essentially Independent of
gs
Operating Temperature
gd
VGS = 0V, VDS = -25V, f = 1.0MHz
ISS
(Figure 10)
OSS RSS
Measured Between the
D
Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die
Measured From The
S
Source Lead, 6mm
DSS
Modified MOSFET Sym­bol Showing the Internal Devices Inductances
D
L
D
-2890ns
,
-7090nC
-14-nC
-56-nC
- 1100 - pF
- 550 - pF
- 250 - pF
- 5.0 - nH
- 12.5 - nH
(0.25in) From the Flange
Thermal Resistance Junction to Case R Thermal Resistance Junction to Ambient R
and the Source Bonding Pad
θJC
Free Air Operation - - 30
θJA
L
S
S
--1oC/W
o
C/W
5-15
Page 3
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I Pulse Source to Drain Current
(Note 3)
SD
I
SDM
IRF9140
Modified MOSFET Symbol Showing the In­tegral Reverse P-N Junction Diode
D
- - -19 A
- - -76 A
G
S
Source to Drain Diode Voltage (Note 2) V Reverse Recovery Time t Reverse Recovered Charge Q
TJ = 25oC, ISD= -19A, VGS = 0V - - -1.5 V
SD
TJ = 150oC, ISD = 19A, dISD/dt = 100A/µs - 170 - ns
rr
TJ = 150oC, ISD = -19A, dISD/dt = 100A/µs - 0.8 - µC
RR
NOTES:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ = 25oC, L = 4µH, RG = 25, peak IAS = 19A. See Figures 15, 16.
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0.0 0 25 50 75 100 150
TC, CASE TEMPERATURE (oC)
Unless Otherwise Specified
125
-20
-15
-10
DRAIN CURRENT (A)
-5
D,
I
0
50 1000 150
TC,CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
1.0
0.5
0.2
0.1
0.1
0.05
0.02
THERMAL IMPEDANCE
0.01 10
-5
0.01
SINGLE PULSE
-4
10
-3
10
t
, RECTANGULAR PULSE DURATION (s)
1
NORMALIZED TRANSIENT
θJC,
Z
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
5-16
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
P
DM
t
1
t
t
2
θJC
2
+ T
2
C
NOTES: DUTY FACTOR: D = t1/t
= PDM x Z
PEAK T
J
-2
10
0.1 1 10
Page 4
IRF9140
Typical Performance Curves
2
10
10
OPERATION IN THIS REGION IS LIMITED BY r
1
, DRAIN CURRENT (A)
D
I
T
= MAX RATED
J
T
= 25oC
C
RJC = 1oC/W SINGLE PULSE
0.1 110
DS(ON)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Unless Otherwise Specified (Continued)
-100
10
10µs
100µs
1ms
10ms 100ms
DC
2
-80
-60
-40
, DRAIN CURRENT (A)
D
I
-20
0
VGS = -16V
-10 -20 -30 -400 -50 V
DRAIN TO SOURCE VOLTAGE (V)
DS,
VGS = -14V
VGS = -12V
VGS = -10V
VGS = -9V
VGS = -8V
VGS = -7V
VGS = -6V
VGS = -5V
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
-50
80µs PULSE TEST
-40
-30
-20
, DRAIN CURRENT (A)
D
I
-10
0
-2 -4 -6 -80 -10 V
DS,
VGS = -16V
VGS = -14V
DRAIN TO SOURCE VOLTAGE (V)
V
VGS = -9V
VGS = -8V
VGS = -7V
VGS = -6V VGS = -5V
VGS = -12V
= -10V
GS
VGS = -4V
2
-10
80µs PULSE TEST
-5
-2
-10
-5
-2
-1.0
, DRAIN CURRENT (A)
D
-5
I
-2
-0.1 0 -2-4-6-8-10
VGS, GATE TO SOURCE VOLTAGE (V)
TJ = 125oC
TJ = 25oC
TJ = -55oC
80µs PULSE TEST
VGS = -4V
-12 -14
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
0.26
80µs PULSE TEST
0.22
0.18
0.14
, DRAIN TO SOURCE
ON RESISTANCE
0.10
DS(ON)
r
0
0 -100
-20 -40
VGS = -10V
-60
ID,DRAIN CURRENT (A)
VGS = -20V
-80
FIGURE 8. DRAIN TO SOURCE ON RESISTANCEvs GATE
VOLTAGE AND DRAIN CURRENT
2.5 ID = -10A
= -10V
V
GS
2.0
1.5
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
0 60 120 160
-20-40 20 40 100 140 T
, JUNCTION TEMPERATURE (oC)
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
5-17
80-60
Page 5
IRF9140
Typical Performance Curves
1.25
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-20 20 100 160
0-40 40 80 120 140
T
, JUNCTION TEMPERATURE (oC)
J
Unless Otherwise Specified (Continued)
60-60
FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
15
80µs PULSE TEST
12
9
6
, TRANSCONDUCTANCE (S)
3
fs
g
0
-20 -40 -60 -800 -100 ID,DRAIN CURRENT (A)
TJ = -55oC
TJ = 25oC
TJ = 125oC
2000
1600
C
-20
C
C
ISS
OSS
RSS
1200
800
C, CAPACITANCE (pF)
400
0
0 -10 -30 -40 -50
V
DRAIN TO SOURCE VOLTAGE (V)
DS,
VGS = 0V, f = 1MHz C
= CGS + C
C C
ISS RSS
OSS
= C
CDS + C
GD
GD
GD
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2
10
5
TJ = 150oC
2
10
5
2
1.0 5
, SOURCE TO DRAIN CURRENT (A)
2
DR
I
0.1
0.4 0.6 0.8 1.0 1.2 1.8 VSD, SOURCE TO DRAIN VOLTAGE (V)
TJ = 25oC
1.4 1.6
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
-5
-10
-15
GATE TO SOURCE VOLTAGE (V)
GS,
V
-20
VDS = -20V
20 40 60080
Q
TOTAL GATE CHARGE (nC)
g(TOT),
ID = -24A
VDS = -50V
VDS = -80V
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5-18
Page 6
IRF9140
Test Circuits and Waveforms
V
DS
t
BV
AV
DSS
L
0
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V V
GS
t
P
AS
R
G
DUT
I
AS
0.01
-
V
DD
+
V
DD
I
AS
t
P
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
V
DS
t
ON
t
d(ON)
t
R
L
DUT
R
V
GS
G
-
V
DD
+
0
V
DS
V
GS
0
10%
r
10%
90%
50%
PULSE WIDTH
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-V
DS
12V
BATTERY
0
0.2µF
50k
I
g(REF)
CURRENT
REGULATOR
0.3µF
G
IG CURRENT
SAMPLING
RESISTOR RESISTOR
DUT
D
DUT
S
CURRENT
I
D
SAMPLING
(ISOLATED SUPPLY)
+V
DS
0
V
DS
Q
gs
V
DD
Q
gd
Q
g(TOT)
0
I
G(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
t
d(OFF)
90%
V
GS
t
OFF
50%
90%
t
f
10%
5-19
Page 7
IRF9140
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporationreserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240
5-20
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Loading...