These are P-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.
Formerly developmental type TA17521.
Ordering Information
PART NUMBERPACKAGEBRAND
IRF9140TO-204AAIRF9140
NOTE: When ordering, include the entire part number.
File Number
Features
• -19A, -100V
•r
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
= 0.200Ω
Components to PC Boards”
Symbol
D
G
2278.3
Packaging
DRAIN
(FLANGE)
JEDEC TO-204AA
GATE (PIN 1)
S
SOURCE (PIN 2)
5-14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
960mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate to Threshold VoltageV
Zero Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
DSSVGS
GS(TH)VGS
DSS
D(ON)VDS
= 0V, ID = -250µA (Figure 10)-100--V
= VDS, ID = -250µA-2.0--4.0V
VDS = Rated BV
VDS = 0.8 x Rated BV
> I
D(ON) xrDS(ON) Max
, VGS = 0V---25µA
DSS
, VGS = 0V, TC = 125oC---250µA
DSS
, VGS = -10V
-19--A
(Figure 7)
Gate to Source LeakageI
Drain to Source On Resistance (Note 2)r
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
0.26
80µs PULSE TEST
0.22
0.18
0.14
, DRAIN TO SOURCE
ON RESISTANCE
0.10
DS(ON)
r
0
0-100
-20-40
VGS = -10V
-60
ID,DRAIN CURRENT (A)
VGS = -20V
-80
FIGURE 8. DRAIN TO SOURCE ON RESISTANCEvs GATE
VOLTAGE AND DRAIN CURRENT
2.5
ID = -10A
= -10V
V
GS
2.0
1.5
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
060120160
-20-402040100140
T
, JUNCTION TEMPERATURE (oC)
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
5-17
80-60
Page 5
IRF9140
Typical Performance Curves
1.25
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-2020100160
0-404080120 140
T
, JUNCTION TEMPERATURE (oC)
J
Unless Otherwise Specified (Continued)
60-60
FIGURE 10. NORMALIZED DRAIN TOSOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
15
80µs PULSE TEST
12
9
6
, TRANSCONDUCTANCE (S)
3
fs
g
0
-20-40-60-800-100
ID,DRAIN CURRENT (A)
TJ = -55oC
TJ = 25oC
TJ = 125oC
2000
1600
C
-20
C
C
ISS
OSS
RSS
1200
800
C, CAPACITANCE (pF)
400
0
0-10-30-40-50
V
DRAIN TO SOURCE VOLTAGE (V)
DS,
VGS = 0V, f = 1MHz
C
= CGS + C
C
C
ISS
RSS
OSS
= C
≈ CDS + C
GD
GD
GD
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2
10
5
TJ = 150oC
2
10
5
2
1.0
5
, SOURCE TO DRAIN CURRENT (A)
2
DR
I
0.1
0.40.60.81.01.21.8
VSD, SOURCE TO DRAIN VOLTAGE (V)
TJ = 25oC
1.41.6
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
-5
-10
-15
GATE TO SOURCE VOLTAGE (V)
GS,
V
-20
VDS = -20V
204060080
Q
TOTAL GATE CHARGE (nC)
g(TOT),
ID = -24A
VDS = -50V
VDS = -80V
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5-18
Page 6
IRF9140
Test Circuits and Waveforms
V
DS
t
BV
AV
DSS
L
0
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
V
GS
t
P
AS
R
G
DUT
I
AS
0.01Ω
-
V
DD
+
V
DD
I
AS
t
P
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
V
DS
t
ON
t
d(ON)
t
R
L
DUT
R
V
GS
G
-
V
DD
+
0
V
DS
V
GS
0
10%
r
10%
90%
50%
PULSE WIDTH
FIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-V
DS
12V
BATTERY
0
0.2µF
50kΩ
I
g(REF)
CURRENT
REGULATOR
0.3µF
G
IG CURRENT
SAMPLING
RESISTORRESISTOR
DUT
D
DUT
S
CURRENT
I
D
SAMPLING
(ISOLATED
SUPPLY)
+V
DS
0
V
DS
Q
gs
V
DD
Q
gd
Q
g(TOT)
0
I
G(REF)
FIGURE 19. GATE CHARGE TEST CIRCUITFIGURE 20. GATE CHARGE WAVEFORMS
t
d(OFF)
90%
V
GS
t
OFF
50%
90%
t
f
10%
5-19
Page 7
IRF9140
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporationreserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
5-20
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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