These are P-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. They can be operated directly from
integrated circuits.
Formerly developmental type TA17511.
Ordering Information
PART NUMBERPACKAGEBRAND
IRF9130TO-204AAIRF9130
NOTE: When ordering, use the entire part number.
File Number
Features
• -12A, -100V
DS(ON)
= 0.30Ω
•r
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
Symbol
D
G
S
2220.3
Packaging
DRAIN
(FLANGE)
JEDEC TO-204AA
GATE (PIN 1)
SOURCE (PIN 2)
5-8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
500mJ
-55 to 150
300
o
C
o
C
NOTE:
1. TJ = 25oC to TJ = 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
D(ON)VDS
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
DS(ON)ID
Forward Transconductance (Note 2)g
Turn-On Delay Timet
d(ON)VDD
Rise Timet
Turn-Off Delay Timet
d(OFF)
Fall Timet
Total Gate Charge
Q
g(TOT)VGS
(Gate to Source + Gate to Drain)
Gate to Source ChargeQ
Gate to Drain “Miller” ChargeQ
Input CapacitanceC
Output CapacitanceC
Reverse Transfer CapacitanceC
Internal Drain InductanceL
Internal Source InductanceL
Thermal Resistance Junction to CaseR
Thermal Resistance Junction to AmbientR
DSSID
DSS
GSS
fs
r
f
gs
gd
ISS
OSS
RSS
D
S
θJC
θJA
= -250µA, VGS = 0V, (Figure 10)-100--V
= VDS, ID = -250µA-2--4V
VDS = Rated BV
VDS = 0.8 x Rated BV
> I
D(ON)
, VGS = 0V---25µA
DSS
, VGS = 0V, TC = 125oC--250µA
DSS
x r
DS(ON)MAX
, VGS = -10V-12--A
VGS = ±20V--±100nA
= -6.5A, VGS = -10V, (Figures 8, 9)-0.250.30Ω
VDS > I
D(ON)
x r
DS(ON)MAX
, ID = -6.5A
23.7-S
(Figure 12)
= 0.5 x Rated BV
RL = 5.7Ω (Figures 17, 18)
MOSFET Switching Times are Essentially
Independent of Operating Temperature
, ID≈ -6.5A, RG = 50Ω
DSS
-3060ns
-70140ns
-70140ns
-70140ns
= -10V, ID = -15A, VDS = 0.8 x Rated BV
I
= -1.5mA (Figures 14, 19, 20)
g(REF)
Gate Charge is Essentially Independent of
Operating Temperature
DSS
-2545nC
-13-nC
-12-nC
VDS = -25V, VGS = 0V, f = 1MHz
(Figure 11)
-500-pF
-300-pF
-100-pF
Measured Between the
Contact Screw on the
Flange that is Closer to
Sourceand Gate Pins and
the Center of Die
Measured From the
Source Lead, 6mm
(0.25in) From the Flange
and the Source
Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
D
L
D
G
L
S
S
-5.0-nH
-12.5-nH
--1.67oC/W
Typical Socket Mount--30
o
C/W
5-9
Page 3
IRF9130
Source to Drain Diode Specifications
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAX UNITS
Continuous Source to Drain CurrentI
Pulse Source to Drain Current
I
SDM
(Note 3)
Source to Drain Diode Voltage (Note 2)V
Reverse Recovery Timet
Reverse Recovery ChargeQ
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
1.0
0.8
0.6
0.4
, DRAIN TO SOURCE
ON RESISTANCE (Ω)
0.2
DS(ON)
r
0
VGS= -10V
0
-10
-20
ID, DRAIN CURRENT (A)
PULSE DURATION = 2µs
VGS= -20V
-30-40
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
5-11
-50
2.2
VGS = -10V, ID = -4A
1.8
1.4
1.0
ON RESISTANCE
0.6
NORMALIZED DRAIN TO SOURCE
0.2
-40040
T
, JUNCTION TEMPERATURE (oC)
J
80
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
120
Page 5
IRF9130
Typical Performance Curves
1.25
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-40040
T
, JUNCTION TEMPERATURE (oC)
J
Unless Otherwise Specified (Continued)
80120160
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
5
4
3
2
, TRANSCONDUCTANCE (S)
1
fs
g
0-4-8-12-16
TJ = -55oC
ID, DRAIN CURRENT (A)
TJ = 25oC
TJ = 125oC
PULSE DURATION = 80µs
-20
1000
800
600
400
C, CAPACITANCE (pF)
200
0
0
C
ISS
C
OSS
C
RSS
V
-10
DS
-20
, DRAIN TO SOURCE VOLTAGE (V)
VGS= 0V, f = 1MHz
C
= CGS + C
ISS
C
= C
RSS
C
≈ CDS+ C
OSS
-30-40
GD
GD
GD
-50
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-100
-10
-1.0
, SOURCE TO DRAIN CURRENT (A)
SD
I
-0.1
-0.4
TJ = 150oC
TJ = 25oC
-0.8-1.4
-1.0-1.2-1.6-1.8-0.6
, SOURCE TO DRAIN VOLTAGE (V)
V
SD
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
0
-5
VDS = -80V
-10
, GATE TO SOURCE VOLTAGE (V)
GS
V
-15
0816243240
VDS = -50V
VDS = -20V
Q
, TOTAL GATE CHARGE (nC)
g(TOT)
ID = 15A
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5-12
Page 6
IRF9130
Test Circuits and Waveforms
V
DS
VARY t
TO OBTAIN
P
REQUIRED PEAK I
0V
V
GS
t
P
AS
L
R
G
-
V
DD
+
DUT
I
AS
0.01Ω
0
V
DD
I
AS
t
P
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
BV
t
AV
DSS
V
DS
t
ON
t
d(ON)
t
R
L
DUT
R
V
GS
G
-
V
DD
+
0
V
DS
V
GS
0
10%
r
10%
90%
50%
PULSE WIDTH
FIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-V
DS
D
(ISOLATED
SUPPLY)
DUT
0
V
DS
Q
gs
Q
gd
12V
BATTERY
0.2µF
50kΩ
CURRENT
REGULATOR
0.3µF
t
d(OFF)
V
GS
t
OFF
50%
90%
90%
t
f
10%
Q
g(TOT)
S
CURRENT
I
D
SAMPLING
DUT
+V
DS
V
DD
0
I
G(REF)
G
0
I
g(REF)
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUITFIGURE 20. GATE CHARGE WAVEFORMS
5-13
Page 7
IRF9130
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
5-14
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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