Datasheet IRF7807A, IRF7807 Datasheet (International Rectifier)

PD – 91747C

IRF7807/IRF7807A

HEXFET® Chip-Set for DC-DC Converters

• N Channel Application Specific MOSFETs

• Ideal for Mobile DC-DC Converters

• Low Conduction Losses

• Low Switching Losses

Description

These new devices employ advanced HEXFET Power

1

S

2

S

3

S

4

MOSFET technology to achieve an unprecedented
balance of on-resistance and gate charge. The

SO-8

Top View

reduced conduction and switching losses make them
ideal for high efficiency DC-DC Converters that power
the latest generation of mobile microprocessors.

A pair of IRF7807 devices provides the best cost/
performance solution for system voltages, such as 3.3V
and 5V .

Device Features

IRF7807 IRF7807A
Vds 30V 30V
Rds(on) 25mΩ 25mΩ
Qg 17nC 17nC
Qsw 5.2nC
Qoss 16.8nC 16.8nC

Absolute Maximum Ratings

Parameter Symbol IRF7807 IRF7807A Units

Drain-Source V oltage V
Gate-Source Voltage V
Continuous Drain or Source 25°C I
Current (V

≥ 4.5V) 70°C 6.6 6.6

GS

Pulsed Drain Current I
Power Dissipation 25°C P

DS

GS

D

DM

D

8.3 8.3 A

66 66

30 V

±12

2.5 W

70°C 1.6
Junction & Storage Temperature Range TJ, T
Continuous Source Current (Body Diode) I
Pulsed source Current I

STG

S

SM

–55 to 150 °C

2.5 2.5 A
66 66

A

8

D

7

D

6

D

5

DG

Thermal Resistance

Parameter Max. Units

Maximum Junction-to-Ambient R

θJA

50 °C/W

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IRF7807/IRF7807A

Electrical Characteristics

IRF7807 IRF7807A

Parameter Min Typ Max Min Typ Max Units Conditions

Drain-to-Source V
Breakdown Voltage*

Static Drain-Source R
on Resistance*

Gate Threshold Voltage* V
Drain-Source Leakage I

Current*

(BR)DSS

DS

GS

DSS

30 – – 30 – – V VGS = 0V, ID = 250µA

(on) 17 2 5 17 25 mΩ VGS = 4.5V, ID = 7A

(th) 1 .0 1.0 V VDS = VGS, ID = 250µA

30 30 µA VDS = 24V, VGS = 0

150 150 V

= 24V, VGS = 0,

DS

Tj = 100°C

Gate-Source Leakage I

GSS

±100 ±100 nA VGS = ±12V

Current*

T otal Gate Charge* Q
Pre-Vth Q

Gate-Source Charge
Post-Vth Q

Gate-Source Charge
Gate to Drain Charge Q
Switch Charge* Q

(Q

+ Qgd)

gs2

Output Charge* Q
Gate Resistance R

T urn-on Delay Time t
Rise Time t
T urn-off Delay Time t
Fall Time t

g

gs1

gs2

gd

SW

oss

g

(on) 12 12 VDD = 16V

d

r

(off) 25 25 Rg = 2Ω

d

f

12 17 12 17 VGS = 5V, ID = 7A

2.1 2.1 VDS = 16V, ID = 7A

0.76 0.76 nC

2.9 2.9

3.66 5.2 3.66

14 16.8 14 16.8 VDS = 16V, VGS = 0

1.2 1.2 Ω

17 17 ns ID = 7A

66V

= 4.5V

GS

Resistive Load

Source-Drain Rating & Characteristics

Parameter Min Typ Max Min Typ Max Units Conditions

Diode Forward V
Voltage*

Reverse Recovery Q
Charge VDS = 16V, VGS = 0V, IS = 7A

Reverse Recovery Q
Charge (with Parallel

SD

rr

rr(s)

Schotkky)

1.2 1.2 V IS = 7A, VGS = 0V

80 80 nC di/dt = 700A/µs

50 50

di/dt = 700A/µs
(with 10BQ040)
VDS = 16V, VGS = 0V, IS = 7A

Notes:

 Repetitive rating; pulse width limited by max. junction temperature.
 Pulse width ≤ 300 µs; duty cycle ≤ 2%.
 When mounted on 1 inch square copper board, t < 10 sec.
 Typ = measured - Q

* Devices are 100% tested to these parameters.

oss

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)

Power MOSFET Selection for DC/DC
Converters

Control FET

Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Pow er losses in the high side switch Q1, also called the
Control FET , are impacted by the R
but these conduction losses are only about one half of
the total losses.

of the MOSFET ,

ds(on)

IRF7807/IRF7807A

Drain Current

Gate V oltage

t2

t3

t1

V

GTH

4

1

Pow er losses in the control s witch Q1 are given b y;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

I

=

()

rms




+I



+Q

()

g

Q



+



This simplified loss equation includes the terms Q
and Q

that is included in all MOSFET data sheets. The impor­tance of splitting this gate-source charge into two sub
elements, Q

the gate driver between the time that the threshold volt­age has been reached (t1) and the time the drain cur­rent rises to I
begins to change. Minimizing Q
reducing switching losses in Q1.

capacitance of the MOSFET during every switching
cycle. Figure 2 shows how Q
lel combination of the voltage dependant (non-linear)
capacitance’s Cds and Cdg when multiplied by the power
supply input buss voltage.

which are new to P ower MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source charge

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the output

oss

+ P

2

R

×

ds(on)

Q

gd

×

×

oss

2

V

×

in

i

g

V

f

×

g

V

×

×

in

and Q

gs1

gs2

(t2) at which time the drain voltage

dmax

+ P

switching




f

×

+I×





f



, can be seen from Fig 1.

oss

+ P

drive



Q

gs2



i



g

is a critical factor in

gs2

is formed by the paral-

output

×




V

f

×

in



gs2

t0

2

*

P

+

output



f

+

(



Drain V oltage

Q

V

×

rr

×

in

GS1QGS2QGD

Q

Figure 1: Typical MOSFET switching wavef orm

Synchronous FET

The power loss equation for Q2 is approximated

by;

P

P

=

loss

conduction

2

I

=

rms

()

()

g



Q

oss



+

2



P

loss

+Q

*dissipated primarily in Q1.

P

+

drive

R

×

ds(on)

V

×

f

×

g

V

×

×

in

f

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IRF7807/IRF7807A

For the synchronous MOSFET Q2, R
portant characteristic; howe ver , once again the impor-

ds(on)

is an im-

tance of gate charge must not be overlooked since it
impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con­trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
verse recovery charge Qrr both generate losses that

and re-

oss

are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be­tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca­pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn

Typical Mobile PC Application

The performance of these new devices has been tested
in circuit and correlates well with performance predic­tions generated by the system models. An advanta ge
of this new technology platform is that the MOSFETs
it produces are suitable for both control FET and syn­chronous FET applications. This has been demon­strated with the 3.3V and 5V converters. (Fig 3 and
Fig 4). In these applications the same MOSFET IRF7807
was used for both the control FET (Q1) and the syn­chronous FET (Q2). This provides a highly effective
cost/performance solution.

the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Q
potential for Cdv/dt turn on.

must be minimized to reduce the

gs1

Spice model for IRF7807 can be downloaded in ma-

chine readable format at www.irf .com.

Figure 2: Q

Characteristic

oss

3.3V Supply : Q1 = Q2=IRF7807

93
92
91
90
89
88

Efficiency (%)

87
86
85
84

11.522.533.544.55

Vin = 10V
Vin = 14V
Vin = 24V

Load Current (A)

Figure 3 Figure 4

5V Supply : Q1=Q2=IRF7807

95

94

93

92

Efficiency (%)

91

90

89

11.522.533.544.55

Vin = 10V
Vin = 14V
Vin=24V

Load Current (A)

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IRF7807/IRF7807A

Typical Characteristics

IRF7807 IRF7807A

Figure 5. Normalized On-Resistance vs. Temperature

Figure 7. Typical Gate Charge vs. Gate-to-Source V oltage

Figure 6. Normalized On-Resistance vs. Temperature

Figure 8. Typical Gate Charge vs. Gate-to-Source Voltage

Figure 9. Typical Rds(on) vs. Gate-to-Source V oltage

Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage

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IRF7807/IRF7807A

)

)

IRF7807 IRF7807A

10

°

T = 150 C

J

1

T = 25 C

J

SD

I , Reverse Drain Current (A)

V = 0 V

0.1

0.4 0.5 0.6 0.7 0.8 0.9

V ,Source-to-Drain Voltage (V

SD

°

GS

10

°

T = 150 C

J

1

T = 25 C

J

SD

I , Reverse Drain Current (A)

V = 0 V

0.1

0.4 0.5 0.6 0.7 0.8 0.9

V ,Source-to-Drain Voltage (V

SD

GS

°

Figure 11. Typical Source-Drain Diode Forward V oltage Figure 12. T ypical Source-Drain Diode F orward V oltage

100

D = 0.50

thJA

0.20

10

0.10

0.05

0.02

0.01

1

SINGLE PULSE

(THERMAL RESPONSE)

Thermal Response (Z )

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

0.1

0.001 0.01 0.1 1 10 100 1000

t , Rectangular Pulse Duration (sec)

1

J DM thJA A

1 2

P

DM

t

1

t

2

Figure 13. Maximum Eff ective Transient Thermal Impedance, Junction-to-Ambient

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Package Outline

SO-8 Outline

IRF7807/IRF7807A

Part Marking Information

SO-8

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IRF7807/IRF7807A

Tape & Reel Information

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Dimensions are shown in millimeters (inches)

TERMINAL NUMBER 1

12.3 ( .48 4 )

11.7 ( .46 1 )

8.1 ( .318 )

7.9 ( .312 )

NOTES:

1. CONTROLLING DIMENSION : M ILLIMETER.

2. ALL DIMENSIONS ARE SH O W N IN MILLIM ETER S(INCHES).

3. OUTLINE CONFO R M S TO EIA-481 & EIA-541.

330.00
(12.992)
MAX.

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

FEED DIRECTION

14.40 ( .566 )

12.40 ( .488 )

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Data and specifications subject to change without notice. 10/00

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