Datasheet IRF640NSTR, IRF640NS, IRF640NL, IRF640N Datasheet (International Rectifier)

HEXFET® Power MOSFET

10/09/00

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 18
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 13 A
I

DM

Pulsed Drain Current  72

PD @TC = 25°C Power Dissipation 150 W

Linear Derating Factor 1.0 W/°C

V

GS

Gate-to-Source Voltage ± 20 V

E

AS

Single Pulse Avalanche Energy 247 mJ

I

AR

Avalanche Current 18 A

E

AR

Repetitive Avalanche Energy 15 mJ
dv/dt Peak Diode Recovery dv/dt  8.1 V/ns
T

J

Operating Junction and -55 to +175
T

STG

Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)

Absolute Maximum Ratings

Description

V

DSS

= 200V

R

DS(on)

= 0.15Ω

ID = 18A

S

D

G

l Advanced Process Technology
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Fully Avalanche Rated
l Ease of Paralleling
l Simple Drive Requirements

D2Pak

IRF640NS

TO-220AB

IRF640N

TO-262

IRF640NL

IRF640N

IRF640NS

IRF640NL

Fifth Generation HEXFET® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer with an
extremely efficient and reliable device for use in a wide
variety of applications.

The TO-220 package is universally preferred for all
commercial-industrial applications at power dissipation levels
to approximately 50 watts. The low thermal resistance and
low package cost of the TO-220 contribute to its wide
acceptance throughout the industry.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on­resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of its
low internal connection resistance and can dissipate up to

2.0W in a typical surface mount application.
The through-hole version (IRF640NL) is available for low­profile application.

www.irf.com 1

PD - 94006

www.irf.com 2

IRF640N/S/L

S

D

G

Parameter Min. Typ. Max. Units Conditions

I

S

Continuous Source Current MOSFET symbol
(Body Diode)

––– –––

showing the

I

SM

Pulsed Source Current integral reverse
(Body Diode)

––– –––

p-n junction diode.

V

SD

Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 11A, VGS = 0V 

t

rr

Reverse Recovery Time ––– 167 251 ns TJ = 25°C, IF = 11A

Q

rr

Reverse Recovery Charge ––– 929 1394 nC di/dt = 100A/µs



t

on

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Source-Drain Ratings and Characteristics

18

72

A

Parameter Min. Typ. Max. Units Conditions

V

(BR)DSS

Drain-to-Source Breakdown Voltage 200 ––– –– – V VGS = 0V, ID = 250µA

∆V

(BR)DSS

/∆T

J

Breakdown Voltage Temp. Coefficient ––– 0.25 –– – V/°C Reference to 25°C, ID = 1mA

R

DS(on)

Static Drain-to-Source On-Resistance ––– ––– 0.15 Ω VGS = 10V, ID = 11A 

V

GS(th)

Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA

g

fs

Forward Transconductance 6.8 ––– ––– S VDS = 50V, ID = 11A 

––– ––– 25

µA

VDS = 200V, VGS = 0V

––– ––– 250 VDS = 160V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100

nA

VGS = -20V

Q

g

Total Gate Charge ––– ––– 67 ID = 11A

Q

gs

Gate-to-Source Charge ––– ––– 11 nC VDS = 160V

Q

gd

Gate-to-Drain ("Miller") Charge ––– ––– 33 VGS = 10V, See Fig. 6 and 13

t

d(on)

Turn-On Delay Time ––– 10 ––– VDD = 100V

t

r

Rise Time ––– 19 ––– ID = 11A

t

d(off)

Turn-Off Delay Time ––– 23 ––– RG = 2.5Ω

t

f

Fall Time ––– 5.5 ––– RD = 9.0Ω, See Fig. 10 

Between lead,

––– –––

6mm (0.25in.)
from package
and center of die contact

C

iss

Input Capacitance ––– 1160 ––– VGS = 0V

C

oss

Output Capacitance ––– 185 ––– VDS = 25V

C

rss

Reverse Transfer Capacitance ––– 53 ––– pF ƒ = 1.0MHz, See Fig. 5

nH

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

L

D

Internal Drain Inductance

L

S

Internal Source Inductance ––– –––

S

D

G

I

GSS

ns

4.5

7.5

I

DSS

Drain-to-Source Leakage Current

Thermal Resistance

Parameter Typ. Max. Units

R

θJC

Junction-to-Case ––– 1.0

R

θCS

Case-to-Sink, Flat, Greased Surface  0.50 ––– °C/W

R

θJA

Junction-to-Ambient ––– 62

R

θJA

Junction-to-Ambient (PCB mount) ––– 40

IRF640N/S/L

www.irf.com 3

0.01

0.1

1

10

100

0.1 1 10 100

20µs PULSE WIDTH
T = 25 C

J

°

TOP

BOTTOM

VGS
15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

V , Drain-to-Source Voltage (V)

I , Drain-to-Source Current (A)

DS

D

4.5V

0.1

1

10

100

0.1 1 10 100

20µs PULSE WIDTH
T = 175 C

J

°

TOP

BOTTOM

VGS
15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

V , Drain-to-Source Voltage (V)

I , Drain-to-Source Current (A)

DS

D

4.5V

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

0.1

1

10

100

4.0 5.0 6.0 7.0 8.0 9.0 10.0

V = 50V
20µs PULSE WIDTH

DS

V , Gate-to-Source Voltage (V)

I , Drain-to-Source Current (A)

GS

D

T = 25 C

J

°

T = 175 C

J

°

-60 -40 -20 0 20 40 60 80 100 120140 160 180

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

T , Junction Temperature( C)

R , Drain-to-Source On Resistance

(Normalized)

J

DS(on)

°

V =

I =

GS

D

10V

18A

Fig 4. Normalized On-Resistance

Vs. Temperature

www.irf.com 4

IRF640N/S/L

Fig 7. Typical Source-Drain Diode

Forward Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

0.1

1

10

100

1000

0.1 1 10 100 1000

OPERATION IN THIS AREA LIMITED

BY R

DS(on)

Single Pulse

T T= 175 C

= 25 C

°

°

J

C

V , Drain-to-Source Voltage (V)

I , Drain Current (A)I , Drain Current (A)

DS

D

10us

100us

1ms

10ms

Fig 7. Typical Source-Drain Diode

Forward Voltage

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

1 10 100 1000

VDS, Drain-to-Source Voltage (V)

0

500

1000

1500

2000

2500

C, Capacitance(pF)

Coss

Crss

Ciss

V

GS

= 0V, f = 1 MHZ

C

iss

= C

gs

+ Cgd, C

ds

SHORTED

C

rss

= C

gd

C

oss

= C

ds

+ C

gd

0 20 40 60 80

0

4

8

12

16

20

Q , Total Gate Charge (nC)

V , Gate-to-Source Voltage (V)

G

GS

I =

D

11A

V = 40V

DS

V = 100V

DS

V = 160V

DS

0.1

1

10

100

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

V ,Source-to-Drain Voltage (V)

I , Reverse Drain Current (A)

SD

SD

V = 0 V

GS

T = 25 C

J

°

T = 175 C

J

°

IRF640N/S/L

www.irf.com 5

R

D

Fig 9. Maximum Drain Current Vs.

Case Temperature

Fig 10a. Switching Time Test Circuit

V

DS

90%

10%
V

GS

t

d(on)tr

t

d(off)tf

Fig 10b. Switching Time Waveforms

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

V

GS

R

G

D.U.T.

10V

+

-

25 50 75 100 125 150 175

0

4

8

12

16

20

T , Case Temperature( C)

I , Drain Current (A)

°

C

D

Fig 9. Maximum Drain Current Vs.

Case Temperature

Fig 10a. Switching Time Test Circuit

V

DS

90%

10%
V

GS

t

d(on)tr

t

d(off)tf

Fig 10b. Switching Time Waveforms

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

V

GS

R

G

D.U.T.

10V

V

DD

25 50 75 100 125 150 175

0

4

8

12

16

20

T , Case Temperature( C)

I , Drain Current (A)

°

C

D

0.01

0.1

1

10

0.00001 0.0001 0.001 0.01 0.1 1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

1 2

J DM thJC C

P

t

t

DM

1

2

t , Rectangular Pulse Duration (sec)

Thermal Response(Z )

1

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

www.irf.com 6

IRF640N/S/L

Q

G

Q

GS

Q

GD

V

G

Charge

D.U.T.

V

DS

I

D

I

G

3mA

V

GS

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

+

-

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

t

p

V

(BR)DSS

I

AS

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

R

G

I

AS

0.01

Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

DRIVER

A

15V

20V

25 50 75 100 125 150 175

0

100

200

300

400

500

600

Starting T , Junction Temperature ( C)

E , Single Pulse Avalanche Energy (mJ)

J

AS

°

I

D

TOP
BOTTOM

4.4A

7.6A
11A

IRF640N/S/L

www.irf.com 7

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple ≤ 5%

Body Diode Forward Drop

Re-Applied
Voltage

Reverse
Recovery
Current

Body Diode Forward

Current

VGS=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

D =

P.W.

Period

+

-

+

+

+

-

-

-

Fig 14. For N-Channel HEXFET® Power MOSFETs

* V

GS

= 5V for Logic Level Devices

Peak Diode Recovery dv/dt Test Circuit







R

G

V

DD

• dv/dt controlled by R

G

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance
Current Transformer



*

www.irf.com 8

IRF640N/S/L

LEAD ASSIGNMENTS
1 - G ATE
2 - DR AIN
3 - SOURCE
4 - DR AIN

- B -

1.32 (.052)

1.22 (.048)

3X

0.55 (.022)

0.46 (.018)

2.92 (.115)

2.64 (.104)

4.69 (.185)

4.20 (.165)

3X

0.93 (.037)

0.69 (.027)

4.06 (.160)

3.55 (.140)

1.15 (.045)
MIN

6.47 (.255)

6.10 (.240)

3.78 (.149)

3.54 (.139)

- A -

10.54 (.415)

10.29 (.405)

2.87 (.113)

2.62 (.103)

15.24 (.600)

14.84 (.584)

14.09 (.555)

13.47 (.530)

3X

1.40 (.055)

1.15 (.045)

2.54 (.100)
2X

0.3 6 (.0 1 4 ) M B A M

4

1 2 3

NOTES:
1 DIM ENSION IN G & T OLE RANCIN G PER A NSI Y 1 4 .5M, 1 9 8 2 . 3 O U T LINE CON FORMS TO J E DEC OUT L IN E TO - 2 2 0 AB.
2 CONT R OLLING DIM ENS ION : INCH 4 H EAT SINK & LE AD M EASUREMENTS DO N OT INCLUDE BURRS.

TO-220AB Part Marking Information

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

PART NUMBER

INT ERN ATIO NAL
REC TI F IE R
LOG O

EXAMPLE : THIS IS AN IRF1010
W ITH ASSEMBLY
LO T C OD E 9 B 1 M

ASSEMBLY
LO T C OD E

DATE CODE
(YYWW )
YY = YEAR
WW = WEEK

9246

IRF1010

9B 1M

A

IRF640N/S/L

www.irf.com 9

D2Pak Package Outline

D

2

Pak Part Marking Information

10.16 (.400)
REF.

6.47 (.255)

6.18 (.243)

2.61 (.103)

2.32 (.091)

8.89 (.350)
REF.

- B -

1.32 (.052)

1.22 (.048)

2.79 (.110)

2.29 (.090)

1.39 (.055)

1.14 (.045)

5.28 (.208)

4.78 (.188)

4.69 (.185)

4.20 (.165)

10.54 (.415)

10.29 (.405)

- A ­2

1 3

15.49 (.610)

14.73 (.580)

3X

0.93 (.037)

0.69 (.027)

5.08 (.200)

3X

1.40 (.055)

1.14 (.045)

1.78 (.070)

1.27 (.050)

1.40 (.055)
MAX.

NOTES:
1 D IMEN S IONS AFTER SOLDER DIP .
2 DIMENS IONING & TOLE R AN C ING PER AN S I Y14.5M, 1982.
3 CONTROLLING DIMENSION : INCH.
4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS.

0.55 (.022)

0.46 (.018)

0.25 (.010) M B A M

MINIMUM RECOMMENDED FOOTPRINT

11.43 (.450)

8.89 (.350)

17.78 (.700)

3.81 (.150)

2.08 (.082)
2X

LEAD ASSIGNMENTS
1 - G ATE
2 - D RAIN
3 - S OU R C E

2.54 (.100)
2X

PART NUMBER

INTERNATIONAL
R E CT IF IER
L O GO

DATE CODE
(YYWW)
YY = YEAR
WW = WEEK

A S SE MB L Y
L O T CO DE

F530S

9 B 1 M

9246

A

www.irf.com 10

IRF640N/S/L

TO-262 Part Marking Information

TO-262 Package Outline

IRF640N/S/L

www.irf.com 11

 I

SD

≤ 11A, di/dt ≤ 344A/µs, V

DD

≤ V

(BR)DSS

,

TJ ≤ 175°C

 Repetitive rating; pulse width limited by

max. junction temperature.

Notes:

 Starting T

J

= 25°C, L = 4.2mH

RG = 25Ω, I

AS

= 11A.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.
 This is only applied to TO-220AB package

D2Pak Tape & Reel Information

3

4

4

TRR

FEED DIRECTION

1.85 (.073)

1.65 (.065)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

TRL

FEED DIRECTION

10.90 (.429)

10.70 (.421)

16.10 (.634)

15.90 (.626)

1.75 (.069)

1.25 (.049)

11.60 (.457)

11.40 (.449)

15.42 (.609)

15.22 (.601)

4.72 (.136)

4.52 (.178)

24.30 (.957)

23.90 (.941)

0.368 (.0145)

0.342 (.0135)

1.60 (.063)

1.50 (.059)

13.50 (.532)

12.80 (.504)

330.00
(14.173)
MA X.

27.40 (1.079)

23.90 (.941)

60.00 (2.362)
M IN .

30.40 (1.197)
M A X.

26.40 (1.039)

24.40 (.961 )

NOTES :

1. COMFO R M S T O EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

 This is applied to D

2

Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).

For recommended footprint and soldering techniques refer to application note #AN-994.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

IR EUROPEAN REGIONAL CENTER: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000

IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: [phone]

IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 (0) 6172 96590

IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111

IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: [phone]

IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 (0)838 4630

IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673 Tel: [phone]

Data and specifications subject to change without notice. 10/00