This N-Channel enhancementmode silicon gate power field
effect transistor is designed, tested and guaranteed to
withstand a specified level of energy in the breakdown
avalanche mode of operation. These MOSFETs are
designed for applications such as switching regulators,
switchingconverters,motordrivers,relaydrivers,anddrivers
for high power bipolar switching transistors requiring high
speed and low gate drive power. They can be operated
directly from integrated circuits.
Formerly developmental type TA09295.
Ordering Information
PART NUMBERPACKAGEBRAND
IRF250TO-204AEIRF250
NOTE: When ordering, include the entire part number.
File Number
Features
• 30A, 200V
•r
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
= 0.085Ω
Components to PC Boards”
Symbol
D
G
1825.3
Packaging
DRAIN
(FLANGE)
JEDEC TO-204AE
GATE (PIN 1)
S
TOP VIEW
SOURCE (PIN 2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
910mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
On State Drain Current (Note 2)I
D(ON)
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
0.5
0.4
0.3
0.2
, DRAIN TO SOURCE
ON RESISTANCE (Ω)
DS(ON)
0.1
r
0
80µs PULSE TEST
0
2550
VGS = 10V
75
ID, DRAIN CURRENT (A)
VGS = 20V
100
125
3.0
2.4
1.8
1.2
0.6
ON RESISTANCE VOLTAGE
NORMALIZED DRAIN TO SOURCE
0
ID = 30A
VGS = 10V
-4040-60-202060 80120120
0
T
, JUNCTION TEMPERATURE (oC)
J
100
140
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Page 5
IRF250
Typical Performance Curves
1.25
ID = 250µA
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-4040-60-202060 80120120
0100
T
, JUNCTION TEMPERATURE (oC)
J
Unless Otherwise Specified (Continued)
140
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
25
V
≥ 50V
DS
80µs PULSE TEST
20
15
10
, TRANSCONDUCTANCE (S)
5
fs
g
0
10203040050
ID, DRAIN CURRENT (A)
TJ = 25oC
TJ = 150oC
7500
VGS = 0V, f = 1MHz
C
= CGS + C
ISS
C
= C
RSS
6000
C
≈ CDS + C
OSS
4500
3000
C, CAPACITANCE (pF)
1500
0
121025
GD
GD
GD
C
ISS
C
OSS
C
RSS
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
3
10
5
2
2
10
5
2
10
5
, SOURCE TO DRAIN CURRENT (A)
2
SD
I
1
00.51.01.52.5
TJ = 150oC
TJ = 25oC
2.0
VSD, SOURCE TO DRAIN VOLTAGE (V)
2
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 30A
16
12
8
4
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
2550751000125
Q
, TOTAL GATE CHARGE (nC)
g(TOT)
VDS = 40V
VDS = 100V
VDS = 160V
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5
Page 6
IRF250
Test Circuits and Waveforms
V
DS
t
I
AS
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
L
R
G
+
V
DD
-
DUT
0V
P
I
AS
0
t
0.01Ω
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
BV
DSS
P
t
AV
V
DS
V
DD
R
G
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
CURRENT
REGULATOR
12V
BATTERY
0.2µF
50kΩ
0.3µF
t
ON
t
d(ON)
t
V
R
L
+
V
DD
-
DUT
DS
0
V
GS
0
90%
10%
r
10%
50%
PULSE WIDTH
t
d(OFF)
90%
t
OFF
50%
t
f
90%
10%
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPPLY)
SAME TYPE
AS DUT
V
DD
Q
g(TOT)
Q
gd
Q
gs
V
GS
G
I
0
g(REF)
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
6
D
S
CURRENT
I
D
SAMPLING
DUT
V
DS
0
I
V
DS
g(REF)
0
FIGURE 20. GATE CHARGE WAVEFORMS
Page 7
IRF250
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only .Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
7
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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