Datasheet IRF243, IRF242, IRF240, IRF241 Datasheet (Intersil)

Page 1
IRF240
Data Sheet March 1999
18A, 200V, 0.180 Ohm, N-Channel Power MOSFET
This N-Channel enhancementmode silicon gate power field effect transistor is an advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdownavalanchemodeof operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits.
Formerly developmental type TA17422.
Ordering Information
PART NUMBER PACKAGE BRAND
IRF240 TO-204AE IRF240
NOTE: When ordering, include the entire part number.
File Number
Features
• 18A, 200V
•r
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
= 0.180
Components to PC Boards”
Symbol
D
G
1584.3
Packaging
DRAIN (FLANGE)
JEDEC TO-204AE
GATE (PIN 1)
S
TOP VIEW
SOURCE (PIN 2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
Page 2
IRF240
Absolute Maximum Ratings T
= 25oC, Unless Otherwise Specified
C
IRF240 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
DS
D D
DM
GS
D
200 V 200 V
18 A 11 A
72 A ±20 V 125 W
Linear Derating Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T
AS
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
580 mJ
-55 to 150
300 260
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications T
= 25oC, Unless Otherwise Specified
C
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV Gate to Threshold Voltage V
GS(TH)VGS
Zero Gate Voltage Drain Current I
On-State Drain Current (Note 2) I
D(ON)
Gate to Source Leakage I Drain to Source On Resistance r
DS(ON)VGS
Forward Transconductance (Note 2) g Turn-On Delay Time t
D(ON)
Rise Time t Turn-Off Delay Time t
D(OFF)
Fall Time t Total Gate Charge
(Gate to Source + Gate to Drain) Gate to Source Charge Q Gate to Drain “Miller” Charge Q Input Capacitance C Output Capacitance C Reverse-Transfer Capacitance C Internal Drain Inductance L
Internal Source Inductance L
Thermal Resistance Junction to Case R Thermal ResistanceJunctionto Ambient R
DSSVGS
DSS
GSS
fs
r
f
Q
g
gs gd
ISS OSS RSS
D
S
θJC
θJA
= 0V, ID = 250µA (Figure 10) 200 - - V
= VDS, ID = 250µA 2.0 - 4.0 V VDS = Rated BV VDS = 0.8 x Rated BV VDS> I
D(ON) xrDS(ON)MAX
, VGS = 0V - - 25 µA
DSS
, VGS = 0V, TJ = 125oC - - 250 µA
DSS
, VGS = 10V 18 - - A
VGS = ±20V - - ±100 nA
= 10V, ID = 10A (Figures 8, 9) - 0.14 0.180 VDS= 10V, ID = 11V (Figure 12) 6.7 9.0 - S VDD= 100V, ID≈ 18A, RG = 9.1, RL = 5.3
(Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature
-1630ns
-2760ns
-4080ns
-3160ns
VGS = 10V, ID = 18A, VDS = 0.8 x Rated BV I
= 1.5mA (Figures 14, 19, 20) Gate Charge is
g(REF)
Essentially Independent of Operating Temperature
DSS
,
-4360nC
-8-nC
-27- nC
VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 1275 - pF
- 500 - pF
- 160 - pF
Measured between the Contact Screw on Header that is Closer to Source and Gate PinsandCenter of Die
Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad
Free Air Operation - - 30
Modified MOSFET Symbol Showing the Internal Devices Inductances
D
L
D
G
L
S
S
- 5.0 - nH
- 12.5 - nH
- - 1.0
o o
C/W C/W
2
Page 3
IRF240
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I Pulse Source to Drain Current
SD
I
SM
(Note 3)
Source to Drain Diode Voltage (Note 2) V Reverse Recovery Time t Reverse Recovered Charge Q
NOTES:
2. Pulse Test: Pulse width 300µs, duty cycle 2%.
3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 2.7mH, RG = 25, peak IAS = 9A. See Figures 15 and 16.
Modified MOSFET Symbol Showing the Integral Reverse P-N
D
- - 18 A
- - 72 A
Junction Diode
G
S
TJ = 25oC, ISD= 18A, VGS = 0V (Figure 13) - - 2.0 V
SD
TJ = 150oC, ISD = 18A, dISD/dt = 100A/µs - 650 - ns
rr
TJ = 150oC, ISD = 18A, dISD/dt = 100A/µs - 4.1 - µC
RR
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 50 100 150
TC, CASE TEMPERATURE (oC)
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
1.0
0.5
20
16
12
8
DRAIN CURRENT (A)
D,
I
4
0
50 75 10025 150
TC, CASE TEMPERATURE (oC)
125
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
0.1
, THERMAL IMPEDANCE
θJC
Z
0.01 10
0.2
0.1
0.05
0.02
0.01 SINGLE PULSE
-5
-4
10
-3
10
t1, RECTANGULAR PULSE DURATION (s)
-2
10
0.1 1 10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
3
P
DM
t
1
t
2
NOTES: DUTY FACTOR: D = t1/t PER UNIT BASE = R
= 1.0oCW
θJC
- TC= PDM x Z
T
JM
θJC
t
2
2
(t)
Page 4
IRF240
Typical Performance Curves
100
10
OPERATION IN THIS REGION IS LIMITED BY r
1
, DRAIN CURRENT (A)
D
I
TC = 25oC TJ = MAX RATED
SINGLE PULSE
0.1
1.0 10
DS(ON)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Unless Otherwise Specified (Continued)
40
10µs 100µs
1ms
10ms
100ms DC
2
10
3
10
32
24
16
, DRAIN CURRENT (A)
D
I
8
0
10V
8V
9V
7V
VGS = 6V
5V
4V
10 20 30 400
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
40
80µs PULSE TEST
32
24
16
, DRAIN CURRENT (A)
D
I
8
VGS = 10V VGS = 9V VGS = 8V
VGS = 7V
VGS = 6V
VGS = 5V
40
32
24
V
> I
DS
D(ON)
80µs PULSE TEST
16
, DRAIN CURRENT (A)
D
I
8
TJ = 125oC
x R
DS(ON)MAX
TJ = -55oC
TJ = 25oC
80µs PULSE TEST
50
VGS = 4V
0
123405 VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
0.5
80µs PULSE TEST
0.4
0.3
0.2
, DRAIN TO SOURCE
ON RESISTANCE ()
DS(ON)
0.1
r
0
VGS = 10V
200
40
ID, DRAIN CURRENT (A)
VGS = 20V
60 80
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TOSOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
100
0
02 10
VSD, GATE TO SOURCE VOLTAGE (V)
2.5 ID = 18A
= 10V
V
GS
2.0
1.5
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
0 80 120-40 40 160
TJ, JUNCTION TEMPERATURE (oC)
64
8
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
Page 5
IRF240
Typical Performance Curves
1.25 ID = 250µA
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
0 80 120-40 40 160
, JUNCTION TEMPERATURE (oC)
T
J
Unless Otherwise Specified (Continued)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
19.0
80µs PULSE TEST
15.2 TJ = -55oC
2000
1800
1200
800
C, CAPACITANCE (pF)
400
0
010
C
ISS
C
OSS
C
RSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
20 30
VGS = 0V, f = 1MHz C
= CGS + C
C C
ISS RSS
OSS
= C
C
GD
GD
+ C
DS
40 50
GS
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
50
20
11.4
7.6
, TRANSCONDUCTANCE (S)
3.8
fs
g
0
TJ = 25oC
TJ = 125oC
8162432040
ID, DRAIN CURRENT (A)
10
5
2
, SOURCE TO DRAIN CURRENT (A)
SD
I
1
0 0.4 0.8 1.2 2.0
TJ = 150oC
TJ = 25oC
1.6
VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 18A
16
VDS = 40V
12
8
4
GATE TO SOURCE VOLTAGE (V)
GS,
V
0
12 24 36 48060
VDS = 100V
VDS = 160V
Qg, TOTAL GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5
Page 6
IRF240
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
+
V
DD
-
DUT
0V
P
I
AS
0.01
0
t
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
P
I
AS
t
AV
V
DS
V
DD
R
G
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
CURRENT
REGULATOR
12V
BATTERY
0.2µF
50k
0.3µF
G
t
ON
t
d(ON)
t
R
L
+
V
DD
-
V
DS
0
r
90%
10%
DUT
V
GS
10%
0
50%
PULSE WIDTH
t
d(OFF)
90%
t
OFF
50%
t
f
90%
10%
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED SUPPLY)
SAME TYPE AS DUT
D
DUT
V
DD
Q
g(TOT)
Q
gd
Q
gs
V
DS
V
GS
0
I
0
g(REF)
IG CURRENT
SAMPLING
RESISTOR RESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
6
S
CURRENT
I
D
SAMPLING
V
DS
I
g(REF)
0
FIGURE 20. GATE CHARGE WAVEFORMS
Page 7
IRF240
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240
7
EUROPE
Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Loading...