This N-Channel enhancementmode silicon gate power field
effect transistor is an advanced power MOSFETs designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdownavalanchemodeof operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching converters, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17422.
Ordering Information
PART NUMBERPACKAGEBRAND
IRF240TO-204AEIRF240
NOTE: When ordering, include the entire part number.
File Number
Features
• 18A, 200V
•r
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
= 0.180Ω
Components to PC Boards”
Symbol
D
G
1584.3
Packaging
DRAIN
(FLANGE)
JEDEC TO-204AE
GATE (PIN 1)
S
TOP VIEW
SOURCE (PIN 2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
580mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate to Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
D(ON)
Gate to Source LeakageI
Drain to Source On Resistancer
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
0.5
80µs PULSE TEST
0.4
0.3
0.2
, DRAIN TO SOURCE
ON RESISTANCE (Ω)
DS(ON)
0.1
r
0
VGS = 10V
200
40
ID, DRAIN CURRENT (A)
VGS = 20V
6080
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TOSOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
100
0
0210
VSD, GATE TO SOURCE VOLTAGE (V)
2.5
ID = 18A
= 10V
V
GS
2.0
1.5
1.0
ON RESISTANCE
0.5
NORMALIZED DRAIN TO SOURCE
0
080120-4040160
TJ, JUNCTION TEMPERATURE (oC)
64
8
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4
Page 5
IRF240
Typical Performance Curves
1.25
ID = 250µA
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
080120-4040160
, JUNCTION TEMPERATURE (oC)
T
J
Unless Otherwise Specified (Continued)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
19.0
80µs PULSE TEST
15.2
TJ = -55oC
2000
1800
1200
800
C, CAPACITANCE (pF)
400
0
010
C
ISS
C
OSS
C
RSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
2030
VGS = 0V, f = 1MHz
C
= CGS + C
C
C
ISS
RSS
OSS
= C
≈ C
GD
GD
+ C
DS
4050
GS
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
50
20
11.4
7.6
, TRANSCONDUCTANCE (S)
3.8
fs
g
0
TJ = 25oC
TJ = 125oC
8162432040
ID, DRAIN CURRENT (A)
10
5
2
, SOURCE TO DRAIN CURRENT (A)
SD
I
1
00.40.81.22.0
TJ = 150oC
TJ = 25oC
1.6
VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 18A
16
VDS = 40V
12
8
4
GATE TO SOURCE VOLTAGE (V)
GS,
V
0
12243648060
VDS = 100V
VDS = 160V
Qg, TOTAL GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5
Page 6
IRF240
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
+
V
DD
-
DUT
0V
P
I
AS
0.01Ω
0
t
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
P
I
AS
t
AV
V
DS
V
DD
R
G
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
CURRENT
REGULATOR
12V
BATTERY
0.2µF
50kΩ
0.3µF
G
t
ON
t
d(ON)
t
R
L
+
V
DD
-
V
DS
0
r
90%
10%
DUT
V
GS
10%
0
50%
PULSE WIDTH
t
d(OFF)
90%
t
OFF
50%
t
f
90%
10%
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPPLY)
SAME TYPE
AS DUT
D
DUT
V
DD
Q
g(TOT)
Q
gd
Q
gs
V
DS
V
GS
0
I
0
g(REF)
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT
6
S
CURRENT
I
D
SAMPLING
V
DS
I
g(REF)
0
FIGURE 20. GATE CHARGE WAVEFORMS
Page 7
IRF240
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
7
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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