This N-Channel enhancementmode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdownavalanchemodeof operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly Developmental Type TA17421.
Ordering Information
PART NUMBERPACKAGEBRAND
IRF150TO-204AEIRF150
NOTE: When ordering, include the entire part number.
File Number
Features
• 40A, 100V
•r
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
= 0.055Ω
Components to PC Boards”
Symbol
D
G
1824.3
Packaging
DRAIN
(FLANGE)
JEDEC TO-204AE
GATE (PIN 1)
S
SOURCE (PIN 2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
L
pkg
150mJ
-55 to 150
300
260
o
C
o
C
o
C
NOTE:
1. TJ = 25oC to 125oC.
Electrical SpecificationsT
= 25oC, Unless Otherwise Specified
C
PARAMETERSYMBOLTEST CONDITIONSMINTYPMAXUNITS
Drain to Source Breakdown VoltageBV
Gate to Threshold VoltageV
GS(TH)VGS
Zero Gate Voltage Drain CurrentI
On-State Drain Current (Note 2)I
D(ON)VDS
Gate to Source Leakage CurrentI
Drain to Source On Resistance (Note 2)r
FIGURE 6. SATURATION CHARACTERISTICSFIGURE 7. TRANSFER CHARACTERISTICS
0.20
0.14
VGS = 10V
0.10
, DRAIN TO SOURCE
ON RESISTANCE (Ω)
0.06
DS(ON)
r
0.02
0160
4080
ID, DRAIN CURRENT (A)
VGS = 20V
120
NOTE: Heating effect of 2µs is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
4
2.2
ID = 14A
= 10V
V
GS
1.8
1.4
1.0
ON RESISTANCE
0.6
NORMALIZED DRAIN TO SOURCE
0.2
060120
-20-402040100140
T
, JUNCTION TEMPERATURE (oC)
J
80-60
FIGURE 9. NORMALIZED DRAIN TOSOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Page 5
IRF150
Typical Performance Curves
1.25
ID = 250µA
1.15
1.05
0.95
BREAKDOWN VOLTAGE
0.85
NORMALIZED DRAIN TO SOURCE
0.75
-2020100160
0-404080120 140
, JUNCTION TEMPERATURE (oC)
T
J
60
Unless Otherwise Specified (Continued)
FIGURE 10. NORMALIZED DRAINTOSOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
20
80µs PULSE TEST
16
12
TJ = -55oC
TJ = 25oC
TJ = 125oC
4000
3200
2400
C
ISS
1600
C
C, CAPACITANCE (pF)
800
0
010304050
VDS, DRAIN TO SOURCE VOLTAGE (V)
OSS
C
RSS
20
VGS = 0V, f = 1MHz
C
= CGS + C
C
C
ISS
RSS
OSS
= C
GD
≈ CDS + C
GD
GD
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2
2
10
TJ = 150oC
8
, TRANSCONDUCTANCE (S)
4
fs
g
0
10203040050
ID, DRAIN CURRENT (A)
10
TJ = 25oC
, SOURCE TO DRAIN CURRENT (A)
SD
I
1.0
01234
VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENTFIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 40A
FOR TEST CIRCUIT,
SEE FIGURE 19
15
10
5
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
VDS = 20V
VDS = 50V
VDS = 80V
2856841120140
Q
, TOTAL GATE CHARGE (nC)
g(TOT)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
5
Page 6
IRF150
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
TO OBTAIN
P
REQUIRED PEAK I
V
GS
AS
R
G
+
V
DD
-
DUT
0V
P
I
AS
0.01Ω
0
t
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUITFIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
P
I
AS
t
AV
V
DS
V
DD
t
ON
t
d(ON)
t
R
L
+
V
R
G
DD
-
V
DS
90%
0
r
10%
DUT
V
GS
V
GS
10%
0
50%
PULSE WIDTH
FIGURE 17. SWITCHING TIME TEST CIRCUITFIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPPLY)
SAME TYPE
AS DUT
V
DD
Q
g(TOT)
Q
gd
Q
gs
12V
BATTERY
0.2µF
50kΩ
CURRENT
REGULATOR
0.3µF
t
d(OFF)
90%
V
GS
t
OFF
50%
t
f
10%
90%
D
V
DS
S
CURRENT
I
D
SAMPLING
DUT
0
V
DS
I
G(REF)
0
G
I
0
g(REF)
IG CURRENT
SAMPLING
RESISTORRESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUITFIGURE 20. GATE CHARGE WAVEFORMS
6
Page 7
IRF150
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
7
EUROPE
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
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