Specifically designed for Automotive applications, this
design of HEXFET
processing techniques to achieve extremely low onresistance per silicon area. Additional features of this
HEXFET power MOSFET are a 175°C junction operating
temperature, fast switching speed and improved repetitive
avalanche rating. These combine to make this design an
extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications.
®
Power MOSFETs utilizes the lastest
TO-220AB
Absolute Maximum Ratings
ParameterMax.Units
ID @ TC = 25°CContinuous Drain Current, VGS @ 10V (Silicon limited)240
ID @ TC = 100°CContinuous Drain Current, VGS @ 10V (See Fig.9)170A
ID @ TC = 25°CContinuous Drain Current, VGS @ 10V (Package limited)75
I
DM
PD @TC = 25°CPower Dissipation330W
V
GS
E
AS
E
(tested)Single Pulse Avalanche Energy Tested Value980
AS
I
AR
E
AR
T
J
T
STG
Pulsed Drain Current 960
Linear Derating Factor2.2W/°C
Gate-to-Source Voltage ± 20V
Single Pulse Avalanche Energy510mJ
Avalanche CurrentSee Fig.12a, 12b, 15, 16A
Repetitive Avalanche EnergymJ
Operating Junction and-55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds300 (1.6mm from case )
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com5
Page 6
IRF1503
A
15V
DRIVER
+
-
V
DD
R
20V
V
V
DS
G
GS
L
D.U.T
I
AS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
1000
TOP
800
600
400
200
AS
E , Single Pulse Avalanche Energy (mJ)
0
255075100125150175
Starting T , Junction Temperature( C)
J
BOTTOM
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
4. 0
I
°
D
59A
100A
140A
)
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
G
Current Sampling Resistors
+
V
DS
-
I
D
Fig 13b. Gate Charge Test Circuit
V
(
e
g
a
t
l
o
3. 0
V
d
l
o
h
s
e
r
h
t
e
t
a
2. 0
G
)
h
t
(
S
G
V
1. 0
-75 -50 -25 0 25 50 75 100 125 150 175 200
ID = 250µA
TJ , Temperature ( °C )
Fig 14. Threshold Voltage Vs. Temperature
6www.irf.com
Page 7
IRF1503
10000
Duty Cycle = Single Pulse
1000
)
A
(
t
n
e
r
r
u
C
100
e
h
c
n
a
l
a
v
A
10
1
1.0E-071.0E-061.0E-051.0E-041.0E-031.0E-021.0E-01
0.01
0.05
0.10
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
600
TOP Single Pulse
500
)
J
m
(
y
g
400
r
e
n
E
e
300
h
c
n
a
l
a
v
200
A
,
R
A
E
100
BOTTOM 50% Duty Cycle
ID = 140A
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
every part type.
2. Safe operation in Avalanche is allowed as long asT
not exceeded.
. This is validated for
jmax
jmax
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
avalanche pulse.
= Average power dissipation per single
D (ave)
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
= Allowable avalanche current.
av
7. ∆T = Allowable rise in junction temperature, not to exceed
T
(assumed as 25°C in Figure 15, 16).
0
255075100125150175
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
jmax
t
Average time in avalanche.
av =
D = Duty cycle in avalanche = t
Z
(D, tav) = Transient thermal resistance, see figure 11)
thJC
P
= 1/2 ( 1.3·BV·Iav) = DT/ Z
D (ave)
I
2DT/ [1.3·BV·Zth]
av =
E
= P
AS (AR)
·f
av
D (ave)·tav
thJC
www.irf.com7
is
Page 8
IRF1503
+
-
+
-
Reverse
Recovery
Current
Driver Gate Drive
P.W.
D.U.T. ISDWaveform
D.U.T. VDSWaveform
D.U.T
+
-
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-
+
V
DD
R
G
• dv/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
Re-Applied
Voltage
Inductor Curent
* V
GS
Period
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P. W .
Period
VGS=10V
V
DD
I
SD
*
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
1 DIMENSION ING & TO LERAN CING PER AN SI Y14.5M, 19 82. 3 OUTLINE C ONFOR MS TO JEDEC OUTLIN E TO-220A B.
2 C ONTRO LLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
2X
0.69 (. 027)
0.36 (.014) M B A M
2.92 ( .115)
2.64 ( .104)
Part Marking Information
TO-220AB
EXAMPLE : THIS IS AN IRF1010
WITH ASSEMBLY
LOT CODE 9B1M
TO-220AB package is not recommended for Surface Mount Application.
This product has been designed and qualified for Automotive [Q101]market.
INTERNATIONAL
RECTIFIER
LOGO
IRF1010
9246
9B 1M
ASSEMBLY
LOT CODE
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
3X
0.55 (. 022)
0.46 (. 018)
PART NUMBER
DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/02
www.irf.com9
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