Datasheet IRF1405PbF Datasheet

AUTOMOTIVE MOSFET

yp

PD - 94969A

Typical Applications

l Electric Power Steering (EPS)
l Anti-lock Braking System (ABS)
l Wiper Control
l Climate Control
l Power Door

Benefits

l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating
l 175°C Operating Temperature
l Fast Switching
l Repetitive Avalanche Allowed up to Tjmax
l Lead-Free

G

IRF1405PbF

HEXFET® Power MOSFET

D

V

= 55V

DSS

R

S

D

= 5.3mΩ

DS(on)

ID = 169A

Description

Specifically designed for Automotive applications, this Stripe
Planar design of HEXFET® Power MOSFETs utilizes the latest
processing techniques to achieve extremely low on-resistance
per silicon area. Additional features of this HEXFET power
MOSFET are a 175°C junction operating temperature, fast
switching speed and improved repetitive avalanche rating.
These benefits combine to make this design an extremely
efficient and reliable device for use in Automotive applications
and a wide variety of other applications.

TO-220AB

S

D

G

Absolute Maximum Ratings

Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V

@ TC = 100°C Continuous Drain Current, VGS @ 10V

I

D

I

DM

PD @TC = 25°C

V

GS

E

AS

I

AR

E

AR

dv/dt Peak Diode recovery dv/dt
T

J

T

STG

Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy

Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw

c

d

c

i

e

See Fig.12a, 12b, 15, 16

300 (1.6mm from case )

Max.

169
118

680
330

2.2

± 20

560

5.0

-55 to + 175

y

in (1.1Nym)

10 lbf

h
h

A

W

W/°C

V

mJ

A

mJ

V/ns

°C

Thermal Resistance

Parameter T

R

θJC

R

θCS

R

θJA

Junct ion-to-Case ––– 0.45
Case-to-Sink, Flat, Greased Surface 0.50 –––
Junct ion-to-Ambient ––– 62

. Max.

Units

°C/W

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11/12/08

IRF1405PbF

(BR)

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V

(BR)DSS

∆V
R

DS(on)

V

GS(th)

Drain-to-Source Breakdown Voltage 55 ––– ––– V

/∆T

Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C

DSS

J

Static Drain-to-Source On-Resistance ––– 4.6 5.3

Gate Threshold Voltage 2.0 ––– 4.0 V
gfs Forward Transconductance 69 ––– ––– S
I

DSS

Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250

I

GSS

Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200
Q
Q
Q
t
t
t
t
L

L

C
C
C
C
C
C

g

gs

gd

d(on)

r

d(off)

f

D

S

iss

oss

rss

oss

oss

oss

eff.

Total Gate Charge ––– 170 260

Gate-to-Source Charge ––– 44 66 nC

Gate-to-Drain ("Miller") Charge ––– 62 93

Turn-On Delay Time ––– 13 –––

Rise Time ––– 190 –––

Turn-Off Delay Time ––– 130 ––– ns

Fall Time ––– 110 –––

Internal Drain Inductance Between lead,

Internal Source Inductance from package

–––

4.5–––

–––

–––7.5

Input Capacitance ––– 5480 –––

Output Capacitance ––– 1210 –––

Reverse Transfer Capacitance ––– 280 ––– pF

Output Capacitance ––– 5210 –––

Output Capacitance ––– 900 –––

Effective Output Capacitance

g

–––1500–––

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units

I

S

I

SM

V

SD

t

rr

Q

rr

t

on

Continuous Source Current

(Body Diode) A

Pulsed Source Current

(Body Diode)

c

––– ––– 169

––– ––– 680

h

Diode Forward Voltage ––– ––– 1.3 V

Reverse Recovery Time ––– 88 130 ns

Reverse Recovery Charge ––– 250 380 nC

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

VGS = 0V, ID = 250µA
Reference to 25°C, I
V

mΩ

VDS = VGS, ID = 250µA
V
V
V
V
V
I

D

V
V
VDD = 38V
I

D

R
VGS = 10V

nH 6mm (0.25in.)

and center of die contact
VGS = 0V

V

ƒ = 1.0MHz, See Fig.5
V
V
V

MOSFET symbol
showing the
integral reverse
p-n junction diode.
T
TJ = 25°C, IF = 101A

di/dt = 100A/µs

Conditions

= 1mA

D

= 10V, ID = 101A

GS

= 25V, ID = 101A

DS

= 55V, VGS = 0V

DS

= 44V, VGS = 0V, TJ = 150°C

DS

= 20V

GS

= -20V

GS

f

= 101A

= 44V

DS

f

= 10V

GS

= 101A

Ω

= 1.1

G

f

G

= 25V

DS

= 0V, VDS = 1.0V, ƒ = 1.0MHz

GS

= 0V, VDS = 44V, ƒ = 1.0MHz

GS

= 0V, VDS = 0V to 44V

GS

Conditions

= 25°C, IS = 101A, VGS = 0V

J

f

D

S

f

Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Starting T

RG = 25Ω, I

 I

SD

= 25°C, L = 0.11mH

J

= 101A. (See Figure 12).

AS

≤ 101A, di/dt ≤ 210A/µs, V

DD

≤ V

(BR)DSS

TJ ≤ 175°C

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

 C

eff. is a fixed capacitance that gives the same charging time

oss

as C

oss

while V

is rising from 0 to 80% V

DS

DSS

.
 Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.

,

 Limited by T

, see Fig.12a, 12b, 15, 16 for typical repetitive

Jmax

avalanche performance.

2 www.irf.com

IRF1405PbF

1000

100

10

D

I , Drain-to-Source Current (A)

1

0.1 1 10 100

1000

VGS

TOP

15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM

4.5V

4.5V

20µs PULSE WIDTH
T = 25 C

J

V , Drain-to-Source Voltage (V)

DS

°

T = 25 C

J

°

T = 175 C

J

1000

100

D

I , Drain-to-Source Current (A)

10

0.1 1 10 100

VGS

TOP

15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM

4.5V

4.5V

20µs PULSE WIDTH
T = 175 C

J

V , Drain-to-Source Voltage (V)

DS

°

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

3.0

°

2.5

I =

D

169A

100

10

D

I , Drain-to-Source Current (A)

V = 25V

DS

1

4 6 8 10 12

V , Gate-to-Source Voltage (V)

GS

20µs PULSE WIDTH

Fig 3. Typical Transfer Characteristics

2.0

1.5

(Normalized)

1.0

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160 180

T , Junction Temperature ( C)

J

Fig 4. Normalized On-Resistance

V =

GS

°

10V

Vs. Temperature

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IRF1405PbF

100000

)
F

10000

p

(
e
c
n
a

t

i
c
a
p
a

C
,

1000

C

V

= 0V, f = 1 MHZ

GS

C

= C

iss

gs

C

= C

rss

gd

C

= C

oss

ds

Ciss

Coss

+ Cgd, C

+ C

gd

Crss

100

1 10 100

VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

SHORTED

ds

20

I =

101A

16

12

8

4

GS

V , Gate-to-Source Voltage (V)

D

V = 44V

DS

V = 27V

DS

FOR TEST CIRCUIT

0

0 60 120 180 240 300

Q , Total Gate Charge (nC)

G

SEE FIGURE

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

13

1000

10000

OPERATION IN THIS AREA
LIMITED BY RDS(on)

°

T = 175 C

J

100

°

T = 25 C

J

10

SD

I , Reverse Drain Current (A)

V = 0 V

1

0.0 0.5 1.0 1.5 2.0 2.5 3.0

V ,Source-to-Drain Voltage (V)

SD

GS

Fig 7. Typical Source-Drain Diode

)
A

(
t

1000

n
e

r

r
u

C
e

c

r
u
o
S

­o

t

­n

i
a

r
D
,

I

100

10

D

Tc = 25°C
Tj = 175°C
Single Pulse

1

100µsec

1msec

10msec

0 1 10 100 1000

V

, Drain-toSource Voltage (V)

DS

Fig 8. Maximum Safe Operating Area

Forward Voltage

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IRF1405PbF

200

LIMITED BY PACKAGE

160

120

80

D

I , Drain Current (A)

40

0

25 50 75 100 125 150 175

T , Case Temperature ( C)

C

°

Fig 9. Maximum Drain Current Vs.

Case Temperature

1

R

V

DS

V

GS

R

G

D

D.U.T.

10V

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig 10a. Switching Time Test Circuit

V

DS

90%

10%
V

GS

t

d(on)tr

t

d(off)tf

Fig 10b. Switching Time Waveforms

+

V

DD

-

D = 0.50

thJC

0.20

0.1

0.10

0.05

0.02

0.01

0.01

Thermal Response (Z )

0.001

0.00001 0.0001 0.001 0.01 0.1

SINGLE PULSE

(THERMAL RESPONSE)

t , Rectangular Pulse Duration (sec)

1

P

DM

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

1 2

J DM thJC C

t

1

t

2

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF1405PbF

A

15V

DRIVER

+

-

V

R

G

20V

V

DS

t

L

D.U.T

I

AS

0.01

p

Ω

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

I

AS

Fig 12b. Unclamped Inductive Waveforms

Q

G

10 V

Q

GS

Q

GD

DD

1200

TOP

1000

800

600

400

200

AS

E , Single Pulse Avalanche Energy (mJ)

0

25 50 75 100 125 150 175

Starting T , Junction Temperature ( C)

J

BOTTOM

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

4.0

I

D
41A
71A

101A

°

V

G

Charge

Fig 13a. Basic Gate Charge Waveform

Current Regulator

Same Type as D.U.T.

50KΩ

.2µF

12V

V

GS

.3µF

D.U.T.

3mA

I

G

Current Sampling Resistors

+

V

DS

-

I

D

Fig 13b. Gate Charge Test Circuit

3.5

)
V

(
e

c

3.0

a

i

r
a
V

,

)

2.5

h

t

(
S
G

V

2.0

1.5

-75 -50 -25 0 25 50 75 100 125 150 175

ID = 250µA

TJ , Temperature ( °C )

Fig 14. Threshold Voltage Vs. Temperature

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IRF1405PbF

1000

Duty Cycle = Single Pulse

)
A

(

100

t
n
e

r

r
u

C
e

h
c
n
a

l

10

a
v

A

1

1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

0.01

0.05

0.10

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses

Notes on Repetitive Avalanche Curves , Figures 15, 16:

600

TOP Single Pulse

500

)
J

m

(
y

g

r

400

e
n
E

e
h

300

c
n
a

l
a
v

200

A

,
R

A

E

100

0

25 50 75 100 125 150 175

BOTTOM 10% Duty Cycle
ID = 101A

Starting TJ , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy

Vs. Temperature

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T
every part type.

2. Safe operation in Avalanche is allowed as long asT
not exceeded.

. This is validated for

jmax

jmax

3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.

4. P

avalanche pulse.

= Average power dissipation per single

D (ave)

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. I

= Allowable avalanche current.

av

7. ∆T = Allowable rise in junction temperature, not to exceed

T

(assumed as 25°C in Figure 15, 16).

jmax

t

Average time in avalanche.

av =

D = Duty cycle in avalanche = t
Z

(D, tav) = Transient thermal resistance, see figure 11)

thJC

P

= 1/2 ( 1.3·BV·Iav) = DT/ Z

D (ave)

I

2DT/ [1.3·BV·Zth]

av =

E

= P

AS (AR)

·f

av

D (ave)·tav

thJC

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is

IRF1405PbF

Peak Diode Recovery dv/dt Test Circuit

D.U.T*

+



Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance
Current Transformer

-

+



-



-

+



R

G

V

GS

• dv/dt controlled by R

• ISD controlled by Duty Factor "D"

G

• D.U.T. - Device Under Test

+

V

DD

-

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.

Period

D =

P. W .

Period

VGS=10V

[ ] ***

D.U.T. ISDWaveform

Reverse
Recovery
Current

Re-Applied
Voltage

D.U.T. VDSWaveform

Inductor Curent

*** V

= 5.0V for Logic Level and 3V Drive Devices

GS

Fig 17. For N-channel HEXFET

Body Diode Forward

Current

di/dt

Diode Recovery

dv/dt

Body Diode Forward Drop

Ripple ≤ 5%

®

power MOSFETs

V

DD

[ ]

I

[ ]

SD

8 www.irf.com

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

IRF1405PbF

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TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101] market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

TAC Fax: [phone]

Visit us at www.irf.com for sales contact information. 11/2008

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