l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
G
D
V
DSS
R
DS(on
max.
I
D (Silicon Limited)
I
S
D
(Package Limited)
typ.
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
–––430–––
Reverse Recovery Current–––7.7–––A
Forward Turn-On TimeIntrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VGS = 0V, ID = 250µA
Reference to 25°C, I
= 10V, ID = 195A
V
mΩ
GS
= VGS, ID = 250µA
V
DS
= 24V, VGS = 0V
V
DS
V
= 24V, VGS = 0V, TJ = 125°C
DS
VGS = 20V
VGS = -20V
Ω
VDS = 10V, ID = 195A
= 195A
I
D
= 12V
V
DS
nC
VGS = 10V
I
= 195A, VDS =0V, VGS = 10V
D
V
DD
= 195A
I
D
ns
R
= 2.7Ω
G
VGS = 10V
V
GS
g
= 16V
g
= 0V
VDS = 24V
pF
ƒ = 1.0 MHz, See Fig. 5
= 0V, VDS = 0V to 19V i, See Fig. 11
V
GS
= 0V, VDS = 0V to 19V
V
GS
MOSFET symbol
showing the
A
integral reverse
p-n junction diode.
T
= 25°C, IS = 195A, VGS = 0V
J
TJ = 25°CVR = 20V,
ns
= 125°CIF = 195A
T
J
TJ = 25°C
nC
= 125°C
T
J
TJ = 25°C
Conditions
= 5.0mA
D
g
Conditions
h
Conditions
di/dt = 100A/µs
d
D
G
S
g
g
Notes:
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
RG = 25Ω, I
above this value .
I
≤ 195A, di/dt ≤ 450 A/µs, V
SD
, starting TJ = 25°C, L = 0.014mH
Jmax
= 195A, VGS =10V. Part not recommended for use
AS
DD
≤ V
(BR)DSS
, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
C
eff. (TR) is a fixed capacitance that gives the same charging time
oss
as C
C
C
R
while V
oss
eff. (ER) is a fixed capacitance that gives the same energy as
oss
while V
oss
is measured at TJ approximately 90°C
θ
is rising from 0 to 80% V
DS
is rising from 0 to 80% V
DS
DSS
DSS
.
.
2www.irf.com
Page 3
IRF1324PbF
10000
60µs PULSE WIDTH
)
A
(
t
n
e
r
r
u
C
e
c
r
u
o
S
o
t
n
i
a
r
D
,
D
I
1000
100
10
≤
Tj = 25°C
1
4.0V
TOP 15V
BOTTOM4.0V
0.1
0.1110100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
)
A
(
t
100
n
e
r
r
u
C
e
c
r
u
o
S
o
t
n
i
a
r
D
,
D
I
10
1
TJ = 175°C
TJ = 25°C
V
= 15V
DS
≤
60µs PULSE WIDTH
0.1
23456789
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
VGS
10V
8.0V
6.0V
5.5V
5.0V
4.5V
10000
VGS
10V
8.0V
6.0V
5.5V
5.0V
4.5V
)
A
(
t
n
e
r
1000
r
u
C
e
c
r
u
o
S
o
t
-
100
n
i
a
r
D
,
D
I
60µs PULSE WIDTH
≤
Tj = 175°C
TOP 15V
BOTTOM4.0V
4.0V
10
0.1110100
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
2.0
e
c
n
a
t
s
i
s
e
R
n
O
e
c
r
u
o
S
o
t
n
i
a
r
D
,
)
n
o
(
S
D
R
ID = 195A
V
= 10V
GS
1.5
)
d
e
z
i
l
a
m
r
o
N
(
1.0
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance vs. Temperature
100000
)
F
p
(
e
c
n
a
t
i
10000
c
a
p
a
C
,
C
1000
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
+ Cgd, C
gs
gd
+ C
ds
iss
C
rss
C
oss
C
iss
C
oss
C
rss
SHORTED
ds
gd
110100
VDS, Drain-to-Source Voltage (V)
14.0
ID= 195A
12.0
)
V
(
e
g
10.0
a
t
l
o
V
e
8.0
c
r
u
o
S
-
6.0
o
t
e
t
a
4.0
G
,
S
G
V
2.0
VDS= 19V
VDS= 12V
0.0
050100150200
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
www.irf.com3
Page 4
IRF1324PbF
1000
)
A
(
t
n
e
r
r
100
u
C
n
i
a
r
D
e
s
r
e
v
10
e
R
,
D
S
I
1.0
TJ = 175°C
TJ = 25°C
0.00.51.01.5
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
400
350
300
)
A
(
t
250
n
e
r
r
u
C
200
n
i
a
r
150
D
,
D
I
100
50
0
255075100125150175
TC , Case Temperature (°C)
Limited By Package
Fig 9. Maximum Drain Current vs.
V
GS
= 0V
10000
OPERATION IN THIS AREA
)
A
(
t
1000
n
e
r
r
u
C
e
c
r
u
100
o
S
o
t
n
i
a
r
D
,
D
I
Limited by
package
10
Tc = 25°C
Tj = 175°C
Single Pulse
1
110100
LIMITED BY RDS(on)
100µsec
1msec
10msec
DC
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
)
V
(
32
e
g
a
t
l
o
V
n
w
o
d
k
a
e
r
B
e
c
r
u
o
S
o
t
n
i
a
r
D
,
S
S
D
)
R
B
(
V
Id = 5mA
30
28
26
24
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
2.0
1.8
1.6
1.4
)
1.2
J
µ
(
y
1.0
g
r
e
n
0.8
E
0.6
0.4
0.2
0.0
-5051015202530
V
Drain-to-Source Voltage (V)
DS,
Fig 11. Typical C
Stored Energy
OSS
1200
)
J
m
(
y
1000
g
r
e
n
E
e
800
h
c
n
a
l
a
v
600
A
e
s
l
u
P
400
e
l
g
n
i
S
,
200
S
A
E
0
255075100125150175
Starting TJ , Junction Temperature (°C)
TOP 44A
BOTTOM 195A
I
D
83A
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4www.irf.com
Page 5
1
τ
W
/
C
°
)
Z
(
e
s
n
o
p
s
e
R
l
a
m
r
e
h
T
C
J
h
t
0.01
0.1
D = 0.50
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
τ
J
τ
J
τ
1
τ
1
Ci= τi/Ri
R
R
R
R
1
2
R
1
τ
2
τ
3
R
R
2
3
τ
3
τ
2
3
Ri (°C/W) τi (sec)
4
R
4
0.0125 0.000008
τ
C
τ
0.0822 0.000078
4
τ
4
0.2019 0.001110
0.2036 0.007197
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-0061E-0050.00010.0010.010.1
t1 , Rectangular Pulse Duration (sec)
IRF1324PbF
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
)
A
(
100
t
n
e
r
r
u
C
e
h
c
n
a
l
a
v
A
0.05
0.10
10
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-061.0E-051.0E-041.0E-031.0E-021.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
www.irf.com5
Page 6
IRF1324PbF
300
TOP Single Pulse
250
)
J
m
(
y
g
200
r
e
n
E
e
h
150
c
n
a
l
a
v
A
100
,
R
A
E
50
BOTTOM 1.0% Duty Cycle
ID = 195A
0
255075100125150175
Starting TJ , Junction Temperature (°C)
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
2. Safe operation in Avalanche is allowed as long asT
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
. This is validated for every part type.
jmax
is not exceeded.
jmax
= Average power dissipation per single avalanche pulse.
during avalanche).
6. I
= Allowable avalanche current.
av
7. ∆T = Allowable rise in junction temperature, not to exceedT
(assumed as
jmax
25°C in Figure 14, 15).
t
Average time in avalanche.
av =
D = Duty cycle in avalanche = t
(D, tav) = Transient thermal resistance, see Figures 13)
Z
thJC
P
D (ave)
·f
av
= 1/2 ( 1.3·BV·Iav) = DT/ Z
I
2DT/ [1.3·BV·Zth]
av =
E
= P
AS (AR)
D (ave)·tav
thJC
4.5
)
V
4.0
(
e
g
a
t
l
3.5
o
V
d
l
o
3.0
h
s
e
r
h
t
e
t
a
G
,
)
h
t
(
S
G
V
2.5
2.0
1.5
ID = 250µA
ID = 1.0mA
ID = 1.0A
1.0
-75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
6www.irf.com
Page 7
IRF1324PbF
A
Reverse
Recovery
Current
Driver Gate Drive
D.U.T. ISDWaveform
D.U.T. VDSWaveform
Inductor Current
Inductor Curent
* V
GS
D.U.T
+
-
R
G
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
Current Transformer
-
• dv/dt controlled by R
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
G
+
V
DD
Re-Applied
Voltage
+
-
Period
P.W.
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
= 5V for Logic Level Devices
D =
P. W .
Period
VGS=10V
V
DD
I
SD
*
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
15V
V
DS
L
DRIVER
t
p
(BR)DSS
R
G
V
20V
GS
Fig 22a. Unclamped Inductive Test Circuit
V
GS
R
G
10V
V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
D.U.T
I
AS
Ω
0.01
t
p
+
V
DD
-
I
AS
Fig 22b. Unclamped Inductive Waveforms
R
V
DS
D
V
DS
90%
D.U.T.
+
V
DD
-
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 23a. Switching Time Test CircuitFig 23b. Switching Time Waveforms