Datasheet IR3637ASPbF Datasheet (International Rrectifier)

Data Sheet No. 94715

IR3637ASPbF

1% ACCURATE SYNCHRONOUS PWM CONTROLLER

FEATURES

0.8V Reference Voltage
Operates with a single 5V Supply
Internal 600KHz Oscillator
Soft-Start Function
Fixed Frequency Voltage Mode
Short Circuit Protection

APPLICATIONS

Computer Peripheral Voltage Regulator
Memory Power supplies
Graphics Card
Low cost on-board DC to DC

TYPICAL APPLICATION

12V

C3

5V

C2

DESCRIPTION

The IR3637A controller IC is designed to provide a simple
synchronous Buck regulator for on-board DC to DC ap­plications in a small 8-pin SOIC. The output voltage can
be precisely regulated using the internal 0.8V reference
voltage for low voltage applications.
The IR3637A operates at a fixed internal 600KHz switch­ing frequency to reduce the component size.
The device features under-voltage lockout for both input
supplies, an external programmable soft-start function
as well as output under-voltage detection that latches
off the device when an output short is detected.

C1

C4

C5

R1

Vc Vcc

Q1

L1

Q2

SS/SD

HDrv

D1

LDrv

IR3637A

Comp

Fb

Gnd

Figure 1 - Typical application of IR3637A.

R3

R2

ORDERING INFORMATION

PKG PACKAGE PIN PARTS PARTS T & R
DESIG DESCRIPTION COUNT PER TUBE PER REEL Oriantation

S IR3637ASPbF 8 95 -----­ S IR3637ASTRPbF 8 ------- 2500

Fig A

Vout

C6

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1

IR3637ASPbF

ABSOLUTE MAXIMUM RATINGS

Vcc Supply Voltage ................................................ 16V

Vc Supply Voltage .................................................. 25V

Storage Temperature Range ..................................... -65°C To 150°C

Operating Junction Temperature Range ..................... 0°C To 125°C

ESD Classification ................................................. HBM Class 2 (2KV) JEDEC Standard

Moisture Sensitivity Level ........................................ JEDEC Level 1 @ 260°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.

PACKAGE INFORMATION

Recommended Operating Conditions

1

Fb

2

Vcc

3

LDrv

4

Gnd HDrv

θJA=154°C/W
θJC=41.2°C/W

8

7

6

5

SS/SD

Comp

Vc

Parameter Min Max Units

Vcc 4.5 5.5 V
Vc 8 14 V

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc=5V, Vc=12V and 0°C<Tj<125°C.

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Feedback Voltage

Fb Voltage

Fb Voltage Line Regulation

UVLO

UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - Vc
UVLO Hysteresis - Vc
UVLO Threshold - Fb

Supply Current

Vcc Dynamic Supply Current
Vc Dynamic Supply Current
Vcc Static Supply Current
Vc Static Supply Current

Soft-Start Section

Charge Current
Shutdown Threshold

VFB

LREG

UVLO Vcc

UVLO Vc

UVLO Fb

Dyn Icc

Dyn Ic

ICCQ

ICQ

SSIB

SD

25°C<Tj<75°C
0°C<Tj<125°C

4.5<Vcc<5.5

Supply Ramping Up

Supply Ramping Up

Fb Ramping Down

Freq=600KHz, CL=1500pF
Freq=600KHz, CL=1500pF
SS=0V
SS=0V

SS=0V

0.792

0.789

4.0

3.1

0.3

4
6
1

0.5

-15

0.800

0.800

4.2

0.25

3.3

0.2

0.4

7

15

3.3
1

-25

0.808

0.811

0.1

4.4

3.5

0.5

16
20

6

4.7

-35

0.4

V
V

%

V
V
V
V
V

mA
mA
mA
mA

µA

V

2

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IR3637ASPbF

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Error Amp

Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
Transconductance

Oscillator

Frequency

SS=3V, Fb=0.6V

IFB1

SS=0V, Fb=0.6V

IFB2

gm

Freq

450

540

-0.1

-64

600

600

800

660

µA
µA

µmho

KHz

Ramp-Amplitude Voltage

V

RAMP

Output Drivers

Rise Time, Hdrv, Ldrv
Fall Time,Hdrv, Ldrv
Dead Band Time
Max Duty Cycle
Min Duty Cycle

CL=1500pF, Vcc=12V,2V to 9V

Tr

C

Tf

TDB

TON

TOFF

L=1500pF, Vcc=12V, 9V to 2V

Vcc=12V, 2V to 2V
Fb=0.6V, Freq=600KHz
Fb=1V

PIN DESCRIPTIONS

PIN# PIN SYMBOL PIN DESCRIPTION

1

2

3

4

Fb

Vcc

LDrv

Gnd

This pin is connected directly to the output of the switching regulator via resistor divider to
set the output voltage and provide feedback to the error amplifier.

This pin provides biasing for the internal blocks of the IC as well as powers the low side
driver. A minimum of 0.1µF, high frequency capacitor must be connected from this pin to
ground to provide peak drive current capability.

Output driver for the synchronous power MOSFET.

IC's ground pin, this pin must be connected directly to the ground plane. A high frequency
capacitor (0.1 to 1µF) must be connected from Vcc and Vc pins to this pin for noise free
operation.

40
76

1.25

30
30

150

60
60

200

V

ns
ns
ns

%

0

0

%

5

6

7

8

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HDrv

Vc

Comp

SS / SD

Output driver for the high side power MOSFET. The negative voltage at this pin may cause
instability for the gate drive circuit. To prevent this, a low forward voltage drop diode (e.g.
BAT54 or 1N4148) is required between this pin and ground.

This pin is connected to a voltage that must be at least 4V higher than the bus voltage
(assuming 5V threshold MOSFET) and powers the high side output driver. A minimum of

0.1µF, high frequency capacitor must be connected from this pin to ground to provide
peak drive current capability.

Compensation pin of the error amplifier. An external resistor and capacitor network is
typically connected from this pin to ground to provide loop compensation.

This pin provides user programmable soft-start function. Connect an extrnal capacitor
from this pin to ground to set the start up time of the output. The converter can be shut­down by pulling this pin below 0.4V. During shutdown both drivers turn off.

3

IR3637ASPbF

BLOCK DIAGRAM

SS/SD

POR

Fb

Comp

8

0.8V

1

7

3V

25uA

25K

25K

64uA Max

Error Amp

Vcc

4.2V

Vc

3.3V

0.4V

Ct

Oscillator

Error Comp

FbLo Comp

POR

Bias

Generator

S

R

Reset Dom

3V

0.8V

POR

6

Vc

5

HDrv

Q

2

Vcc

3

LDrv

Gnd

4

Figure 2 - Simplified block diagram of the IR3637A.

THEORY OF OPERATION

Introduction

The IR3637A is a fixed frequency, voltage mode syn­chronous controller and consists of a precision refer­ence voltage, an error amplifier, an internal oscillator, a
PWM comparator, 0.5A peak gate driver, soft-start and
shutdown circuits (see Block Diagram).

The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier; this is
the amplified error signal from the sensed output voltage
and the reference voltage.

This voltage is compared to a fixed frequency linear
sawtooth ramp and generates fixed frequency pulses of
variable duty-cycle, which drives the two N-channel ex­ternal MOSFETs.The timing of the IC is provided through
an internal oscillator circuit which uses on-chip capaci­tor to set the oscillation frequency to 600 KHz.

Short-Circuit Protection

The output is protected against the short-circuit. The
IR3637A protects the circuit for shorted output by sens­ing the output voltage (through the external resistor di­vider). The IR3637A shuts down the PWM signals, when
the output voltage drops below 0.4V.

Under-Voltage Lockout

The under-voltage lockout circuit assures that the
MOSFET driver outputs remain in the off state whenever
the supply voltage drops below set parameters. Lockout
occurs if Vc or Vcc fall below 3.3V and 4.2V respec­tively. Normal operation resumes once Vc and Vcc rise
above the set values.

Shutdown

The converter can be shutdown by pulling the soft-start
pin below 0.4V. This can be easily done by using an
external small signal transistor. During shutdown both
drivers turn off.

4

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THEORY OF OPERATION

IR3637ASPbF

Soft-Start

The IR3637A has a programmable soft-start to control
the output voltage rise and limit the current surge at the
start-up. To ensure correct start-up, the soft-start se­quence initiates when the Vc and Vcc rise above their
threshold (3.3V and 4.2V respectively) and generates
the Power On Reset (POR) signal. Soft-start function
operates by sourcing an internal current to charge an
external capacitor to about 3V. Initially, the soft-start func­tion clamps the E/A’s output of the PWM converter and
disables the short circuit protection. During the power
up, the output starts at zero and voltage at Fb is below

0.4V. The feedback UVLO is disabled during this time
by injecting a current (64µA) into the Fb. This generates
a voltage about 1.6V (64µA×25K) across the negative
input of E/A and positive input of the feedback UVLO
comparator (see Figure 3).
The magnitude of this current is inversely proportional to
the voltage at soft-start pin.

The 20µA current source starts to charge up the exter­nal capacitor. In the mean time, the soft-start voltage
ramps up, the current flowing into Fb pin starts to de­crease linearly and so does the voltage at the positive
pin of feedback UVLO comparator and the voltage nega­tive input of E/A.

3V

64uA
Max

Error Amp

Feeback
UVLO Comp

HDrv

LDrv

POR

SS/SD

Comp

0.8V

Fb

25uA

POR

64uA

25K

25K

0.4V

×

25K=1.6V

When SS=0

Figure 3 - Soft-start circuit for IR3637A.

The output start-up time is the time period when soft­start capacitor voltage increases from 1V to 2V. The start­up time will be dependent on the size of the external
soft-start capacitor. The start-up time can be estimated
by:

25µA×TSTART/CSS = 2V-1V

When the soft-start capacitor is around 1V, the current
flowing into the Fb pin is approximately 32µA. The volt­age at the positive input of the E/A is approximately:

32µA×25K = 0.8V

The E/A will start to operate and the output voltage starts
to increase. As the soft-start capacitor voltage contin­ues to go up, the current flowing into the Fb pin will keep
decreasing. Because the voltage at pin of E/A is regu­lated to reference voltage 0.8V, the voltage at the Fb is:

VFB = 0.8-25K×(Injected Current)

The feedback voltage increases linearly as the injecting
current goes down. The injecting current drops to zero
when soft-start voltage is around 2V and the output volt­age goes into steady state.

As shown in Figure 4, the positive pin of feedback UVLO
comparator is always higher than 0.4V, therefore, feed­back UVLO is not functional during soft-start.

For a given start up time, the soft-start capacitor can be
estimated as:

CSS ≅ 25µA×TSTART/1V

Output of UVLO

Current flowing

Voltage at negative input

of Error Amp and Feedback

UVLO comparator

Voltage at Fb pin

POR

Soft-Start

Voltage

into Fb pin

0V

64uA

≅

1.6V

0V

0uA

0.8V

0.8V

3V

≅

2V

≅

1V

Figure 4 - Theoretical operational waveforms

during soft-start.

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IR3637ASPbF

APPLICATION INFORMATION

Design Example:

The following example is a typical application for IR3637A.
Appliaction circuit is shown in page 12.

VIN = Vcc = 5V
Vc=12V
VOUT = 1.8V
IOUT = 6A
∆VOUT = 50mV
FS = 600KHz

Output Voltage Programming

Output voltage is programmed by reference voltage and
external voltage divider. The Fb pin is the inverting input
of the error amplifier, which is internally referenced to

0.8V. The divider is ratioed to provide 0.8V at the Fb pin
when the output is at its desired value. The output volt­age is defined by using the following equation:

R6

VOUT = VREF ×

When an external resistor divider is connected to the
output as shown in Figure 5.

1 +

( )

IR3637A

Figure 5 - Typical application of the IR3637A for

programming the output voltage.

---(1)

R5

Fb

V

OUT

6

R

R

5

Css ≅ 25×tSTART (µF) ---(2)

Where tSTART is the desired start-up time (ms)

For a start-up time of 4ms, the soft-start capacitor will
be 0.1µF. Choose a ceramic capacitor at 0.1µF.

Boost Supply for Single 5V appliaction

To drive the high side switch, it is necessary to supply a
gate voltage at least 4V grater than the bus voltage. This
is achieved by using a charge pump configuration as
shown in Figure 6. This method is simple and inexpen­sive. The operation of the circuit is as follows: when the
lower MOSFET is turned on, the capacitor (C1) is pulled
down to ground and charges, up to VBUS value, through
the diode (D1). The bus voltage will be added to this
voltage when upper MOSFET turns on in next cycle,
and providing supply voltage (Vc) through diode (D2). Vc
is approximately:

Vc ≅ 2VBUS - (VD1 + VD2)

Capacitors in the range of 0.1µF and 1µF are generally
adequate for most applications. The diode must be a
fast recovery device to minimize the amount of charge
fed back from the charge pump capacitor into V
diodes need to be able to block the full power rail volt­age, which is seen when the high side MOSFET is
switched on. For low voltage application, schottky di­odes can be used to minimize forward drop across the
diodes at start up.

BUS

V

C3

D1

D2

BUS. The

Equation (1) can be rewritten as:

VOUT

R6 = R5 ×

Choose R5 = 1KΩ
This will result to R6 = 1.25KΩ

If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage set point can be
more accurate by using precision resistor.

Soft-Start Programming

The soft-start timing can be programmed by selecting
the soft-start capacitance value. The start-up time of the
converter can be calculated by using:

- 1

( )

VREF

6

BUS

C1

V

Q1

L

Q2

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Vc

C2

IR3637A

Figure 6 - Charge pump circuit.

Input Capacitor Selection

The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
ripple current generated during the on time of upper
MOSFET should be provided by input capacitor. The RMS
value of this ripple is expressed by:

HDrv

IR3637ASPbF

RMS = IOUT D×(1-D) ---(3)

I

Where:
D is the Duty Cycle, D=VOUT/VIN.
IRMS is the RMS value of the input capacitor current.
IOUT is the output current for each channel.

For IOUT=6A and D=0.36, the IRMS=2.8A

For higher efficiency, low ESR capacitor is recommended.
Two capacitors of Sanyo's TPB series PosCap with
150µF, 6.3V, 40mΩ ESR and 1.4A ripple current will
meet the ripple current requirement.

Inductor Selection

The inductor is selected based on output power, operat­ing frequency and efficiency requirements. Low inductor
value causes large ripple current, resulting in the smaller
size, faster response to a load transient but poor effi­ciency and high output noise. Generally, the selection of
inductor value can be reduced to desired maximum ripple

current in the inductor (∆i). The optimum point is usually

found between 20% and 50% ripple of the output cur­rent.

For the buck converter, the inductor value for desired
operating ripple current can be determined using the fol­lowing relation:

VIN - VOUT = L× ; ∆t = D× ; D =

L = (VIN - VOUT)× ---(5)

∆i
∆t

VOUT

VIN×∆i×fS

1
fS

VOUT

VIN

Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage

∆i = Inductor Ripple Current

fS = Switching Frequency

∆t = Turn On Time

D = Duty Cycle

The ESR of the output capacitor is calculated by the
following relationship:

ESR ≤ ---(4)

∆VO

∆IO

Where:

∆VO = Output Voltage Ripple
∆IO = Inductor Ripple Current
∆VO=50mV and ∆IO=1.92A

Results to ESR=26.8mΩ

The Sanyo TPB series, PosCap capacitor is a good
choice. The 6TPB150M 150µF, 6.3V has an ESR 40mΩ.
Selecting two of these capacitors in parallel, results to

an ESR of ≅ 20mΩ which achieves our low ESR goal.

Power MOSFET Selection

The IR3637A uses two N-Channel MOSFETs. The se­lections criteria to meet power transfer requirements is
based on maximum drain-source voltage (V

DSS), gate-

source drive voltage (VGS), maximum output current, On­resistance RDS(ON) and thermal management.

The MOSFET must have a maximum operating voltage
(VDSS) exceeding the maximum input voltage (VIN).

The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and cau­tion should be taken with devices at very low VGS to pre­vent undesired turn-on of the complementary MOSFET,
which results a shoot-through current.

The total power dissipation for MOSFETs includes con­duction and switching losses. For the Buck converter
the average inductor current is equal to the DC load cur­rent. The conduction loss is defined as:

PCOND (Upper Switch) = ILOAD × RDS(ON) × D × ϑ

PCOND (Lower Switch) = ILOAD × RDS(ON) × (1 - D) × ϑ

2

2

If ∆i = 32%(I

O), then the output inductor will be:

L = 1.0µH
The Coilcraft DO3316P series provides a range of induc­tors in different values, low profile suitable for large cur­rents, 1.0µH, 9A(Isat) is a good choice for this applica­tion.

Output Capacitor Selection

The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy sta­bility requirements.

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ϑ = RDS(ON) Temperature Dependency

The RDS(ON) temperature dependency should be consid­ered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.

7

IR3637ASPbF

For this design, IRF8910 is a good choice. The device
provides two N-MOSFETs in a compact SOIC 8-Pin pack­age.

The IRF8910 has the following data:

VDSS = 20V
ID = 10A
RDS(ON) =18.3Ω @ VGS=4.5V (Lower FET)
RDS(ON) =13.4Ω @ VGS=10V (Upper FET)

The total conduction losses will be:

PCON(TOTAL)=PCON(Upper Switch)+PCON(Lower Switch)

ϑ = 1.4 according to the IRF8910 data sheet for
150C junction temperature

PCON(TOTAL) =0.83W

The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such
as turn-on / turnoff delays and rise and fall times. The
control MOSFET contributes to the majority of the switch­ing losses in synchronous Buck converter. The synchro­nous MOSFET turns on under zero voltage conditions,
therefore, the turn on losses for synchronous MOSFET
can be neglected. With a linear approximation, the total
switching loss can be expressed as:

VDS(OFF)

PSW = ILOAD ---(6)

2

tr + tf

T

××

Where:
V

DS(OFF) = Drain to Source Voltage at off time

tr = Rise Time
tf = Fall Time

T = Switching Period
ILOAD = Load Current

The switching time waveform is shown in figure 7.

DS

V

90%

These values are taken under a certain condition test.
For more detail please refer to the IRF8915 data sheet.

By using equation (6), we can calculate the switching
losses.

SW = 0.127mW

P

Feedback Compensation

The IR3637A is a voltage mode controller; the control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensa­tion circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 45).

The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 (see Figure 8). The Reso­nant frequency of the LC filter expressed as follows:

1

FLC = ---(7)

2π× LO×CO

Figure 8 shows gain and phase of the LC filter. Since we
already have 180 phase shift just from the output filter,
the system risks being unstable.

0dB

Gain

-40dB/decade

LC

F

Frequency

-180

Phase



0



LC

F

Frequency

Figure 8 - Gain and phase of LC filter.

The IIR3637A’s error amplifier is a differential-input
transconductance amplifier. The output is available for
DC gain control or AC phase compensation.

10%

GS

V

d

t

(ON)

r

t

Figure 7 - Switching time waveforms.

From IRF8910 data sheet:

8

d

t

(OFF)

tr = 10ns
tf = 4.1ns

The E/A can be compensated with or without the use of
local feedback. When operated without local feedback
the transconductance properties of the E/A become evi­dent and can be used to cancel one of the output filter

f

t

poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 9.

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IR3637ASPbF

Note that this method requires that the output capacitor
should have enough ESR to satisfy stability requirements.
In general the output capacitor’s ESR generates a zero
typically at 5KHz to 50KHz which is essential for an
acceptable phase margin.

The ESR zero of the output capacitor expressed as fol­lows:

FESR = ---(8)

2π × ESR × Co

V

OUT

1

R

6

Fb

Comp

R

E/A

5

V

REF

Gain(d B)

Ve

C

9

C

R

4

POLE

H(s) dB

Frequency

F

Z

Figure 9 - Compensation network without local

feedback and its asymptotic gain plot.

The transfer function (Ve / V

H(s) = gm × × ---(9)

( )

R6 + R5

R5

OUT) is given by:

1 + sR4C9

sC9

The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:

|H(s)| = gm× × R4 ---(10)

FZ = ---(11)

2π×R4×C9

R5

R6×R5

1

The gain is determined by the voltage divider and E/A's
transconductance gain.

Where:

IN = Maximum Input Voltage

V
VOSC = Oscillator Ramp Voltage
Fo = Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
gm = Error Amplifier Transconductance

For:
VIN = 5.5V
VOSC = 1.25V
Fo = 60KHz
FESR = 26.5KHz
FLC = 9.20KHz
R5 = 1K
R6 = 1.25K
gm = 600µmho

This results to R

4=16.06KΩ. Choose R4=16KΩ

To cancel one of the LC filter poles, place the zero be­fore the LC filter resonant frequency pole:

FZ ≅ 75%FLC
FZ ≅ 0.75 × ---(13)

1

2π LO × CO
For:
Lo = 1.0µH
Co = 300µF
FZ = 6.9KHz
R4 = 16KΩ

Using equations (11) and (13) to calculate C9, we get:

C9 = 1.44nF
Choose C9 = 1.5nF

One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to supress the switching noise. The additional pole
is given by:

1

FP =

2π × R4 ×

C9 × CPOLE

C9 + CPOLE

First select the desired zero-crossover frequency (Fo):

Fo > FESR and FO ≤ (1/5 ~ 1/10)× fS

Use the following equation to calculate R4:

VOSC

R4 = ---(12)

VIN

Fo×FESR

2

FLC

×××

R5 + R6

R5

1

gm

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The pole sets to one half of switching frequency which
results in the capacitor CPOLE:

CPOLE =

for FP <<

1

π×R4×fS -

fS
2

1

C9

≅

π×R4×fS

1

9

IR3637ASPbF

For a general solution for unconditionally stability for any
type of output capacitors, in a wide range of ESR values
we should implement local feedback with a compensa­tion network. The typically used compensation network
for voltage-mode controller is shown in Figure 10.

V

Z

IN

Gain(dB)

OUT

C

10

R

8

R

6

Fb

R

5

V

REF

R

7

E/A

C

12

C

11

Z

f

Ve

Comp

H(s) dB

F

F

1

Z

2

Z

F

2

P

Frequency

F

3

P

Figure 10 - Compensation network with local

feedback and its asymptotic gain plot.

In such configuration, the transfer function is given by:

Ve

VOUT

1 - gmZf

=

1 + gmZIN

The error amplifier gain is independent of the transcon­ductance under the following condition:

gmZf >> 1 and gmZIN >>1 ---(14)

By replacing Z
former function can be expressed as:

H(s)= ×

sR6(C12+C11)

As known, transconductance amplifier has high imped­ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli­fier will not be able to swing its output voltage over the
necessary range.

The compensation network has three poles and two ze­ros and they are expressed as follows:

IN and Zf according to Figure 7, the trans-

1

(1+sR7C11)×[1+sC10(R6+R8)]

C12×C11

1+sR7

×(1+sR8C10)

[ ( )]

C12+C11

FP1 = 0

FP2 =

FP3 = ≅

FZ1 =

FZ2 = ≅

1

8×C10

2π×R

1

12×C11

2π×R7×

C

( )

C12+C11

1

2π×R

7×C11

1

2π×C10×(R6 + R8)

1

2π×R7×C12

1

2π×C10×R6

Cross Over Frequency:

FO = R7×C10× × ---(15)

VIN

VOSC12π×Lo×Co

Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors

The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (14) regarding transconduc­tance error amplifier.

1) Select the crossover frequency:
Fo < F

ESR and Fo ≤ (1/10 ~ 1/6)× fS

2) Select R7, so that R7 >>

2

gm

3) Place first zero before LC’s resonant frequency pole.

FZ1 ≅ 75% FLC

C11 =

1

2π × FZ1 × R7

4) Place third pole at the half of the switching frequency.

fS

FP3 =

2

C12 =

2π × R7 × FP3

1

C12 > 50pF
If not, change R7 selection.

5) Place R7 in (15) and calculate C10:

2π × Lo × Fo × Co

C10 ≤ ×

R7

VOSC

VIN

10

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IR3637ASPbF

6) Place second pole at the ESR zero.
FP2 = FESR

R8 =

2π × C10 × FP2

Check if R8 >

If R8 is too small, increase R7 and start from step 2.

7) Place second zero around the resonant frequency.
FZ2 = FLC

R6 = - R8

2π × C10 × FZ2

8) Use equation (1) to calculate R5.

R5 = × R6

VOUT - VREF

These design rules will give a crossover frequency ap­proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran­sient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to ­12dB). The phase margin should be greater than 45 for
overall stability.

1

1

gm

1

VREF

Layout Consideration

The layout is very important when designing high fre­quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start to place the power components, make all the con­nection in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET, to reduce
the ESR replace the single input capacitor with two par­allel units. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control cir­cuit ground (analog ground), to which all signals are ref­erenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.

Based on the frequency of the zero generated by ESR
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.

Compensator

Type

Type II (PI)

Type III (PID)
Method A
Type III (PID)
Method B

Table - The compensation type and location of zero

Detail information is dicussed in application Note AN­1043 which can be downloaded from the IR Web-Site.

All design should be tested for stability to verify the cal­culated values.

Location of Zero

Crossover Frequency

(FO)

FLC < FESR < FO < fS/2

FLC < FO < FESR < fS/2

FLC < FO < fS/2 < FESR

crossover frequency.

Typical

Output

Capacitor

Electrolytic,

Tantalum

Tantalum,

Ceramic
Ceramic

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11

IR3637ASPbF

TYPICAL APPLICATION

Two Supplies Application: Vc=12V, Vin=Vcc=5V to 1.8V @ 6A

IN

V
5V

Gnd

C1
150uF

C2
150uF

12V

47pF

C11

C3

1uF

C6

0.1uF

C9

1.5nF

16K

R4

Vcc Vc

SS/SD

U1

IR3637A

Comp

Gnd

Figure 11 - Typical Application for IR3637A.

HDrv

LDrv

Fb

R5
1K

C4
1uF

D1

R6

1.24K

C5
1uF

Q1
IRF8910

L1

1.0uH

DO3316P-102

C7
150uF

C8
150uF

C10
1uF

OUT

V

1.8V
@ 6A

Gnd

12

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TYPICAL APPLICATION

Single 5V Application

D1

IR3637ASPbF

5V

C8

C9

R4

C3

Vcc Vc

SS/SD

IR3637A

Comp

U1

Gnd

HDrv

LDrv

Fb

C4

C5

C1

Q1

D2

Q2

R6

R5

Figure 12 - Typical application for single 5V

L1

Vout

C7

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13

IR3637ASPbF

TYPICAL APPLICATION

Two Supplies Application, Vcc=Vc=12V, Vin=5V

12V

C8

C9

R4

C3

Vcc Vc

SS/SD

IR3637A

Comp

U1

Gnd

HDrv

LDrv

Fb

C4

D2

R5

Q1

Q2

5V

C1

L1

Vout

C7

R6

14

Figure 13 - Typical application using 12V for biasing both Vcc and Vc and 5V for Bus Voltage

For proper start up the 5V rail needs to start before 12V

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TYPICAL OPERATING CHARACTERISTICS

IR3637ASPbF

mV

800.00

799.75

799.50

799.25

799.00

798.75

798.50

798.25

798.00

797.75

797.50

797.25

797.00

mmhos

0.620

0.600

0.580

0.560

0.540

0.520

0.500

Feedback Voltage

0

-40

-30

102030405060708090

-20

-10

Temp, C

100

110

120

E/A Transconductance

0

-40

-30

102030405060708090

-20

-10

Temp, C

100

110

120

-40

-30

-20

-10

4.800

4.600

4.400

4.200

4.000

mA

3.800

3.600

3.400

3.200

3.000

-40

Soft Start Charge Current

0

102030405060708090

Temp, C

Static Vcc Current

0

-30

102030405060708090

-20

-10

Temp, C

-15.00

-16.00

-17.00

-18.00

-19.00

-20.00

-21.00

-22.00

uA

-23.00

-24.00

-25.00

-26.00

-27.00

-28.00

-29.00

-30.00

100

110

120

100

110

120

Static Vc Current

4.500

4.000

3.500

mA

3.000

2.500

2.000

-40

0

-30

102030405060708090

-20

-10

Temp, C

100

110

120

8.250

8.000

7.750

mA

7.500

7.250

7.000

-40

Dynamic Vcc Current

10

-15

35

Temp, C

60

85

110

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15

IR3637ASPbF

TYPICAL PERFORMANCE CURVES

Test Conditions:
Vcc=Vin=5V, Vc=12V, Vout=1.8V, Iout=0-7A, Ta=Room Temp, No Air Flow. Unless otherwise specified.

Figure 14 - Start up waveforms

Ch1: Vin=Vcc, Ch2:Vc, Ch3:Vss, Ch4: Vout

Figure 16 - Gates waveforms

Ch1:Hdrv, Ch2:Ldrv, Ch4:Inductor Current

ILoad=5A

Figure 15 - Start up waveforms

Ch1:Vin=Vcc, Ch3:Vss, Ch4:Vout

Figure 17 - Gates waveforms

Ch1:Hdrv, Ch2:Ldrv, Ch3:Inductor Point

ILoad=5A

16

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IR3637ASPbF

TYPICAL OPERATING WAVEFORMS

Test Conditions:
Vcc=Vin=5V, Vc=12V, Vout=1.8V, Iout=0-7A, Ta=Room Temp, No Air Flow. Unless otherwise specified.

Figure 18 - Shutdown by shorting the SS pin

Ch1:Hdrv, Ch2:Ldrv, Ch3:SS

ILoad=5A

Figure 20 - Load Transient (0-5A)
Ch1:Vout, Ch4:Step Load Current

Figure 19 - Output Voltage Ripple

Ch1:Vout, Ch4:Inductor Current

ILoad=5A

Figure 21 - Load Transient (5-0A)

Ch1:Vout, Ch4:Step Load Current

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17

IR3637ASPbF

A

B C

(S) SOIC Package

8-Pin Surface Mount, Narrow Body

H

E

PIN NO. 1

DETAIL-A

L

D

0.38±0.015 x 45

T

F

G

8-PIN

SYMBOL

A
B
C
D
E
F
G
H

I

J
K
L
T

K

MIN

4.80

1.27 BSC

0.53 REF

0.36

3.81

1.52

0.10
7 BSC

0.19

5.80

0

0.41

1.37



J

MAX

4.98

0.46

3.99

1.72

0.25

0.25

6.20
8

1.27

1.57

DETAIL-A

I

18

NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.

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PACKAGE SHIPMENT METHOD

IR3637ASPbF

PKG

DESIG

S

PACKAGE

DESCRIPTION

SOIC, Narrow Body

1 11 1 11

PIN

COUNT

8

PARTS

PER TUBE

95

PARTS

PER REEL

2500

Feed Direction

Figure A

T & R

Orientation

Fig A

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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

TAC Fax: [phone]

Visit us at www.irf.com for sales contact information

This product has been designed and qualified for the Consumer market.

Data and specifications subject to change without notice. 9/22/2005

19