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Data Sheet No. PD-6.042D
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IR2128
CURRENT SENSING SINGLE CHANNEL DRIVER
Features
n Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
n Gate drive supply range from 10 to 20V
n Undervoltage lockout
n 5V Schmitt-triggered input logic
FAULT
n
n Output out of phase with input
lead indicates shutdown has occured
Description
The IR2128 is a high voltage, high speed power
MOSFET and IGBT driver. Proprietar y HVIC and
latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL outputs.
The protection circuity detects over-current in the
driven power transistor and terminates the gate
FAULT
drive voltage. An open drain
vided to indicate that an over-current shutdown has
occurred. The output driver features a high pulse
current buffer stage designed for minimum crossconduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the
high side or low side configuration which operates
up to 600 volts.
signal is pro-
Product Summary
V
OFFSET
IO+/- 200 mA / 420 mA
V
OUT
V
CSth
t
(typ.) 150 & 100 ns
on/off
Packages
600V max.
10 - 20V
250 mV
Typical Connection
V
CC
IN
FAULT
V
CC
IN
FAULT
COM
V
B
HO
CS
V
S
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-129
Page 2
IR2128
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Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Ther mal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Parameter Value
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
IN
V
FLT
V
CS
dVs/dt Allowable Offset Supply Voltage Transient — 50 V/ns
P
D
R
θJA
T
J
T
S
T
L
High Side Floating Supply Voltage -0.3 625
High Side Floating Offset Voltage VB - 25 VB + 0.3
High Side Floating Output Voltage VS - 0.3 V
B
+ 0.3
Logic Supply Voltage -0.3 25 V
Logic Input Voltage -0.3 V
Output Voltage -0.3 V
FAULT
Current Sense Voltage VS - 0.3 V
Package Power Dissipation @ TA ≤ +25°C (8 Lead DIP) — 1.0
(8 Lead SOIC) — 0.625
Thermal Resistance, Junction to Ambient (8 Lead DIP) — 125
(8 Lead SOIC) — 200
CC
CC
B
+ 0.3
+ 0.3
+ 0.3
W
°C/W
Junction Temperature — 150
Storage Temperature -55 150 °C
Lead Temperature (Soldering, 10 seconds) — 300
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Parameter Value
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
IN
V
FLT
V
CS
T
A
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS.
B-130 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
High Side Floating Supply Voltage VS + 10 VS + 20
High Side Floating Offset Voltage Note 1 600
High Side Floating Output Voltage V
S
Logic Supply Voltage 11.8 20 V
Logic Input Voltage 0 V
Output Voltage 0 V
FAULT
Current Sense Signal Voltage V
S
V
Ambient Temperature -40 125 °C
V
B
CC
CC
+ 5
S
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IR2128
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Dynamic Electrical Characteristics
V
(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics
BIAS
are measured using the test circuit shown in Figure 3.
Parameter Value
Symbol Definition Min. Typ. Max. Units Test Conditions
t
on
t
off
t
t
t
bl
t
cs
t
flt
Static Electrical Characteristics
V
(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
BIAS
COM. The V
Symbol Definition Min. Typ. Max. Units Test Conditions
V
V
V
CSTH+
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
I
CS+
I
CS-
V
BSUV+
V
BSUV-
I
O+
I
O-
Tur n-On Propagation Delay — 1 50 200 V
Tur n-Off Propagation Delay — 1 00 150 V
Tur n-On Rise Time — 80 1 20 C
r
Tur n-Off Fall Time — 40 60 ns C
f
Start-Up Blanking Time 500 750 900
CS Shutdown Propagation Delay — 240 360
CS to
FAULT Pull-Up Propagation Delay — 3 40 510
and IO parameters are referenced to VS.
O
Parameter Value
Logic “0” Input Voltage (OUT = LO) 2.7 — — VCC = 10V to 20V
IH
Logic “1” Input Voltage (OUT = HI) — — 0.8 VCC = 10V to 20V
IL
CS Input Positive Going Threshold 180 250 320 VCC = 10V to 20V
High Level Output Voltage, V
- VO — — 100 mV IO = 0A
BIAS
Low Level Output Voltage , VO — — 100 IO = 0A
Offset Supply Leakage Current — — 50 VB = VS = 600V
Quiescent VBS Supply Current — 150 300 VIN = 0V or 5V
Quiescent VCC Supply Current — 60 120 VIN = 0V or 5V
Logic “1” Input Bias Current — 7.0 15 µA V
Logic “0” Input Bias Current — — 1.0 VIN = 5V
“High” CS Bias Current — — 1.0 VCS = 3V
“High” CS Bias Current — — 1.0 VCS = 0V
VBS Supply Undervoltage Positiv e Going 8.8 10.3 11.8
Threshold
VBS Supply Undervoltage Negative Going 7.5 9.0 10.6
Threshold
Output High Short Circuit Pulsed Current 200 250 — VO = 0V, V
Output Low Short Circuit Pulsed Current 420 500 — VO = 15V, V
V
V
mA
= 0V
S
= 600V
S
= 1000 pF
L
= 1000 pF
L
= 0V
IN
IN
PW ≤ 10 µs
IN
PW ≤ 10 µs
= 0V
= 5V
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-131
Page 4
IR2128
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Functional Block Diagram
V
CC
5V
UP
SHIFTERS
IN
FAULT -
QR
S
COM
PULSE
GEN
PULSE
FILTER
HV
LEVEL
SHIFT
DETECT
PULSE
FILTER
DOWN
SHIFTER
UV
V
R
Q
R
S
B
PULSE
GEN
QR
S
Lead Definitions
Lead
Symbol Description
V
CC
IN
FAULT
COM Logic ground
V
B
HO
V
S
CS
Logic and gate drive supply
Logic input for gate driver output (HO), out of phase with HO
Indicates over-current shutdown has occurred, negative logic
High side floating supply
High side gate drive output
High side floating supply return
Current sense input to current sense comparator
DELAY
+
BUFFER
V
HO
V
CS
B
S
Lead Assignments
8 Lead DIP SO-8
B-132 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
IR2128 IR2128S
Page 5
Device Information
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Process & Design Rule HVDCMOS 4.0 µm
Transistor Count 206
Die Size 77 X 85 X 26 (mil)
Die Outline
Thickness of Gate Oxide 800Å
Connections Material Poly Silicon
First Width 4 µm
Layer Spacing 6 µm
Thickness 5000Å
Material Al - Si (Si: 1.0% ±0.1%)
Second Width 6 µm
Layer Spacing 7 µm
Thickness 20,000Å
Contact Hole Dimension 8 µm X 8 µm
Insulation Layer Material PSG (SiO2)
Thickness 1.5 µm
Passivation Material PSG (SiO2)
Thickness 1.5 µm
Method of Saw Full Cut
Method of Die Bond Ablebond 84 - 1
Wire Bond Method Thermo Sonic
Material Au (1.0 mil / 1.3 mil)
Leadframe Material Cu
Die Area Ag
Lead Plating Pb : Sn (37 : 63)
Pa ckage Types 8 Lead PDIP / SO-8
Materials EME6300 / MP150 / MP190
Remarks:
IR2128
CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-133
Page 6
IR2128
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IN
CS
FAULT
HO
IN
HO
t
t
r
on
90% 90%
10% 10%
50%50%
t
t
f
off
Figure 2. Switching Time Waveform DefinitionFigure 1. Input/Output Timing Diagram
IN
50%
t
bl
CS
HO
90%
CS
HO
V
CSTH
t
cs
90%
FAULT
Figure3. Start-up Blanking Time Waveform Definitions Figure 4. CS Shutdown Waveform Definitions
CS
FAULT
B-134 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
Figure 5. CS to
V
CSTH
t
flt
90%
FAULT
Waveform Definitions
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