Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
•
Undervoltage lockout
•
CMOS Schmitt-triggered inputs with pull-down
•
• Output in phase with input (IR2117) or out of
phase with input (IR2118)
Also available LEAD-FREE
•
Description
The IR2117/IR2118(S) is a high voltage, high speed
power MOSFET and IGBT driver. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized
monolithic construction. The logic input is compatible
with standard CMOS outputs. The output driver features a high pulse current buffer stage designed for
minimum cross-conduction. The floating channel can
be used to drive an N-channel power MOSFET or IGBT
in the high or low side configuration which operates up
to 600 volts.
Typical Connection
Product Summary
V
OFFSET
+/-200 mA / 420 mA
I
O
V
OUT
t
(typ.)125 & 105 ns
on/off
Packages
8-Lead PDIP
IR2117/IR2118
up to 600V
600V max.
10 - 20V
8-Lead SOIC
IR2117S/IR2118S
V
CC
IN
V
CC
COM
V
B
HOIN
V
S
TO
LOAD
IR2117
up to 600V
(Refer to Lead Assignments for correct pin configuration).
This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for
proper circuit board layout.
V
CC
IN
V
CC
COM
V
B
HOIN
V
S
IR2118
TO
LOAD
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Page 2
IR2117(S)/IR2118(S) & ( PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 5 through 8.
SymbolDefinitionMin.Max.Units
V
B
V
S
V
HO
V
CC
V
IN
dVs/dtAllowable offset supply voltage transient (figure 2)—50V/ns
P
D
Rth
JA
T
J
T
S
T
L
High side floating supply voltage-0.3625
High side floating supply offset voltageVB - 25VB + 0.3
CC
B
+ 0.3
+ 0.3
High side floating output voltageVS - 0.3V
Logic supply voltage-0.325
Logic input voltage-0.3V
Package power dissipation @ TA ≤ +25°C(8 lead PDIP)—1.0
(8 lead SOIC)—0.625
Thermal resistance, junction to ambient(8 lead PDIP)—125
(8 lead SOIC)—200
Junction temperature—150
Storage temperature-55150
Lead temperature (soldering, 10 seconds)—300
W
°C/W
°C
V
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
SymbolDefinitionMin.Max.Units
V
B
V
S
V
HO
V
CC
V
IN
T
A
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
2www.irf.com
High side floating supply absolute voltageVS + 10VS + 20
High side floating supply offset voltageNote 1600
High side floating output voltageV
Logic supply voltage1020
Logic input voltage0V
Ambient temperature-40125°C
S
V
B
CC
V
Page 3
IR2117(S)/IR2118(S) & ( PbF)
Dynamic Electrical Characteristics
V
(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics
BIAS
are measured using the test circuit shown in Figure 3.
SymbolDefinitionMin. Typ. Max. Units Test Conditions
t
on
t
off
t
t
Static Electrical Characteristics
V
(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
BIAS
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
SymbolDefinitionMin. Typ. Max. Units Test Conditions
Output high short circuit pulsed current200250—VO = 0V
Output low short circuit pulsed current420500—VO = 15V
mA
= 0V or V
IN
V
= Logic “1”
IN
PW ≤ 10 µs
V
= Logic “0”
IN
PW ≤ 10 µs
CC
CC
CC
CC
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Page 4
IR2117(S)/IR2118(S) & ( PbF)
Functional Block Diagram (IR2117)
V
CC
COM
IN
UV
DETECT
PULSE
GEN
Functional Block Diagram (IR2118)
V
CC
IN
PULSE
GEN
LEVEL
HV
LEVEL
SHIFT
HV
SHIFT
UV
DETECT
PULSE
FILTER
UV
DETECT
PULSE
FILTER
V
B
R
Q
R
S
R
Q
R
S
V
HO
V
HO
V
S
B
S
UV
DETECT
COM
4www.irf.com
Page 5
IR2117(S)/IR2118(S) & ( PbF)
Lead Definitions
SymbolDescription
V
CC
INLogic input for gate driver output (HO), in phase with HO (IR2117)
INLogic input for gate driver output (HO), out of phase with HO (IR2118)
COMLogic ground
V
B
HOHigh side gate drive output
V
S
Lead Assignments
Logic and gate drive supply
High side floating supply
High side floating supply return
1
V
CC
2
IN
3
COM
4
V
HO
V
8
B
7
6
S
5
1
2
IN
3
COM
4
8 Lead PDIP8 Lead SOIC
IR2117IR2117S
1
V
CC
2
IN
3
COM
4
8 Lead PDIP8 Lead SOIC
V
HO
V
8
B
7
6
S
5
1
V
2
IN
3
COM
4
IR2118IR2118S
V
CC
CC
V
HO
V
V
HO
V
8
B
7
6
S
5
8
B
7
6
S
5
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Page 6
IR2117(S)/IR2118(S) & ( PbF)
IN
(IR2118)
IN
(IR2117)
HO
Figure 1. Input/Output Timing Diagram
IR2117/IR2118
IR2117/IR2118
<50 V/ns
Figure 2. Floating Supply Voltage Transient Test Circuit
IN
(IR2118)
50%
50%
50%50%
IN
(IR2117)
t
t
r
on
90%90%
t
t
f
off
HO
10%10%
Figure 3. Switching Time Test CircuitFigure 4. Switching Time Waveform Definition