Datasheet IR 2110 Datasheet

Data Sheet No. PD60147 Rev.

T

IR2110(S)/IR2113(

S) & (PbF

HIGH AND LOW SIDE DRIVER

Features

• Floating channel designed for bootstrap operation

Fully operational to +500V or +600V
Tolerant to negative transient voltage
dV/dt immune

• Gate drive supply range from 10 to 20V

• Undervoltage lockout for both channels

• 3.3V logic compatible

Separate logic supply range from 3.3V to 20V
Logic and power ground ±5V offset

• CMOS Schmitt-triggered inputs with pull-down

• Cycle by cycle edge-triggered shutdown logic

• Matched propagation delay for both channels

• Outputs in phase with inputs

Also available LEAD-FREE

•

Description

The IR2110/IR2113 are high voltage, high speed power MOSFET and
IGBT drivers with independent high and low side referenced output
channels. Proprietar y HVIC and latch immune CMOS technologies
enable ruggedized monolithic construction. Logic inputs are compat­ible with standard CMOS or LSTTL output, down to 3.3V logic. The
output drivers feature a high pulse current buff er stage designed f or minimum driver cross-conduction. Propaga­tion delays are matched to simplify use in high frequency applications. The floating channel can be used to drive
an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts.

Product Summary

V

OFFSET

(IR2113) 600V max.

Delay Matching (IR2110) 10 ns max.
(IR2113) 20ns max.

(IR2110) 500V max.

+/- 2A / 2A

I

O

V

OUT

t

(typ.) 120 & 94 ns

on/off

10 - 20V

Packages

14-Lead PDIP

IR2110/IR2113

16-Lead SOIC

IR2110S/IR2113S

)

Typical Connection

HO

V

DD

HIN

SD
LIN

V

SS

V

CC

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only . Please ref er to our Application Notes and DesignTips f or proper circuit board lay out.

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V

DD

HIN
SD
LIN
V

SS

V

COM

LO

V

B

V

S

CC

up to 500V or 600V

TO

LOAD

IR2110(S)/IR2113( S ) & (PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

DD

V

SS

V

IN

dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns

P

D

R

THJA

T

J

T

S

T

L

High side floating supply voltage (IR2110) -0.3 525

(IR2113) -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V

B

+ 0.3
Low side fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3
Logic supply voltage -0.3 VSS + 25
Logic supply offset voltage VCC - 25 V
Logic input voltage (HIN, LIN & SD) VSS - 0.3 V

CC
DD

+ 0.3
+ 0.3

Package power dissipation @ TA ≤ +25°C (14 lead DIP) — 1.6

(16 lead SOIC) — 1.25

Thermal resistance, junction to ambient (14 lead DIP) — 75

(16 lead SOIC) — 100
Junction temperature — 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) — 300

V

W

°C/W

°C

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. T ypical
ratings at other bias conditions are shown in figures 36 and 37.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

DD

V

SS

V

IN

T

A

Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When VDD < 5V, the minimum VSS offset is limited to -V

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High side floating supply absolute voltage VS + 10 VS + 20
High side floating supply offset voltage (IR2110) Note 1 500

(IR2113) Note 1 600

High side floating output voltage V

S

V

B

Low side fixed supply voltage 10 20
Low side output voltage 0 VCC
Logic supply voltage VSS + 3 VSS + 20
Logic supply offset voltage -5 (Note 2) 5
Logic input voltage (HIN, LIN & SD) V

SS

V

DD

Ambient temperature -40 125 °C

DD.

V

IR2110(S)/IR2113( S) & (PbF)

Dynamic Electrical Characteristics

V

(VCC, VBS, VDD) = 15V, CL = 1000 pF, T

BIAS

electrical characteristics are measured using the test circuit shown in Figure 3.

Symbol Definition Figure Min. Typ. Max. Units T est Conditions

t
t
t

MT Delay matching, HS & LS (IR2110) — — — 10

turn-on/off (IR2113) — — — 20

Turn-on propagation delay 7 — 120 150 VS = 0V

on

Turn-off propagation delay 8 — 94 125 VS = 500V/600V

off

Shutdown propagation delay 9 — 110 140 VS = 500V/600V

sd

t

Turn-on rise time 10 — 25 35

r

t

Turn-off fall time 11 — 17 25

f

Static Electrical Characteristics

V

(VCC, VBS, VDD) = 15V, T

BIAS

are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

V

V
V
V

I

I

QBS

I

QCC

I

QDD

I

I

V

BSUV+

V

BSUV-

V

CCUV+

V

CCUV-

I

OH

OL

LK

IN+

IN-

O+

I

O-

IH

Logic “1” input voltage 12 9.5 — —
Logic “0” input voltage 13 — — 6.0

IL

High level output voltage, V
Low level output voltage, V
Offset supply leakage current 16 — — 50 VB=VS = 500V/600V
Quiescent VBS supply current 17 — 125 230 V
Quiescent VCC supply current 18 — 180 340 VIN = 0V or V
Quiescent VDD supply current 19 — 15 30 VIN = 0V or V
Logic “1” input bias current 20 — 20 40 VIN = V
Logic “0” input bias current 21 — — 1.0 V

VBS supply undervoltage positive going 22 7.5 8.6 9.7
threshold
VBS supply undervoltage negative going 23 7.0 8.2 9.4
threshold
VCC supply undervoltage positive going 24 7.4 8.5 9.6
threshold
VCC supply undervoltage negative going 25 7.0 8.2 9.4
threshold
Output high short circuit pulsed current 26 2.0 2.5 — VO = 0V, VIN = V

Output low short circuit pulsed current 27 2.0 2.5 — VO = 15V , VIN = 0V

= 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters

A

BIAS

O

= 25°C and VSS = COM unless otherwise specified. The dynamic

A

ns

µA

V

V

IN

A

PW ≤ 10 µs

PW ≤ 10 µs

- V

O

14 — — 1.2 IO = 0A
15 — — 0.1 IO = 0A

= 0V or V

DD

= 0V

IN

DD
DD
DD

DD

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IR2110(S)/IR2113( S ) & (PbF)

Functional Block Diagram

V

DD

HIN

SD

LIN

V

RSQ

RSQ

SS

VDD/V

LEVEL
SHIFT

VDD/V

LEVEL

SHIFT

CC

PULSE

GEN

CC

Lead Definitions

Symbol Description

V

DD

HIN Logic input for high side gate driver output (HO), in phase
SD Logic input for shutdown
LIN Logic input for low side gate driver output (LO), in phase
V

SS

V

B

HO High side gate drive output
V

S

V

CC

LO Low side gate drive output
COM Low side return

Logic supply

Logic ground
High side floating supply

High side floating supply return
Low side supply

HV
LEVEL
SHIFT

UV

DETECT

PULSE
FILTER

DETECT

UV

DELAY

RQ
R
S

V

B

HO

V

S

V

CC

LO

COM

Lead Assignments

14 Lead PDIP 16 Lead SOIC (Wide Body)

IR2110/IR2113 IR2110S/

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IR2113S

IR2110(S)/IR2113( S) & (PbF)

200

HO

10KF6

IRF820

HV = 10 to 500V/600V

µH

V =15V

cc

11

12

9

10

13

10KF6

36

5
7

1

2

OUTPUT
MONITOR

0.1

µ

F

0.1

10

µF

µF

Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit

V =15V

cc

50%

t

off

90% 90%

HIN

LIN

SD

V

10

0.1

µ

µ

F

F

9

36

10

11

12

13

5
7

1

2

0.1
F

µ

C

L

HO

LO

C

L

+

10

15V

µ

F

(0 to 500V/600V)

10

µ

F

B

-

V

S

HIN
LIN

HO
LO

50%

t

on

t

r

10% 10%

t

f

10KF6

dV

+

S

dt

100µF

>50 V/ns

Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition

HIN

50%

50%

LIN

SD

HO
LO

50%

t

sd

90%

MT

LO

HO

10%

MT

90%

HOLO

Figure 6. Delay Matching Waveform DefinitionsFigure 5. Shutdown Waveform Definitions

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IR2110(S)/IR2113( S ) & (PbF)

T

s)

T

s)

T

s)

T

s)

0

250

200

150

Max.

Typ.

100

urn-On Delay Time (n

50

0

-50 -25 0 25 50 75 100 125
Temperature (°C)

250

200

Max.

Typ.

150

100

urn-On Delay Time (n

50

0

10 12 14 16 18 20

VCC/VBS Supply Voltage (V)

Figure 7A. T urn-On Time vs. Temperature Figure 7B. T urn-On Time vs. VCC/VBS Supply Voltage

250

Max .

200

Typ

150

.

100

Turn-On Delay Time (ns)

50

0

0 2 4 6 8 101214161820

VDD Supply Voltage (V)

Figure 7C. Turn-On Time vs. VDD Supply Volta ge

250

200

150

Max.

100

Typ.

urn-Off Delay Time (n

50

0

-50 -25 0 25 50 75 100 125
Temperature (°C)

Figure 8A. Turn-Off Time vs. Temperature

250

200

Max.

150

Typ.

100

urn-Off Delay Time (n

50

0

10 12 14 16 18 20

VCC/VBS Supply Voltage (V)

Figure 8B. Turn-Off Time vs. VCC/VBS Supply Voltage

250

200

Max

.

150

100

50

Turn-Off Delay Time (ns)

Typ

0

0 2 4 6 8 10 12 14 16 18 2

VDD Supply Voltage (V)

Figure 8C. Turn-Off Time vs. VDD Supply Voltage

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