Page 1
8-Bit Serial-Input/Serial or
Parallel-Output Shift Register
with Latched 3-State Outputs
High-Performance Silicon-Gate CMOS
The IN74HC595A is identical in pinout to the LS/ALS595. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC595A consists of an 8-bit shift register and an 8-bit Dtype latch with three-state parallel outputs. The shift register accepts
serial data and provides a serial output. The shift register also provides
parallel data to the 8-bit latch. The shift register and latch have
independent clock inputs. This device also has an asynchronous reset
for the shift register.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0 µA
•
High Noise Immunity Characteristic of CMOS Devices
TECHNICAL DATA
IN74HC595A
ORDERING INFORMATION
IN74HC595AN Plastic
IN74HC595AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
PIN 8 = GND
CC
423
Page 2
IN74HC595A
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
I
OUT
I
CC
P
DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+
±
20
±
35
±
75
750
500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
VIN, V
T
A
tr, t
f
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
Unused outputs must be left open.
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
Input Rise and Fall Time (Figure 1) VCC =2.0 V
IN
or V
OUT
)≤VCC.
V
CC
V
CC
and V
IN
=4.5 V
=6.0 V
OUT
should be constrained to the range
0
0
0
CC
1000
500
400
V
°
C
ns
CC
).
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IN74HC595A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
OH
V
OL
V
OH
V
OL
I
IN
Minimum High-Level
IH
Input Voltage
Maximum Low -
IL
Level Input Voltage
Minimum High-Level
Output Voltage, Q
Q
H
Maximum Low-Level
Output Voltage, Q
Q
H
Minimum High-Level
Output Voltage, SQ
Maximum Low-Level
Output Voltage, SQ
Maximum Input
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
V
=0.1 V or VCC-0.1 V
OUT
≤
I
20 µA
OUT
-
A
-
A
H
H
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
VIN=VIH or V
≤
I
OUT
VIN=VIH or V
≤
I
OUT
≤
I
OUT
IL
20 µA
IL
6.0 mA
7.8 mA
IL
20 µA
IL
6.0 mA
7.8 mA
IL
20 µA
IL
4.0 mA
5.2 mA
IL
20 µA
IL
4.0 mA
5.2 mA
VIN=VCC or GND 6.0
Leakage Current
I
OZ
Maximum ThreeState Leakage
Current, Q
A-QH
Output in High-Impedance
State
V
= VIL or V
IN
IH
VIN=VCC or GND
I
CC
Maximum Quiescent
Supply Current
VIN=VCC or GND
=0µA
I
OUT
(per Package)
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
0.1
±
0.5
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
1.0
±
5.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
±
6.0 4.0 40 160
C
1.0
10
Unit
V
V
V
V
V
V
µ
A
µ
A
µ
A
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IN74HC595A
AC ELECTRICAL CHARACTERISTICS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
f
max
Minimum Clock Frequency (50 % D ut y Cycle)
(Figures 1and 7)
t
PLH
, t
Maximum Propagation Delay, Shift Clock to SQ
PHL
H
(Figures 1and 7)
t
PHL
Maximum Propagation Delay , Reset to SQ
H
(Figures 2 and 7)
t
t
t
t
TLH
PLH
PLZ
PZL
, t
, t
, t
, t
Maximum Propagat ion Delay , Latch Clock to
PHL
Q
(Figures 3 and 7)
A-QH
Maximum Propagation Delay , Output Enable to
PHZ
Q
(Figures 4 and 8)
A-QH
Maximum Propagation Delay , Output Enable to
PZH
Q
(Figures 4 and 8)
A-QH
Maximum Output Transition Time, QA-Q
THL
H
(Figures 3 and 7)
t
TLH
, t
Maximum Output Transition Time, SQ
THL
H
(Figures 1 and 7)
C
IN
C
OUT
Maximum Input Capacitance - 10 10 10 pF
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A-QH
V
CC
Guaranteed Limit
25 °C
to
≤
85
°
C
≤
125
°
C
Unit
-55°C
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
6.0
30
35
140
28
24
145
29
25
140
28
24
150
30
26
135
27
23
60
12
10
75
15
13
4.8
24
28
175
35
30
180
36
31
175
35
30
190
38
33
170
34
29
75
15
13
95
19
16
4.0
20
24
210
42
36
220
44
38
210
42
36
225
45
38
205
41
35
90
18
15
110
22
19
MHz
ns
ns
ns
ns
ns
ns
ns
-151515pF
426
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D=CPDVCC
2
f+ICCV
CC
Typical @25°C,V
300 pF
=5.0 V
CC
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IN74HC595A
TIMING REQUIREMENTS
(CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter V
t
su
Minimum Setup Time,Serial Data
Input A to Shift Clock (Figure 5)
t
su
Minimum Setup Time, Shift Clock to
Latch Clock (Figure 6)
t
h
Minimum Hold Time, Shift Clock to
Serial Data Input A (Figure 5)
t
rec
Minimum Rec overy Time, Re set
Inactive to Shift Clock (Figure 2)
t
w
t
w
Minimum Pulse Width, Reset (Figure2)2.0
Minimum Pulse Width, Shift Clock
(Figure 1)
t
w
Minimum Pulse Width, Latch Clock
(Figure 6)
tr, t
Maximum Input Rise an d Fall Times
f
(Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
CC
Guaranteed Limit
25 °C to
-55°C
50
10
9
75
15
13
5
5
5
50
10
9
60
12
10
50
10
9
50
10
9
1000
500
400
≤85°
65
13
11
95
19
16
5
5
5
65
13
11
75
15
13
65
13
11
65
13
11
1000
500
400
≤
C
125°C
75
Unit
ns
15
13
110
ns
22
19
5
ns
5
5
75
ns
15
13
90
ns
18
15
75
ns
15
13
75
ns
15
13
1000
ns
500
400
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IN74HC595A
FUNCTION TABLE
Inputs Resulting Function
Operation Reset Serial
Input
A
Shift
Clock
Latch
Clock
Output
Enable
Shift
Register
Contents
Latch
Register
Contents
Reset shift register L X X L,H, L L U L U
Serial
Output
SQ
H
Outputs
Parallel
Q
A-QH
Shift data into shift
register
Shift register remains
H D L,H, L D SR
SRN SR
A
N+1
USR
H X L,H, L,H, L U U U U
unchanged
Transfer shift register
HXL,H, L U SRN LR
contents to latch
register
Latch register remains
XXXL,H,L * U * U
unchanged
Enable parallel
XXXX L * ** * Enabled
outputs
Force outputs into
XXXX H * ** * Z
high-impedance stat e
SR = shift register contents X = don’t care
LR = latch register contents Z = high impedance
D = data (L,H) logic level * = depends on Reset and Shift Clock inputs
U = remains unchanged ** = depends on Latch Cl ock input
PIN DESCRIPTIONS
INPUTS:
- Serial Data Input. The data on this pin is shifted
A
into the 8-bit serial shift register.
CONTROL INPUTS:
Shift Clock
high transition on this input causes the data at the
Serial Input pin to be shifted into the 8-bit shift
register.
Reset
Reset Input. A low on this pin resets the shift
register portion of this device only. The 8-bit latch
is not affected.
Latch Clock
to-high transition on this input latches the shift
register data.
- Shift Register Clock Input. A low-to-
- Active-low, Asynchronous, Shift Register
- Storage Latch Clock Input. A low-
Output Enable
low on this input allows the data from the latches to
bepresented at the outputs. A high on this input
forces the outputs (Q
state. The serial output is not affected by this
control unit.
OUTPUTS:
- Noninverted, 3-state, latch outputs.
QA-Q
H
- Voninverted, Serial Data Output. This is the
SQ
H
output of the eighth stage of the 8-bit shift register.
This output does not have three-state capability.
- Active-Low Output Enable. A
) into the high-impedance
A-QH
SR
G
H
USR
N
U
N
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Page 7
IN74HC595A
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
Figure 5. Switching Waveforms Figure 6. Switching Waveforms
Figure 7. Test Circuit Figure 8. Test Circuit
429
Page 8
IN74HC595A
TIMING DIAGRAM
430
Page 9
EXPANDED LOGIC DIAGRAM
IN74HC595A
431
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