Datasheet IN74HC30AN, IN74HC30AD, IN74HC30A Datasheet (INTEGRAL)

8-Input NAND Gate

The IN74HC30A is high-speed Si-gate CMOS device and is compatible with low power Schottky TTL (LSTTL) . The device provide the 8-input NAND function.

•

Outputs Directly Interface to CMOS, NMOS, and TTL

•

Operating Voltage Range: 2.0 to 6.0 V

•

Low Input Current: 1.0 µA

•

High Noise Immunity Characteristic of CMOS Devices

LOGIC DIAGRAM

TECHNICAL DATA

IN74HC30A

ORDERING INFORMATION

IN74HC30AN Plastic IN74HC30AD SOIC IZ74HC30A Chip

TA = -55° ÷ 125° C for all packages

A

PIN ASSIGNMENT

B

1

A

C

D

Y

E

F

G

H

GND

2

B

C

3

4

D

5

E

F

6

7

14

13

12

11

10

9

8

V

CC

-

H

G

-.

-

Y

FUNCTION TABLE

PIN 14 =V

PIN 7 = GND

CC

Inputs Output

ABС DEFGH Y

LXXXXXXX H

XL XXXXXX H

XXLXXXXX H

XXXLXXXX H

XXXXLXXX H

XXXXXLXX H

XXXXXXLX H

XXXXXXXL H

HHHHHHHH L

INTEGRAL

X = don’t care

1

IN74HC30A

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

OUT

I

IN

I

OUT

I

CC

P

DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V

DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V

IN

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

DC Input Current, per Pin

DC Output Current, per Pin

DC Supply Current, VCC and GND Pins

Power Dissipation in Still Air, Plastic DIP**

D

SOIC Package**

±

20

±

25

±

50

750 500

Tstg Storage Temperature -65 to +150

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

260

(Plastic DIP or SOIC Package)

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

mA

mW

°

C

°

C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

CC

VIN, V

OUT

T

A

tr, t

f

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V

)≤VCC.

V

OUT

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V outputs must be left open.

DC Supply Voltage (Referenced to GND) 2.0 6.0 V

DC Input Voltage, Output Voltage (Referenced to GND) 0 V

Operating Temperature, All Package Types -55 +125

Input Rise and Fall Time (Figure 1) VCC =2.0 V

V

=4.5 V

CC

V

=6.0 V

CC

and V

IN

should be constrained to the range GND≤(VIN or

OUT

0 0 0

CC

1000

500 400

°

ns

). Unused

CC

V

C

INTEGRAL

2

IN74HC30A

DC ELECTRICAL CHARACTERISTICS

V

OH

V

OL

I

IL

I

IH

I

CC

Minimum High-Level

IH

Input Voltage

Maximum Low -Level

IL

Input Voltage

Minimum High-Level Output Voltage

Maximum Low-Level Output Voltage

Maximum Low-Level

≤

V

0.1V or

OUT

≥VCC-0.1V

V

OUT



≤

I

20 μA

OUT

≤

V

0.1V or

OUT

≥VCC-0.1V

V

OUT



≤

I

20 μA

OUT

VIN=VIH or V



 ≤

I

OUT

VIN= VIH or V



 ≤

I

OUT

VIN= VIH or V



 ≤

I

OUT

= VIH or V

V

IN



 ≤

I

OUT

VIN= VIH or V



 ≤

I

OUT

VIN= VIH or V



 ≤

I

OUT

VIN= VIH or V



 ≤

I

OUT

= VIH or V

V

IN



 ≤

I

OUT

IL

- 20 μA

IL

- 2.4 mA

IL

- 4.0 mA

IL

- 5.2 mA

IL

20 μA

IL

2.4 mA

IL

4.0 mA

IL

5.2 mA

VIN= 0 V 6.0 -0.1 -1.0 -1.0

Input Leakage Current

Maximum High-Level

VIN= V

CC

Input Leakage Current

Maximum Quiescent Supply Current

VIN=VCC or 0 V I

=0 μA

OUT

(per Package)

(Voltages Referenced to GND)

V

CC

V

Guaranteed LimitSymbol Parameter Test Conditions

25 °C

to

-55°C

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

4.5

6.0

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

3.0 2.48 2.34 2.20

4.5 3.98 3.84 3.70

6.0 5.48 5.34 5.20

2.0

4.5

6.0

0.1

3.0 0.26 0.33 0.4

4.5 0.26 0.33 0.4

6.0

0.26 0.33 0.4

6.0 0.1 1.0 1.0

6.0 2.0 20 40

≤

85

°

C

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

0.1

≤

125

°

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

0.1

Unit

C

V

µ

A

µ

A

µ

A

INTEGRAL

3

IN74HC30A

AC ELECTRICAL CHARACTERISTICS

(CL=50pF,Input tr=tf=6.0 ns)

Symbol Parameter V

t

THL

PHL

, t

Maximum Propagation Delay (Figure 1) 2.0

PLH

Maximum Output Transition Time

TLH

(Figure 1)

C

IN

Maximum Input Capacitance 5.0 10 10 10 pF

Power Dissipation Capacitance (Per Gate)

C

PD

Used to determine the no-load dynamic power consumption: P

D=CPDVCC

2

f+ICCV

Input

Output

CC

0.9

t

f

V

2

0.1 0.1

t

PLH

V

2

0.1

t

TLH

0.9

V

4.5

6.0

2.0

4.5

6.0

t

CC

Guaranteed Limit

25 °C

≤85°C≤

125°C

Unit

to

-55°C

175

35 30

75 15 13

T

=25°C,VCC=5.0 V

A

220

44 37

95 19 16

265

53 45

110

22 19

ns

27 pF

r

0.9

V

2

t

PHL

0.9 V

t

THL

V

1

GND

V

CC

2

0.1

0 V

PULSE

GENERATOR

V = V

1 CC

V = 0.5 V

2 CC

V

I

Figure 1. Switching Waveforms

V

CC

V

DEVICE UNDER

R

TEST

T

O

C

50 pF

L

Termination resistance RT – should be equal to Z

of pulse generators

OUT

Figure 2. Test Circuit

INTEGRAL

4

CHIP PAD DIAGRAM IZ74HC30A

IN74HC30A

09

10

11

±

1.27 0.03

01

02

Pad size 0.108 x 0.108 mm (Pad size is given as per Thickness of chip 0.46 ± 0,02 mm

03

1.03 0.03

±

08

04

metallization

07

06

05

layer)

Chip marking

74HC30

(x=0.788; y=0.298

)

PAD LOCATION

Pad No Symbol X Y

01 А 0.1155 0.7200

02 B 0.1155 0.4015

03 C 0.1355 0.1465

04 D 0.3080 0.1160

05 E 0.6220 0.1160

06 F 0.8130 0.1465

07 GND 0.8130 0.4810

08

09---

10---

11 G 0.6220 1.0465

12 H 0.3080 1.0465

13---

14 Vcc 0.1155 0.9670

Y

0.8130 0.8000

INTEGRAL

5