Datasheet ILC7080AIM5-50, ILC7080AIM5-36, ILC7080AIM5-33, ILC7080AIM5-30, ILC7080AIM5-285 Datasheet (Impala Linear Corporation)
...Page 1
ILC7080/81
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Cor poration
Impala Linear Corporation
1
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
The ILC7080/81 are 50 or 100mA low dropout (LDO) voltage regulators designed to provide a high performance
solution to low power systems.
The devices offer a typical combination of low dropout
and low quiescent current expected of CMOS parts,
while uniquely providing the low noise and high ripple
rejection characteristics usually only associated with
bipolar LDO regulators.
The devices have been optimized to meet the needs of
modern wireless communications design; Low noise, low
dropout, small size, high peak current, high noise immunity. The ILC7080/81 are designed to make use of low cost
ceramic capacitors while outperforming other devices that
require tantalum capacitors.
General Description
Features
• Ultra low 1mV dropout per 1mA load
• 1% output voltage accuracy
• Uses low ESR ceramic output capacitor to minimize
noise and output ripple
• Only 100µA ground current at 100mA load
• Ripple rejection up to 85dB at 1kHz, 60dB at 1MHz
• Less than 80µV
RMS
noise at BW = 100Hz to 100kHz
• Excellent line and load transient response
• Over current / over temperature protection
• Guaranteed up to 80/150mA output current
• Industry standard five lead SOT-23 package
• Fixed 2.85V, 3.0V, 3.3V, 3.6V, 4.7V, 5.0V and adjustable
output voltage options
• Metal mask option available for custom voltages between
2.5 to 10V
• Cellular phones
• Wireless communicators
• PDAs / palmtops / organizers
• Battery powered portable electronics
Applications
Typical Circuit
ILC7080
ILC7081
V
OUT
V
IN
C
OUT
C
NOISE
SOT23-5
123
45
ON
OFF
Ordering Information (TA = -40°C to +85°C)
ILC7080AIM5-xx
50mA, fixed voltage
ILC7080AIM5-ADJ
50mA adjustable voltage
ILC7081AIM5-xx
100mA, fixed voltage
ILC7081AIM5-ADJ
100mA, adjustable voltage
Note: Fixed voltage options are defined by 2-digit code as shown in the
package markings information section of the datasheet.
Page 2
50/100mA SOT-23 CMOS RF LDO™ Regulators
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ILC7080/81 1.1
Pin Description ILC7081/81-xx (fixed voltage version)
Pin
Number
Pin Name
Pin Description
1
VIN
Connect direct to supply
2
GND
Ground pin. Local ground for C
NOISE
and C
OUT
.
3
ON/OFF
By applying less than 0.4V to this pin the device will be turned off.
4
C
NOISE
Optional noise bypass capacitor may be connected between this
pin and GND (pin 2). Do not connect C
NOISE
directly to the main
power ground plane.
5
V
OUT
Output Voltage. Connect C
OUT
between this pin and GND (pin 2)
Pin Description ILC7081/81-ADJ (adjustable voltage version)
Pin
Number
Pin Name
Pin Description
1
VIN
Connect direct to supply
2
GND
Ground pin. Local ground for C
NOISE
and C
OUT
.
3
ON/OFF
By applying less than 0.4V to this pin the device will be turned off.
4
V
ADJ
Voltage feedback pin to set the adjustable output voltage. Do not
connect a capacitor to this pin.
5
V
OUT
Output Voltage. Connect C
OUT
between this pin and GND (pin 2)
Pin Package Configurations
ILC7080-xx
ILC7081-xx
SOT23-5
ON
OFF
C
NOISE
V
IN
V
OUT
GND
123
45
ILC7080-ADJ
ILC7081-ADJ
SOT23-5
ON
OFF
V
ADJ
V
IN
V
OUT
GND
123
45
Page 3
50/100mA SOT-23 CMOS RF LDO™ Regulators
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Sept. 1998
ILC7080/81 1.1
Parameter
Symbol
Ratings
Units
Input voltage
On/Off Input voltage
VIN
V
ON/OFF
-0.3 to +13.5
-0.3 to V
IN
V
Output Current
I
OUT
Short circuit protected
mA
Output voltage
V
OUT
-0.3 to VIN+0.3
V
Package Power Dissipation
(SOT-23-5)
PD
250
(Internally Limited)
mW
Maximum Junction Temp Range
T
J(max)
-40~+150
°C
Storage Temperature
T
STG
-40~+125
°C
Operating Ambient Temperature
TA
-40 to +85
°C
Package Thermal Resistance
θJA
333
°C/W
Absolute Maximum Ratings (Note 1)
Absolute Maximum Ratings (Note 1)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input Voltage Range
VIN
2
13
V
Output voltage
V
OUT
I
OUT
= 1mA
1mA < I
OUT
< 100mA
1mA < I
OUT
< 100mA
-1
-1.5
-3.5
V
OUT(NOM)
+1
1.5
+3.5
%
Feedback Voltage
(ADJ version)
V
ADJ
1.215
1.202
1.240
1.265
1.278
V
Line Regulation
∆V
OUT
/
(V
OUT
*∆VIN)
V
OUT(NOM)
+ 1V < VIN < 12V
0.007
0.014
0.032
%/V
I
OUT
= 0mA
0.1
1
2
I
OUT
= 10mA
10
25
35
7080/81
I
OUT
= 50mA
50
75
100
I
OUT
= 100mA
100
150
200
Dropout voltage
(Note 3)
VIN – V
OUT
7081 only
I
OUT
= 150mA
150
225
300
mV
Unless otherwise specified, all limits are at TA= 25°C; VIN= V
OUT(NOM)
+ 1V, I
OUT
= 1mA, C
OUT
= 1µF, V
ON/OFF
= 2V.
Boldface limits apply over the operating temperature range. (Note 2)
Page 4
50/100mA SOT-23 CMOS RF LDO™ Regulators
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ILC7080/81 1.1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
I
OUT
= 0mA
95
200
220
I
OUT
= 10mA
100
220
240
7080/81
I
OUT
= 50mA
100
220
240
I
OUT
= 100mA
100
240
260
Ground Pin Current
I
GND
7081
only
I
OUT
= 150mA
115
260
280
µA
Shutdown (OFF) Current
I
ON/OFF
V
ON/OFF
= 0V
0.1 2 µA
ON/OFF Input Voltage
V
ON/OFF
High = Regulator On
Low = Regulator Off
2.0 13
0.6
V
ON/OFF Pin Input Current
(Note 5)
I
IN(ON/OFF)
V
ON/OFF
= 0.6V, regulator OFF
V
ON/OFF
= 2V, regulator ON
0.3 1
µA
Peak Output Current
(Note 4)
I
OUT(PEAK)
V
OUT
> 0.95V
OUT(NOM)
,
tpw = 2ms
400
500 mA
Output Noise Voltage
eN
BW = 300Hz to 50kHz,
C
NOISE
= 0.01µF
80 µV
RMS
freq = 1kHz
85
freq = 10kHz
70
Ripple Rejection
∆V
OUT
/∆VIN
C
OUT
= 4.7µF,
I
OUT
= 100mA
freq = 1MHz
60
dB
Dynamic Line Regulation
∆V
OUT(line)
VIN: V
OUT(NOM)
+ 1V to
V
OUT(NOM)
+ 2V,
tr/tf = 2µs; I
OUT
= 100mA
4
mV
Dynamic Load Regulation
∆V
OUT(load)
I
OUT
: 0 to 100mA;
d(I
OUT
)/dt = 100mA/µs
with C
OUT
= 0.47µF
with C
OUT
= 2.2µF
50
25
mV
Short Circuit Current
ISC
V
OUT
= 0V
600 mA
Note 1: Absolute maximum ratings indicate limits which when exceeded may result in damage to the component. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.
Note 2: Specified Min/Max limits are production tested or guaranteed through correlation based on statistical control methods. Measurements are taken at constant junction
temperature as close to ambient as possible using low duty pulse testing.
Note 3: Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the nominal value measured with a 1V differential.
Note 4: Guaranteed by design
Note 5: The device’s shutdown pin includes a 2MW internal pull down resistor connected to ground.
Electrical Characteristics ILC7080/81AIM5 (cont.)
Unless otherwise specified, all limits are TA= 25°C; VIN= V
OUT(NOM)
+ 1V, I
OUT
= 1mA, C
OUT
= 1µF, V
ON/OFF
= 2V.
Boldface limits apply over the operating temperature range. (Note 2)
Page 5
50/100mA SOT-23 CMOS RF LDO™ Regulators
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Sept. 1998
ILC7080/81 1.1
The ILC7080/81 LDO design is based on an advanced circuit configuration for which patent protection has been
applied. Typically it is very difficult to drive a capacitive output with an amplifier. The output capacitance produces a
pole in the feedback path, which upsets the carefully tailored dominant pole of the internal amplifier. Traditionally
the pole of the output capacitor has been “eliminated” by
reducing the output impedance of the regulator such that
the pole of the output capacitor is moved well beyond the
gain bandwidth product of the regulator. In practice, this is
difficult to do and still maintain high frequency operation.
Typically the output impedance of the regulator is not simply resistive, such that the reactive output impedance interacts with the reactive impedance of the load resistance and
capacitance. In addition, it is necessary to place the dominant pole of the circuit at a sufficiently low frequency such
that the gain of the regulator has fallen below unity before
any of the complex interactions between the output and the
load occur. The ILC7080/81 does not try to eliminate the
output pole, but incorporates it into the stability scheme.
The load and output capacitor forms a pole, which rolls off
the gain of the regulator below unity. In order to do this the
output impedance of the regulator must be high, looking like
a current source. The output stage of the regulator
becomes a transconductance amplifier, which converts a
voltage to a current with a substantial output impedance.
The circuit which drives the transconductance amplifier is
the error amplifier, which compares the regulator output to
the band gap reference and produces an error voltage as
the input to the transconductance amplifier. The error amplifier has a dominant pole at low frequency and a “zero”
which cancels out the effects of the pole. The zero allows
the regulator to have gain out to the frequency where the
output pole continues to reduce the gain to unity. The configuration of the poles and zero are shown in figure 1.
Instead of powering the critical circuits from the unregulated input voltage, the CMOS RF LDO powers the internal
circuits such as the bandgap, the error amplifier and most
of the transconductance amplifier from the boot strapped
regulated output voltage of the regulator. This technique
offers extremely high ripple rejection and excellent line transient response.
A block diagram of the regulator circuit used in the
ILC7080/81 is shown in figure 2, which shows the input-tooutput isolation and the cascaded sequence of amplifiers
that implement the pole-zero scheme outlined above.
The ILC7080/81 were designed in a CMOS process with
some minor additions, which allow the circuit to be used at
input voltages up to 13V. The resulting circuit exceeds the
frequency response of traditional bipolar circuits. The
ILC7080/81 is very tolerant of output load conditions with
the inclusion of both short circuit and thermal overload protection. The device has a very low dropout voltage, typically a linear response of 1mV per milliamp of load current,
and none of the quasi-saturation characteristics of a bipolar
output device. All the good features of the frequency
response and regulation are valid right to the point where
the regulator goes out of regulation in a 4mV transition
region. Because there is no base drive, the regulator is
capable of providing high current surges while remaining in
regulation. This is shown in the high peak current of 500mA
which allows for the ILC7080/81 to be used in systems that
require short burst mode operation.
DOMINANT POLE
OUTPUT POLE
85 dB
COMPENSATING
ZERO
UNITY GAIN
FREQUENCY
GAIN
Figure 1: ILC7080/81 RF LDO frequency response
Operation
Page 6
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ILC7080/81 1.1
ON/OFF
GND
V
OUT
V
IN
C
NOISE
FEEDBACK
BANDGAP
REFERENCE
V
REF
ERROR
AMPLIFIER
TRANSCONDUCTANCE
AMPLIFIER
INTERNAL V
DD
Figure 2: ILC7080/81 RF LDO regulator block digram
Shutdown (ON/OFF) Operation
The ILC7080/81 output can be turned off by applying 0.4V
or less to the device’s ON/OFF pin (pin 3). In shutdown
mode, the ILC7080/81 draws less than 1mA quiescent current. The output of the ILC7081 is enabled by applying 2V
to 13V at the ON/OFF pin. In applications where the
ILC7080/81 output will always remain enabled, the ON/OFF
pin may be connected to V
IN
(pin 1). The ILC7080/81’s
shutdown circuitry includes hysteresis, as such the device
will operate properly even if a slow moving signal is applied
to the ON/OFF pin. The device’s shutdown pin includes a
2MΩ internal pull down resistor connected to ground.
Short Circuit Protection
The ILC7080/81 output can withstand momentary short circuit to ground. Moreover, the regulator can deliver very high
output peak current due to its 1A instantaneous short circuit
current capability.
Thermal Protection
The ILC7080/81 also includes a thermal protection circuit
which shuts down the regulator when die temperature
exceeds 170°C due to overheating. In thermal shutdown,
once the die temperature cools to below 160°C, the regulator is enabled. If the die temperature is excessive due to
high package power dissipation, the regulator’s thermal circuit will continue to pulse the regulator on and off. This is
called thermal cycling.
Excessively high die temperature may occur due to high differential voltage across the regulator or high load current or
high ambient temperature or a combination of all three.
Thermal protection protects the regulator from such fault
conditions and is a necessary requirement in today’s
designs. In normal operation, the die temperature should be
limited to under 150°C.
Adjustable Output Voltage
Figure 3 shows how an adjustable output voltage can be
easily achieved using ILC7080/81-ADJ. The output voltage,
V
OUT
is given by the following equation:
V
OUT
= 1.24V x (R1/R2 + 1)
For best results, a resistor value of 470kΩ or less may be
used for R2. The output voltage can be programmed from
2.5V to 12V.
Note: An external capacitor should not be connected to the
adjustable feedback pin (pin 4). Connecting an external capacitor
to pin 4 may cause regulator instability and lead to oscillations.
ILC7080-ADJ
ILC7081-ADJ
V
OUT
V
IN
C
OUT
SOT23-5
C
IN
R1 R2
ON
OFF
123
45
V
ADJ
Figure 3: Application circuit for adjustable output voltage
Page 7
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ILC7080/81 1.1
Maximum Output Current
The maximum output current available from the ILC7080/81
is limited by the maximum package power dissipation as
well as the device’s internal current limit. For a given ambient temperature, T
A
, the maximum package power dissipa-
tion is given by:
P
D(max)
= (T
J(max)
- TA) / θ
JA
where T
J(max)
= 150°C is the maximum junction temperature
and θ
JA
= 333°C/W is the package thermal resistance. For
example at T
A
= 85°C ambient temperature, the maximum
package power dissipation is;
P
D(max)
= 195mW.
The maximum output current can be calculated from the following equation:
I
OUT(max)
< P
D(max)
/ (VIN- V
OUT
)
For example at V
IN
= 6V, V
OUT
= 5V and TA= 85°C, the
maximum output current is I
OUT(max)
< 195mA. At higher
output current, the die temperature will rise and cause the
thermal protection circuit to be enabled.
APPLICATION HINTS
Figure 4 shows the typical application circuit for the
ILC7080/81.
Input Capacitor
An input capacitor C
IN
of value 1mF or larger should be con-
nected from V
IN
to the main ground plane. This will help to
filter supply noise from entering the LDO. The input capacitor should be connected as close to the LDO regulator
input pin as is practical. Using a high-value input capacitor
will offer superior line transient response as well as better
power supply ripple rejection. A ceramic or tantalum capacitor may be used at the input of the LDO regulator.
Note that there is a parasitic diode from the LDO regulator
output to the input. If the input voltage swings below the
regulator’s output voltage by a couple of hundred milivolts
then the regulator may be damaged. This condition must be
avoided. In many applications a large value input capacitor,
CIN, will hold VINhigher than V
OUT
and decay slower than
V
OUT
when the LDO is powered off.
Output Capacitor Selection
Impala strongly recommends the use of low ESR (equivalent series resistance) ceramic capacitors for C
OUT
and
C
NOISE
. The ILC7080/81 is stable with low ESR capacitor
(as low as zero Ω). The value of the output capacitor should
be 1µF or higher. Either ceramic chip or a tantalum capacitor may be used at the output.
Use of ceramic chip capacitors offer significant advantages
over tantalum capacitors. A ceramic capacitor is typically
considerably cheaper than a tantalum capacitor, it usually
has a smaller footprint, lower height, and lighter weight than
a tantalum capacitor. Furthermore, unlike tantalum capacitors which are polarized and can be damaged if connected
incorrectly, ceramic capacitors are non-polarized. Low
value ceramic chip capacitors with X7R dielectric are available in the 100pF to 4.7µF range, while high value capacitors with Y5V dielectric are available in the 2200pF to 22µF
range. Evaluate carefully before using capacitors with Y5V
dielectric because their ESR increases significantly at cold
temperatures. Figure 10 shows a list of recommended
ceramic capacitors for use at the output of ILC7080/81.
Note: If a tantalum output capacitor is used then for stable operation Impala recommends a low ESR tantalum capacitor with maximum rated ESR at or below 0.4Ω. Low ESR tantalum capacitors,
such as the TPS series from A VX Corporation (www.avxcorp.com)
or the T495 series from Kemet (www.kemet.com) may be used.
In applications where a high output surge current can be
expected, use a high value but low ESR output capacitor for
superior load transient response. The ILC7080/81 is stable
with no load.
Noise Bypass Capacitor
In low noise applications, the self noise of the ILC7080/81
can be decreased further by connecting a capacitor from
the noise bypass pin (pin 4) to ground (pin 2). The noise
bypass pin is a high impedance node as such, care should
be taken in printed circuit board layout to avoid noise pickup from external sources. Moreover, the noise bypass
capacitor should have low leakage.
Noise bypass capacitors with a value as low as 470pF
may be used. However, for optimum performance, use a
0.01µF or larger, ceramic chip capacitor. Note that the turn
on and turn off response of the ILC7080/81 is inversely
proportional to the value of the noise bypass capacitor.
For fast turn on and turn off, use a small value noise
bypass capacitor. In applications were exceptionally low
output noise is not required, consider omitting the noise
bypass capacitor altogether.
ILC7080
ILC7081
V
OUT
V
IN
C
OUT
C
NOISE
SOT23-5
123
45
ON
OFF
Figure 4: Basic application circuit for fixed output voltage versions
Page 8
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ILC7080/81 1.1
The Effects of ESR (Equivalent Series Resistance)
The ESR of a capacitor is a measure of the resistance due
to the leads and the internal connections of the component.
Typically measured in mΩ (milli-ohms) it can increase to
ohms in some cases.
Wherever there is a combination of resistance and current,
voltages will be present. The control functions of LDOs use
two voltages in order to maintain the output precisely; V
OUT
and V
REF
.
With reference to the block diagram in figure 2, V
OUT
is fed
back to the error amplifier and is used as the supply voltage for the internal components of the 7080/81. So any
change in V
OUT
will cause the error amplifier to try to com-
pensate to maintain V
OUT
at the set level and noise on
V
OUT
will be reflected into the supply of each internal cir-
cuit. The reference voltage, V
REF
, is influenced by the
C
NOISE
pin. Noise into this pin will add to the reference volt-
age and be fed through the circuit. These factors will not
cause a problem if some simple steps are taken. Figure 5
shows where these added ESR resistances are present in
the typical LDO circuit.
With this in mind low ESR components will offer better performance as LDOs may be exposed to large transients of
output voltage, and current flows through the capacitors in
order to filter these transient swings. ESR is less of a problem with C
IN
as the voltage fluctuations at the input will be
filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of
several currents can develop detectable voltage ripple and
will be amplified by the LDO. Particularly the accumulation
of current flows in the ground plane can develop significant
voltages unless care is taken.
With a degree of care, the ILC7080/81 will yield outstanding
performance.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full
advantage of any high performance LDO regulator requires
paying careful attention to grounding and printed circuit
board (PCB) layout.
Figure 7 shows the effects of poor grounding and PCB layout caused by the ESR and PCB resistances and the accumulation of current flows.
Note particularly that during high output load current, the
LDO regulator’s ground pin and the ground return for C
OUT
and C
NOISE
are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current
loop between C
OUT
, C
NOISE
and the LDO regulator’s ground
pin will degrade performance of the LDO.
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground current and noise bypass current return of the LDO regulator.
Note that the key difference here is that C
OUT
and C
NOISE
are directly connected to the LDO regulator’s ground pin.
The LDO is then separately connected to the main ground
plane and returned to a single point system ground.
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
V
OUT
V
IN
ILC7080
ILC7081
C
OUT
C
NOISE
SOT23-5
ON
OFF
R*
R
C
I
OUT
I
C
4
5
123
R*
C
IN
RF LDO
TM
Regulator
ILC7080
ILC7081
V
IN
C
OUT
C
NOISE
SOT23-5
ESR
R
PCB
I
2
V
OUT
I
OUT
R
PCB
ESR
I
1
R
PCB
R
PCB
4
5
123
V
IN
R
PCB
ON
OFF
5
4
3
21
LOAD
Figure 5: ESR in C
OUT
and C
NOISE
Figure 6: Inherent PCB resistance
Figure 7: Effects of poor circuit layout
Page 9
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ILC7080/81 1.1
45
1
23
Connect CINbetween VINof the ILC7080/81 and the
“GROUND PLANE”.
Keep the ground side of C
OUT
and C
NOISE
connected to
the “LOCAL GROUND” and not directly to the
“GROUND PLANE”.
On multilayer boards use component side copper for
grounding around the ILC7080/81 and connect back to a
“GROUND PLANE” using vias.
If using a DC-DC converter in your design, use a star
grounding system with separate traces for the power
ground and the control signals. The star should radiate
from where the power supply enters the PCB.
Place all RF LDO related components; ILC7080/81,
input capacitor CIN, noise bypass capacitor C
NOISE
and
output capacitor C
OUT
as close together as possible.
Keep the output capacitor C
OUT
as close to the
ILC7080/81 as possible with very short traces to the
V
OUT
and GND pins.
The traces for the related components; ILC7080/81,
input capacitor C
IN
, noise bypass capacitor C
NOISE
and
output capacitor C
OUT
can be run with minimum trace
widths close to the LDO.
Maintain a separate “LOCAL GROUND” remote from
the “GROUND PLANE” to ensure a quiet ground near
the LDO.
Figure 9 shows how this circuit can be translated into a
PCB layout.
Figure 8: Recommended application circuit schematic
Label
Part Number
Manufacturer
Description
U1
ILC7081AIM5-30
Impala Linear
100mA RF LDO™
J1
69190-405
Berg
Connector, four position header
CIN
GRM40 Y5V 105Z16
muRata
Ceramic capacitor, 1µF, 16V, SMT
(size 0805)
C
NOISE
ECU-V1H103KBV
Panasonic
Ceramic Capacitor, 0.01µF, 16V,
SMT (size 0603)
C
OUT
GRM42-
6X5R475K10
muRata
Ceramic Capacitor, 4.7µF, 16V, SMT
(size 1206)
Evaluation Board Parts List For Printed Circuit Board Shown Above
1.
2.
3.
4.
1.
2.
3.
4.
Grounding Recommendations Layout Considerations
Figure 9: Recommended application circuit layout
(not drawn to scale). Note: ground plane is bottom layer
of PCB and connects to top layer ground connections
through vias
Page 10
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Corporation
10
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
Recommended Ceramic Output Capacitors
C
OUT
Capacitor Size
I
OUT
Dielectric
Part Number
Capacitor Vendor
1µF
0805
0 to 100mA
X5R
C2012X5R1A105KT
TDK
1µF
0805
0 to 100mA
X7R
GRM40X7R105K010
muRata
1µF
0805
0 to 100mA
X7R
LMK212BJ105KG
Talyo-Yuden
1µF
1206
0 to 100mA
X7R
GRM42-6X7R105K016
muRata
1µF
1206
0 to 100mA
X7R
EMK316BJ105KL
Talyo-Yuden
1µF
1206
0 to 100mA
X5R
TMK316BJ105KL
Talyo-Yuden
2.2µF
0805
0 to 150mA
X5R
GRM40X5R225K 6.3
muRata
2.2µF
0805
0 to 150mA
X5R
C2012X5R0J225KT
TDK
2.2µF
1206
0 to 150mA
X5R
EMK316BJ225ML
Talyo-Yuden
4.7µF
1206
0 to 150mA
X5R
GRM42-6X5R475K010
muRata
4.7µF
1206
0 to 150mA
X7R
LMK316BJ475ML
Talyo-Yuden
Page 11
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Corporation
11
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
Output Vo ltage vs Temperature
3.015
3.01
3.005
3
2.995
2.99
Output voltage (V)
C
OUT
= 1µF (Ceram ic)
V
OUT
= 3.0V
2.985
Temperature (°C)
0 50 100 150-50
Dropout Characteristics
V
IN
(V)
3.4
3.3
3.2
3.1
3
V
OUT
(V)
C
OUT
= 1µF (Ceramic)
V
OUT
= 3.3V
3 3.2 3.4 3.6
I
OUT
= 0mA
I
OUT
= 10mA
I
OUT
= 50mA
I
OUT
= 100mA
I
OUT
= 150mA
Unless otherwise specified TA T=25°C, VIN=V
OUT(NOM)
, + 1V, ON/OFF pin tied to V
IN
Characterization at output currents above 50mA applies to ILC7081
TYPICAL PERFORMANCE CHARACTERISTICS
D rop ou t Volt a ge vs Temper a t u re
D ropout vo lta ge (mV)
T emperature (°C)
250
200
150
100
50
0
–40 8525
V
OUT
= 3.0V
I
OUT
= 150mA
I
OUT
= 100mA
I
OUT
= 50mA
I
OUT
= 0mA
150
125
100
75
50
2 4 6 8 10 12 14
Ground Current vs Input Voltage
V
OUT
= 3.0 V
C
OUT
= 1µF (Ceramic)
I
OUT
= 150mA
I
OUT
= 100mA
I
OUT
= 50mA
I
OUT
= 10mA
I
OUT
= 0mA
VIN (V)
I
GN D
(µA)
250
200
150
100
50
0
0 50 100 150
Dropout Voltage vs I
OU T
Dropout voltage (mV)
Output Current (mA)
T
A
= –40°C
T
A
= 85°C
T
A
= 25°C
V
OUT
= 3.0V
Lin e Trans ient Re spo nse
5µs/div
V
IN
(V)V
OUT
(V)
6
5
4
3.01
3.00
2.99
2.98
V
IN
: tr/t f < 1 µs
V
OUT
= 3.0V
C
OUT
= 2.2 µF (Ceramic)
I
OUT
= 100 mA
0.47µF (Ceramic)
7081 only
0.47µF (Ceramic)
0.47µF (Ceramic)
Dropout Characteristics
Line Transient Response
Page 12
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Corporation
12
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
Unless otherwise specified TA T=25°C, VIN=V
OUT(NOM)
, + 1V, ON/OFF pin tied to V
IN
Characterization at output currents above 50mA applies to ILC7081
TYPICAL PERFORMANCE CHARACTERISTICS
5µs/div
Page 13
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Corporation
13
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
Unless otherwise specified TA T=25°C, VIN=V
OUT(NOM)
, + 1V, ON/OFF pin tied to V
IN
Characterization at output currents above 50mA applies to ILC7081
TYPICAL PERFORMANCE CHARACTERISTICS
Page 14
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Corporation
14
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
Unless otherwise specified TA T=25°C, VIN=V
OUT(NOM)
, + 1V, ON/OFF pin tied to V
IN
Characterization at output currents above 50mA applies to ILC7081
TYPICAL PERFORMANCE CHARACTERISTICS
Page 15
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Corporation
15
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
Output voltage (V)
Grade
Order Information
*Package Marking
Supplied as:
2.85
A
ILC7080AIM5-285
CFXX
3k Units on Tape and Reel
3.0
A
ILC7080AIM5-30
CAXX
3k Units on Tape and Reel
3.3
A
ILC7080AIM5-33
CBXX
3k Units on Tape and Reel
3.6
A
ILC7080AIM5-36
CDXX
3k Units on Tape and Reel
5.0
A
ILC7080AIM5-50
CCXX
3k Units on Tape and Reel
ADJ
A
ILC7080AIM5-ADJ
CEXX
3k Units on Tape and Reel
*Note: First two characters i dentify the product and the last two characters identify t he dat e code.
Output voltage (V)
Grade
Order Information
*Package Marking
Supplied as:
2.85
A
ILC7081AIM5-285
CVXX
3k Units on Tape and Reel
3.0
A
ILC7081AIM5-30
CQXX
3k Units on Tape and Reel
3.3
A
ILC7081AIM5-33
CRXX
3k Units on Tape and Reel
3.6
A
ILC7081AIM5-36
CTXX
3k Units on Tape and Reel
4.7
A
ILC7081AIM5-47
CWXX
3k Units on Tape and Reel
5.0
A
ILC7081AIM5-50
CSXX
3k Units on Tape and Reel
ADJ
A
ILC7081AIM5-ADJ
CUXX
3k Units on Tape and Reel
*Note: First two characters i dentify the product and the last two characters identify t he date code.
SOT-23 Package Markings
ILC7080AIM5-xx
ILC7081AIM5-xx
Page 16
50/100mA SOT-23 CMOS RF LDO™ Regulators
Impala Linear Corporation
16
(408) 574-3939
www.impalalinear.com
Sept. 1998
ILC7080/81 1.1
Devices sold by Impala Linear Corporation are covered by the warranty and patent indemnification provisions appearing
in its Terms of Sale only. Impala Linear Corporation makes no warranty, express, statutory, implied, or by description
regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Impala Linear Corporation makes no warranty of merchantability or fitness for any purpose. Impala Linear Corporation
reserves the right to discontinue production and change specifications and prices at any time and without notice.
This product is intended for use in normal commercial applications. Applications requiring an extended temperature
range, unusual environmental requirements, or high reliability applications, such as military and aerospace, are specifically not recommended without additional processing by Impala Linear Corporation.
Impala Linear Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an
Impala Linear Corporation product. No other circuits, patents, licenses are implied.
Life Support Policy
Impala Linear Corporation’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Package Outline Dimensions
Dimensions shown in inches and (mm).
5-Lead plastic surface mount (SOT-23-5)
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