Datasheet ICS8737AG-11, ICS8737AG-11T Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

÷÷

1/

÷

÷÷

2

GENERAL DESCRIPTION

,&6

HiPerClockS™

inputs. The CLK, nCLK pair can accept most standard differ­ential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels.The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.

Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.

The ICS8737-11 is a low skew, high performance
Differential-to-3.3V LVPECL Clock Generator/
Divider and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8737-11 has two selectable clock

FEATURES

• 2 divide by 1 differential 3.3V L VPECL outputs;
2 divide by 2 differential 3.3V L VPECL outputs

• Selectable CLK, nCLK or LVPECL clock inputs

• CLK, nCLK pair can accept the following differential input

levels: L VDS, L VPECL, LVHSTL, SSTL, HCSL

• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL

• Maximum output frequency up to 650MHz

• Translates any single ended input signal (L VCMOS, L VTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

• Output skew: 60ps (maximum)

• Part-to-part skew: 200ps (maximum)

• Bank skew: Bank A - 20ps (maximum),

Bank B - 35ps (maximum)

• Propagation delay: 1.7ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM PIN ASSIGNMENT

CLK_EN

CLK
nCLK
PCLK

nPCLK

CLK_SEL

MR

QA0
nQA0

D

Q

LE

0
1

÷1
÷2

QA1
nQA1

QB0
nQB0

QB1
nQB1

VEE

CLK_EN

CLK_SEL

CLK
nCLK
PCLK

nPCLK

nc
MR
V

CC

ICS8737-11

20-Lead TSSOP

1
2
3
4
5
6
7
8
9
10

6.50mm x 4.40mm x 0.92 package body

G Package

T op View

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

1

20
19
18
17
16
15
14
13
12
11

QA0
nQA0
V

CC

QA1
nQA1
QB0
nQB0
V

CC

QB1
nQB1

Integrated
Circuit
Systems, Inc.

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

1V

2NE_KLCrewoPpulluP

3LES_KLCtupnInwodlluP
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN

5KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
6KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
7KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
8cndesunU.tcennocoN
9RMtupnInwodlluP.redividtuptuoehtsteseR.teserretsaM

81,31,01V
21,111BQ,1BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
51,410BQ,0BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
71,611AQ,1AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
02,910AQ,0AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

:ETON

EE

CC

pulluP

dna

rewoP.dnuorgottcennoC.nipylppusevitageN

rewoP.V3.3ottcennoC.snipylppusevitisoP

nwodlluP

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

.slevelecafretniSOMCVL/LTTVL

.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleSkcolC

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

÷

1/

÷÷

.tupnikcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS

2

.slevelecafretniSOMCVL/LTTVL.stupniKLCn,KLCstceles,WOLnehW

÷÷

.hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

C

NI

R

PULLUP

R

NWODLLUP

ecnaticapaCtupnI

KLCn,KLC 4Fp

KLCPn,KLCP 4Fp

,LES_KLC

RM,NE_KLC

rotsiseRpulluPtupnI 15K

rotsiseRnwodlluPtupnI 15K

4Fp

W
W

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

2

Integrated
Circuit
Systems, Inc.

ICS8737-11

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

TABLE 3A. CONTROL INPUT FUNCTION TABLE

stupnIstuptuO

RMNE_KLCLES_KLCecruoSdetceleS1AQurht0AQ1AQnurht0AQn1BQurht0BQ1BQnurht0BQn

1X X X WOLHGIHWOLHGIH
00 0 KLCn,KLCWOL;delbasiDHGIH;delbasiDWOL;delbasiDHGIH;delbasiD
00 1 KLCPn,KLCPWOL;delbasiDHGIH;delbasiDWOL;delbasiDHGIH;delbasiD
01 0 KLCn,KLCdelbanEdelbanEdelbanEdelbanE
01 1 KLCPn,KLCPdelbanEdelbanEdelbanEdelbanE

.1erugiFfinwohssa

.B3elbaTni

÷÷

÷÷

÷

÷

1/

÷÷

2

÷÷

egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA

debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQA0 - nQA1,

nQB0 - nQB1

QA0 - QA1,

QB0 - QB1

TABLE 3B. CLOCK INPUT FUNCTION TABLE

stupnIstuptuO

KLCProKLCKLCPnroKLCnxAQxAQnxBQxBQn

00WOLHGIHWOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
11HGIHWOLHGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN

1ETON;desaiB0HGIHWOLHGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHWOLHGIHlaitnereffiDotdednEelgniSgnitrevnI

.sleveldedneelgnistpecca

Disabled

Enabled

FIGURE 1: CLK_EN TIMING DIAGRAM

edoMtuptuOottupnIytiraloP

ottupnilaitnereffidgniriwsessucsidhcihw,9erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

3

Integrated
Circuit
Systems, Inc.

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

÷÷

1/

÷

÷÷

2

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

Inputs, V

I

Outputs, V

Package Thermal Impedance, θ

Storage T emperature, T

CC

O

JA

STG

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the

DC Characteristics

or

AC Characteristics

ods may affect product reliability .

4.6V

-0.5V to VCC + 0.5V

-0.5V to VCC + 0.5V

73.2°C/W (0lfpm)

-65°C to 150°C

is not implied. Exposure to absolute maximum rating conditions for extended peri-

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V

= 3.3V±5%, TA = 0°C TO 70°C

CC

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

CC

I

EE

egatloVylppuSevitisoP531.33.3564.3V

tnerruCylppuSrewoP 05Am

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

HI

V

LI

I

HI

I

LI

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

I

HI

I

LI

V

PP

V

RMC

2,1ETON

RM,LES_KLC,NE_KLC2567.3V
RM,LES_KLC,NE_KLC 3.0-8.0V

tnerruChgiHtupnI

tnerruCwoLtupnI

tnerruChgiHtupnI

tnerruCwoLtupnI

NE_KLCV

RM,LES_KLCV

NE_KLCV

RM,LES_KLCV

= 3.3V±5%, TA = 0°C TO 70°C

CC

KLCnV

KLCV

KLCnV

KLCV

NI

NI

NI

NI

egatloVtupnIkaeP-ot-kaeP 51.03.1V

;egatloVtupnIedoMnommoC

snoitacilppadedneelgnisroF:1ETON , VsiKLCn,KLCrofegatlovtupnimumixameht

siegatlovedomnommoC:2ETONVsadenifed

.

= 3.3V±5%, TA = 0°C TO 70°C

CC

V=

NI

CC

V=

NI

CC

V,V0=

NI

V,V0=

NI

V=

CC

V=

CC

V,V0=

CC

V,V0=

CC

V564.3=5Aµ
V564.3=051Aµ

CC

CC

V564.3=051-Aµ
V564.3=5-Aµ

V564.3=5Aµ
V564.3=051Aµ

V564.3=051-Aµ
V564.3=5-Aµ

V

5.0+V

EE

CC

.V3.0+

CC

58.0-V

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

4

Integrated
Circuit
Systems, Inc.

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

÷÷

1/

÷

÷÷

2

TABLE 4D. LVPECL DC CHARACTERISTICS, V

= 3.3V±5%, TA = 0°C TO 70°C

CC

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

I

HI

I

LI

V

PP

V

RMC

V

HO

V

LO

V

GNIWS

tnerruChgiHtupnI

tnerruCwoLtupnI

TABLE 5. AC CHARACTERISTICS, V

V=

NI

CC

V=

V

NI

CC

V

V

NI

V,V0=

NI

V,V0=

egatloVtupnIkaeP-ot-kaeP 3.01V

2,1ETON;egatloVtupnIedoMnommoCV

3ETON;egatloVhgiHtuptuOV

3ETON;egatloVwoLtuptuOV

gniwSegatloVtuptuOkaeP-ot-kaeP 56.09.0V

VsadenifedsiegatlovedomnommoC:1ETON

.

HI

05htiwdetanimretstuptuO:3ETON

W

Vot

= 3.3V±5%, TA = 0°C TO 70°C

CC

.V2-

V564.3=051Aµ
V564.3=5Aµ

CC

CC

V564.3=5-Aµ

V564.3=051-Aµ

5.1+V

EE

4.1-V

CC

0.2-V

CC

VsiKLCPn,KLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON

CC

.V3.0+

CC

0.1-V

CC

7.1-V

CC

V

V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

f

XAM

t

DP

t

)o(ks4,2ETON;wekStuptuO 06sp

t

)b(ks4ETON;wekSknaB

t

)pp(ks4,3ETON;wekStraP-ot-traP 002sp

t

R

t

F

emiTesiRtuptuOzHM05@%08ot%02003007sp

emiTllaFtuptuOzHM05@%08ot%02003007sp

ycneuqerFtuptuOmumixaM 056zHM

1ETON;yaleDnoitagaporP

KLCn,KLC

KLCPn,KLCP2.16.1

ƒ

£

zHM056

3.17.1sn

AknaB02sp
BknaB53

cdoelcyCytuDtuptuO 840525%

.esiwrehtodetonsselnuzHM005taderusaemsretemarapllA

.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcycehT

.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON

.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON

.stniopssorclaitnereffidtuptuoehttaderusaeM

segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON

derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna

.stniopssorclaitnereffidehtta

.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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Integrated
Circuit
Systems, Inc.

PARAMETER MEASUREMENT INFORMATION

V

CC

LVPECL

VCC = 2.0V

VEE = -1.3V ± 0.135V

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

SCOPE

Qx

nQx

÷÷

1/

÷

÷÷

2

nCLK, nPCLK

Qx

nQx

V

CLK, PCLK

V

FIGURE 2 - OUTPUT LOAD TEST CIRCUIT

CC

VPP

EE

FIGURE 3 - DIFFERENTIAL INPUT LEVEL

Cross Points

V

CMR

Qy

nQy

tsk(o)

FIGURE 4 - O UTPUT SKEW

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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Integrated
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Qx

PART 1

nQx

Qy

PART 2

nQy

ICS8737-11

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

tsk(pp)

FIGURE 5 - P ART-TO-PART SKEW

÷÷

÷

÷÷

1/

÷÷

÷

÷÷

2

Clock Inputs
and Outputs

CLK, PCLK

nCLK, nPCLK

Q0A0, Q0A1 -

Q0B0, Q0B1

nQ0A0, nQ0A1 -

nQ0B0, nQ0B1

80%

20%

t

R

t

F

FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME

t

PD

FIGURE 7 - PROPAGATION DELAY

80%

20%

V

SWING

CLK, PCLK

nCLK, nPCLK

Pulse Width

t

PERIOD

t

odc =

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

PW

t

PERIOD

FIGURE 8 - odc & t

7

PERIOD

Integrated
Circuit
Systems, Inc.

ICS8737-11

÷÷

LOW SKEW

÷

÷÷

1/

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

APPLICA TION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

÷÷

÷

÷÷

2

Figure 9

VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to
the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input
voltage swing. For example, if the input clock swing is only 12.5V and VCC = 3.3V , V_REF should be 1.25V and R2/
R1 = 0.609.

shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~

CLK_IN

C1

0.1uF

FIGURE 9 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

R1
1K

V_REF

R2
1K

VCC

+

-

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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Integrated
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ICS8737-11

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8737-11.
Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8737-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

= 3.3V + 5% = 3.465V , which gives worst case results.

CC

÷÷

÷

÷÷

1/

÷÷

÷

÷÷

2

• Power (core)

• Power (outputs)

If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW

Total Power

2. Junction T emperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS

The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature

θ

= junction-to-ambient thermal resistance

JA

Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T

= Ambient T emperature

A

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per T able 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).

MAX

= V

MAX

_MAX

* I

CC_MAX

= 30.2mW/Loaded Output pair

(3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW

= 3.465V * 50mA = 173.25mW

CC_MAX

* Pd_total + T

JA

TM

devices is 125°C.

A

must be used . Assuming a

JA

T able 6. Thermal Resistance

Single-Layer PCB, JEDEC Standard T est Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard T est Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

θθ

θJA for 20-pin TSSOP, Forced Convection

θθ

θθ

θ

by Velocity (Linear Feet per Minute)

θθ

JA

0 200 500

9

Integrated
Circuit
Systems, Inc.

3. Calculations and Equations.

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

÷÷

1/

÷

÷÷

2

LVPECL output driver circuit and termination are shown in

VCC

Q1

FIGURE 10 - LVPECL DRIVER CIRCUIT AND TERMINATION

Figure 10.

RL

50

V

CC

V

- 2V

OUT

T o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCC- 2V .

Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .

Pd_H = [(V
Pd_L = [(V

• For logic high, V
Using V

• For logic low, V
Using V

Pd_H = [(2.465V - (3.465V - 2V))/50 Ω] * (3.465V - 2.465V) = 20.0mW
Pd_L = [(1.765V - (3.465V - 2V))/50 Ω] * (3.465V - 1.765V) = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW

OH_MAX

OL_MAX

– (V

– (V

CC_MAX

CC_MAX

- 2V))/RL] * (V

CC_MAX

- 2V))/RL] * (V

CC_MAX

= V

OUT

OH_MAX

= 3.465, this results in V

= V

OUT

OL_MAX

= 3.465, this results in V

= V

= V

CC_MAX

CC_MAX

CC_MAX

CC_MAX

- V

- V

– 1.0V

OH_MAX

– 1.7V

OL_MAX

OH_MAX

OL_MAX

= 2.465V

= 1.765V

)

)

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

RELIABILITY INFORMATION

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

÷÷

1/

÷

÷÷

2

TABLE 7. θ

TRANSISTOR COUNT

The transistor count for ICS8737-11 is: 510

VS

. AIR FLOW TABLE

JA

θθ

θ

by Velocity (Linear Feet per Minute)

θθ

JA

0 200 500

Single-Layer PCB, JEDEC Standard T est Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard T est Boards 73.2°C/W 66.6°C/W 63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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PACKAGE OUTLINE - G SUFFIX

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

÷÷

1/

÷

÷÷

2

TABLE 8. PACKAGE DIMENSIONS

LOBMYS

N02

A--02.1

1A50.051.0

2A08.050.1
b91.003.0
c90.002.0

D04.606.6

ECISAB04.6

1E03.405.4
eCISAB56.0
L54.057.0

a

aaa--01.0

Reference Document: JEDEC Publication 95, MO-153

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

NIMXAM

°0 °8

12

sretemilliM

Integrated
Circuit
Systems, Inc.

TABLE 9. ORDERING INFORMATION

rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT

11-GA7378SCI11-GA7378SCIPOSSTdael0227C°07otC°0

T11-GA7378SCI11-GA7378SCIleeRdnaepaTnoPOSSTdael020052C°07otC°0

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

÷÷

1/

÷

÷÷

2

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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