allel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics
make the ICS8701I ideal for those clock distribution applications demanding well defined performance and repeatability.
erator and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS outputs are designed to drive 50W series or par-
FEATURES
• 20 LVCMOS outputs, 7W typical output impedance
• Output frequency up to 250MHz
• 200ps bank skew, 250ps output skew, 300ps multiple
frequency skew, 600ps part-to-part skew
• LVCMOS / LVTTL clock input
• LVCMOS control inputs
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
3
Page 4
Integrated
Circuit
Systems, Inc.
ICS8701I
LOW SKEW¸1, ¸2
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage4.6V
Inputs-0.5V to VDD + 0.5V
Outputs-0.5V to VDDO + 0.5V
Ambient Operating Temperature-40°C to 85°C
Storage Temperature-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of product at these condition or any conditions beyond
those listed in the
tions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
7
Page 8
Integrated
Circuit
Systems, Inc.
FIGURE 1A, 1B - TIMING DIAGRAMS
CLK
Qx, ÷1
Qx, ÷2
ICS8701I
LOW SKEW¸1, ¸2
CLOCK GENERATOR
FIGURE 1A - ACTIVE, ÷1, ÷2
nMR/OE
CLK
Qx, ÷1
Qx, ÷2
High ImpedanceActive
FIGURE 1B - RESETTO ACTIVE, ÷1, ÷2
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
8
Page 9
Integrated
Circuit
Systems, Inc.
FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
ICS8701I
LOW SKEW¸1, ¸2
CLOCK GENERATOR
nMR/OE,
BANK_ENx
BANK_ENx
Q
VDDO/2
3.3V
VOH
VDDO/2
VDDO/2
0V
tPHL
Q
tPLH
FIGURE 2A - PROPAGATION DELAYS
fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps
tPHZ
VOH - 300mV
tPLZ
tPZH
tPZL
VOL
Q
VOL + 300mV
FIGURE 2B - DISABLEAND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
9
Page 10
Integrated
Circuit
Systems, Inc.
ICS8701I
LOW SKEW¸1, ¸2
CLOCK GENERATOR
FIGURE 3A, 3B - SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with
equal load conditions.
CLK
Qx0
○○○○○○○○
VDDO/2VDDO/2
tsk(b)tsk(b)
Qx4
VDDO/2VDDO/2
FIGURE 3A - BANK SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with
equal load conditions.
CLK
QA0 - QA4
VDDO/2VDDO/2
tsk(o)tsk(o)
QB0 - QB4
QC0 - QC4
QD0 - QD4
VDDO/2VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
10
Page 11
Integrated
Circuit
Systems, Inc.
ICS8701I
LOW SKEW¸1, ¸2
CLOCK GENERATOR
FIGURE 3C, 3D - SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the
same temperature, supply voltages and with equal load conditions.
CLK
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
QD0 - QD4
in ÷1
VDDO/2VDDO/2
tsk(w)tsk(w)
VDDO/2VDDO/2
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
QD0 - QD4
in ÷2
FIGURE 3C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply
voltages and with equal load conditions.
CLK
VDDO/2VDDO/2
PART 1 QA0 - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
tsk(p)tsk(p)
VDDO/2VDDO/2
PART 2 QA0 - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
11
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Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
ICS8701I
LOW SKEW¸1, ¸2
CLOCK GENERATOR
D
D2
θ
ccc
48
1
2
3
E1
E
N
1225
1324
A
A2
C
A1
D1
37
36
b
TABLE 6. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ
LOBMYS
MUMINIMLANIMONMUMIXAM
N
A
1A
2A
b
c
50.051.0
53.104.154.1
71.022.072.0
90.002.0
D
1D
2D
E
1E
2E
e
L
q
54.006.057.0
°0°7
ccc
Reference Document: JEDEC Publication 95, MS-026
CCB
84
05.5
05.5
L
E2
e
SEATING
-CPLANE
c
SRETEMILLIMNISNOISNEMIDLLA
06.1
CISAB00.9
CISAB00.7
CISAB00.9
CISAB00.7
CISAB5.0
80.0
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
8701Iwww.icst.com/products/hiperclocks.htmlREV. A MARCH 16, 2001
13
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