Datasheet ICS8701CYI, ICS8701CYIT Datasheet (ICST)

Page 1
Integrated Circuit Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8701I is a low skew, ÷1, ÷2 Clock Gen-
,&6
HiPerClockS™
allel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre­quency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also con­trols the active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V in­put supply, and 2.5V output supply operating modes. Guar­anteed bank, output and part-to-part skew characteristics make the ICS8701I ideal for those clock distribution appli­cations demanding well defined performance and repeat­ability.
erator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS out­puts are designed to drive 50W series or par-
FEATURES
• 20 LVCMOS outputs, 7W typical output impedance
• Output frequency up to 250MHz
• 200ps bank skew, 250ps output skew, 300ps multiple frequency skew, 600ps part-to-part skew
• LVCMOS / LVTTL clock input
• LVCMOS control inputs
• Bank enable logic allows unused banks to be disabled in reduced fanout applications
• 3.3V or mixed 3.3V input, 2.5V output operating supply modes
• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch
• -40°C to 85°C ambient operating temperature
• Other divide values available on request
BLOCK DIAGRAM PIN ASSIGNMENT
GND
LVCMOS_CLK
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE BANK_EN0 BANK_EN1
¸
1
¸
2
1
0
1
0
1
0
1
0
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
Bank Enable
Logic
QC3
VDDO
QC4 QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
GND
48 47 46 45 44 43 42 41 40 39 38 37
1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
DIV_SELD
QC1
QC2
ICS8701I
VDDI
nMR/OE
DIV_SELC
48-Pin LQFP
QC0
QB4
BANK_EN0
GND
VDDO
VDDI
VDDO
BANK_EN1
Y Package
Top View
GND
QB2
QB3
DIV_SELB
LVCMOS_CLK
GND
GND
36 35 34 33 32 31 30 29 28 27 26 25
DIV_SELA
QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0
8701I www.icst.com/products/hiperclocks.html REV. A MARCH 16, 2001
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Integrated Circuit Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,5,2
,62,11 ,53,23
44,14
,81,9,7
,03,82,12 ,64,93,73
84
02,61IDDVrewoP.V3.3ottcennoC.ylppusrewoptupnI
,72,52
,92
33,13
,63,43
,83
24,04
,54,34
,74
3,1
,6,4
,8
21,01
22KLC_SOMCVLtupnInwodlluP.slevelecafretniSOMCVL.tupnikcolC 31DLES_VIDtupnIpulluP
41CLES_VIDtupnIpulluP
32BLES_VIDtupnIpulluP
42ALES_VIDtupnIpulluP
91,71
51EO/RMntupnIpulluP
ODDVrewoP.V5.2roV3.3ottcennoC.ylppusrewoptuptuO
DNGrewoP.dnuorgottcennoC.dnuorG
,1AQ,0AQ
,2AQ
4AQ,3AQ
,1BQ,0BQ
,2BQ
4BQ,3BQ
,1CQ,0CQ
,2CQ
4CQ,3CQ
,1DQ,0DQ
,2DQ
4DQ,3DQ
,1NE_KNAB
0NE_KNAB
tuptuO
tuptuO
tuptuO
tuptuO
tupnIpulluP .slevelecafretniSOMCVL.sknabybstuptuoselbasiddnaselbanE
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
.slevelecafretniSOMCVL.stuptuoAknaB
7
W
7
W
7
W
7
W
.ecnadepmituptuolacipyt
.slevelecafretniSOMCVL.stuptuoBknaB
.ecnadepmituptuolacipyt
.slevelecafretniSOMCVL.stuptuoCknaB
.ecnadepmituptuolacipyt
slevelecafretniSOMCVL.stuptuoDknaB
.ecnadepmituptuolacipyt
.stuptuoDknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuoCknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuoBknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuoAknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuollaselbasiddnaselbanE.elbanetuptuodnateserretsaM
.slevelecafretniSOMCVL
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Integrated Circuit Systems, Inc.
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
KLC_SOMCVL Fp
NIC
PULLUPRrotsiseRpulluPtupnI 15K
NWODLLUPRrotsiseRnwodlluPtupnI 15K
DPCecnaticapaCnoitapissiDrewoP
TUORecnadepmItuptuO 7
tupnI
ecnaticapaC
,1NE_KNAB
)tuptuorep(
TABLE 3. FUNCTION TABLE
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
,EO/RMN,0NE_KNAB
=ODDV,IDDV
V564.3
,V564.3=IDDV
V526.2=ODDV
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
W W
Fp
Fp
W
stupnIstuptuO
EO/RMn1NE_KNAB0NE_KNABxLES_VID4AQ-0AQ4BQ-0BQ4CQ-0CQ4DQ-0DQ
0X XX ZiHZiHZiHZiHorez 10 0 0 evitcAZiHZiHZiH2/NIf 11 00 evitcAevitcAZiHZiH2/NIf 10 10 evitcAevitcAevitcAZiH2/NIf 11 10 evitcAevitcAevitcAevitcA2/NIf 10 0 1 evitcAZiHZiHZiHNIf 11 0 1 evitcAevitcAZiHZiHNIf 10 1 1 evitcAevitcAevitcAZiHNIf 11 11 evitcAevitcAevitcAevitcANIf
xQ
ycneuqerf
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Integrated Circuit Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 4.6V Inputs -0.5V to VDD + 0.5V Outputs -0.5V to VDDO + 0.5V Ambient Operating Temperature -40°C to 85°C Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the tions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V ODDVegatloVylppuSrewoPtuptuO 531.33.3564.3V
DDItnerruCylppuSrewoPtnecseiuQ
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating condi-
V564.3=HIV=IDDV
V0=LIV
001Am
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
,BLES_VID,ALES_VID
HIV
LIV
HII
LII
HOVegatloVhgiHtuptuO
LOVegatloVwoLtuptuO
tupnI
egatloVhgiH
tupnI
egatloVwoL
tupnI
tnerruChgiH
tupnI
tnerruCwoL
,0NE_KNAB
KLC_SOMCVLV564.3=IDDV28.3V
,0NE_KNAB
KLC_SOMCVLV564.3=IDDV3.0-3.1V
,0NE_KNAB
KLC_SOMCVLV564.3=NIV=IDDV051Aµ
,0NE_KNAB
KLC_SOMCVLV0=NIV,V564.3=IDDV5-Aµ
,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
V564.3=IDDV28.3V
V564.3=IDDV3.0-8.0V
V564.3=NIV=IDDV5Aµ
V0=NIV,V564.3=IDDV051-Aµ
V531.3=ODDV=IDDV
Am63-=HOI
V531.3=ODDV=IDDV
Am63=LOI
6.2V
5.0V
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Integrated Circuit Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
XAMfycneuqerFtupnImumixaM 052zHM
HLpt
LHpt
)b(kst2ETON;wekSknaB2/ODDVtaegdegnisirnoderusaeM002sp )o(kst3ETON;wekStuptuO2/ODDVtaegdegnisirnoderusaeM052sp
(kstw)
)pp(kst5ETON;wekStraPottraP2/ODDVtaegdegnisirnoderusaeM006sp Rt6ETON;emiTesiRtuptuO%07ot%03002009sp Ft6ETON;emiTllaFtuptuO%07ot%03002009sp
WPthtdiWesluPtuptuO
NEt
SIDt
woL-ot-hgiH
4ETON
6ETON
6ETON
,yaleDnoitagaporP
hgiH-ot-woL
,yaleDnoitagaporP
;wekSycneuqerFelpitluM
;emiTelbanEtuptuO
;emiTelbasiDtuptuO
.snoitidnocdaollauqedna .snoitidnocdaollauqehtiw
ZHM0
ZHM0
ZHM0
£f£
£f£
£f£
zHM0022.26.3sn
zHM0022.26.3sn
2/ODDVtaegdegnisirnoderusaeM003sp
zHM002
zHM002=f9.15.21.3sn
zHM01=f6sn
zHM01=f6sn
2/ELCYCt
6.0-
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:6ETON
2/ELCYCt
05htiwdetanimretstuptuollA.esiwrehtodetonsselnuzHM002taderusaemsretemarapllA:1ETON
W
2/ELCYCt
6.0+
.2/ODDVot .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETON .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofosknabssorcawekssadenifeD:3ETON
segatlovylppusemasehthtiwycneuqerftnereffidtagnitarepostuptuofosknabssorcawekssadenifeD:4ETON
dnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuotnereffidtaweksehtsadenifeD:5ETON
sn
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Integrated Circuit Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V ODDVegatloVylppuSrewoPtuptuO 573.25.2526.2V
DDItnerruCylppuSrewoPtnecseiuQ
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID ,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
HIV
LIV
HII
LII
HOVegatloVhgiHtuptuO
LOVegatloVwoLtuptuO
tupnI
egatloVhgiH
tupnI
egatloVwoL
tupnI
tnerruChgiH
tupnI
tnerruCwoL
,0NE_KNAB
KLC_SOMCVLV564.3=IDDV28.3V
,0NE_KNAB
KLC_SOMCVLV564.3=IDDV3.0-3.1V
,0NE_KNAB
KLC_SOMCVLV564.3=NIV051Aµ
,0NE_KNAB
KLC_SOMCVLV0=NIV5-Aµ
V564.3=HIV=IDDV
V0=LIV
V564.3=IDDV28.3V
V564.3=IDDV3.0-8.0V
V564.3=NIV5Aµ
V0=NIV051-Aµ
,V531.3=IDDV
V573.2=ODDV
Am72-=HOI
,V531.3=IDDV
V573.2=ODDV
Am72=HOI
8.1V
001Am
5.0V
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Integrated Circuit Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
XAMfycneuqerFtupnImumixaM 052zHM
HLpt
LHpt
)b(kst2ETON;wekSknaB2/ODDVtaegdegnisirnoderusaeM522sp )o(kst3ETON;wekStuptuO2/ODDVtaegdegnisirnoderusaeM052sp
(kstw)
)pp(kst5ETON;wekStraPottraP2/ODDVtaegdegnisirnoderusaeM056sp Rt6ETON;emiTesiRtuptuO%07ot%03002009sp Ft6ETON;emiTllaFtuptuO%07ot%03002009sp
WPthtdiWesluPtuptuO
NEt
SIDt
hgiH-ot-woL
woL-ot-hgiH
4ETON
6ETON
6ETON
,yaleDnoitagaporP
,yaleDnoitagaporP
;wekSycneuqerFelpitluM
;emiTelbanEtuptuO
;emiTelbasiDtuptuO
.snoitidnocdaollauqedna
.snoitidnocdaollauqehtiw
ZHM0
ZHM0
ZHM0
£f£
£f£
£f£
zHM0024.27.3sn
zHM0024.27.3sn
2/ODDVtaegdegnisirnoderusaeM003sp
zHM002
zHM002=f9.15.21.3sn
zHM01=f6sn
zHM01=f6sn
2/ELCYCt
6.0-
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:6ETON
2/ELCYCt
05htiwdetanimretstuptuollA.esiwrehtodetonsselnuzHM002taderusaemsretemarapllA:1ETON
W
2/ELCYCt
6.0+
.2/ODDVot .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETON .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofosknabssorcawekssadenifeD:3ETON
segatlovylppusemasehthtiwycneuqerftnereffidtagnitarepostuptuofosknabssorcawekssadenifeD:4ETON
dnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuotnereffidtaweksehtsadenifeD:5ETON
sn
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Integrated Circuit Systems, Inc.
FIGURE 1A, 1B - TIMING DIAGRAMS
CLK
Qx, ÷1
Qx, ÷2
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 1A - ACTIVE, ÷1, ÷2
nMR/OE
CLK
Qx, ÷1
Qx, ÷2
High Impedance Active
FIGURE 1B - RESET TO ACTIVE, ÷1, ÷2
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FIGURE 2A, 2B - TIMING WAVEFORMS
CLK
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
nMR/OE,
BANK_ENx
BANK_ENx
Q
VDDO/2
3.3V
VOH
VDDO/2
VDDO/2
0V
tPHL
Q
tPLH
FIGURE 2A - PROPAGATION DELAYS
fin = 200MHz, Vamp = 3.3V, tr = tf = 600ps
tPHZ
VOH - 300mV
tPLZ
tPZH
tPZL
VOL
Q
VOL + 300mV
FIGURE 2B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
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Integrated Circuit Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 3A, 3B - SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with
equal load conditions.
CLK
Qx0
○○○○○○○○
VDDO/2 VDDO/2
tsk(b) tsk(b)
Qx4
VDDO/2 VDDO/2
FIGURE 3A - BANK SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
QA0 - QA4
VDDO/2 VDDO/2
tsk(o) tsk(o)
QB0 - QB4 QC0 - QC4 QD0 - QD4
VDDO/2 VDDO/2
FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
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Integrated Circuit Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 3C, 3D - SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the
same temperature, supply voltages and with equal load conditions.
CLK
QA0 - QA4, QB0 - QB4, QC0 - QC4,
or
QD0 - QD4
in ÷1
VDDO/2 VDDO/2
tsk(w) tsk(w)
VDDO/2 VDDO/2
QA0 - QA4, QB0 - QB4, QC0 - QC4,
or
QD0 - QD4
in ÷2
FIGURE 3C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply voltages and with equal load conditions.
CLK
VDDO/2 VDDO/2
PART 1 QA0 - QA4
QB0 - QB4 QC0 - QC4 QD0 - QD4
tsk(p) tsk(p)
VDDO/2 VDDO/2
PART 2 QA0 - QA4
QB0 - QB4 QC0 - QC4 QD0 - QD4
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FIGURE 3B - OUTPUT SKEW
fin = 200MHz, Vamp = 3.3V, tr = tf = 200ps
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Integrated Circuit Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
D
D2
θ
ccc
48
1 2 3
E1
E
N
12 25
13 24
A
A2
C
A1
D1
37
36
b
TABLE 6. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ
LOBMYS
MUMINIMLANIMONMUMIXAM
N A
1A
2A b c
50.051.0
53.104.154.1
71.022.072.0
90.002.0
D
1D
2D
E
1E
2E e L
q
54.006.057.0
°0 °7
ccc
Reference Document: JEDEC Publication 95, MS-026
CCB
84
05.5
05.5
L
E2
e
SEATING
-C­PLANE
c
SRETEMILLIMNISNOISNEMIDLLA
06.1
CISAB00.9 CISAB00.7
CISAB00.9 CISAB00.7
CISAB5.0
80.0
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Integrated Circuit Systems, Inc.
TABLE 7. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
IYC1078SCIIYC1078SCIPFQLdaeL84yartrep052C°58otC°04- TIYC1078SCIIYC1078SCIleeRdnaepaTnoPFQLdaeL840002C°58otC°04-
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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