able single ended clock or crystal inputs. The single ended
clock input accepts LVCMOS or LVTTL input levels and
translate them to 3.3V LVPECL levels. The output enable is
internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-11 ideal for those applications demanding well defined performance and repeatability.
The ICS8535-11 is a low skew , high performance
1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
LVPECL fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8535-11 has select-
FEATURES
• 4 differential 3.3V LVPECL outputs
• Selectable CLK or crystal inputs
• CLK can accept the following input levels: LVCMOS, L VTTL
• Maximum output frequency up to 266MHz
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial T emperature information available upon request
BLOCK DIAGRAMPIN ASSIGNMENT
CLK_EN
CLK
XTAL1
XTAL2
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
6.5mm x 4.4mm x 0.92mm Package Body
V
EE
CLK_EN
CLK_SEL
CLK
nc
XTAL1
XTAL2
nc
nc
V
CC
ICS8535-11
20-Lead TSSOP
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
G Package
Top View
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
3
Page 4
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
ICS8535-11
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage T emperature, T
CCx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
ods may affect product reliability.
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for extended peri-
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
5
Page 6
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
V
CC
LVPECL
VCC = 2V
ICS8535-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
SCOPE
Qx
nQx
VEE = -1.3V ± 0.135V
Qx
nQx
Qy
nQy
FIGURE 2 - CHARACTERIZATION TEST CIRCUIT
tsk(o)
FIGURE 3 - OUTPUT SKEW
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
6
Page 7
Integrated
Circuit
Systems, Inc.
ICS8535-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V L VPECL FANOUT BUFFER
Clock Inputs
and Outputs
CLK
Q0 - Q3
nQ0 - nQ3
80%
20%
t
R
t
F
FIGURE 4 - INPUTAND OUTPUT RISING/FALL TIME
t
PD
80%
20%
V
SWING
CLK, Qx
nCLK, nQx
FIGURE 5 - PROPAGATION DELAY
Pulse Width
t
PERIOD
t
t
PERIOD
PW
odc =
FIGURE 6 - odc & t
PERIOD
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
7
Page 8
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
ICS8535-11
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
CR YSTA L OSCILLA TOR CIRCUIT FREQUENCY FINE TUNING
A crystal can be characterized for either series or parallel mode operation. The ICS8535-11 and ICS8533-11 fanout buf fers have
built-in crystal oscillator circuits that can accept either a series or parallel crystal without additional components. The frequency
accuracy provided by this configuration is sufficient for most computer applications.
For applications requiring highly accurate clock frequencies, the output frequency can be fine tuned by inserting a small series
capacitor C1 at the XT AL1 input (Pin 6 for ICS8535-11) as shown in
parallel or series crystal. The C1 value depends on the crystal type, frequency and the board layout. The parallel crystal fine tuning
results in smaller ppm and better performance. It is difficult to provide the precise value of C1. This section provides recommended
series capacitor C1 values to start with. This example uses 18pF parallel crystals.
Figure 7.
This fine tuning approach can be applied in either
Figure 7
about 33pF .
Figure 8
figure, a 24pF, 33pF and 43pF series capacitor is used to achieve the lowest ppm error for 19.44MHz, 16.666MHz and 15MHz
respectively.
Figure 9
shows the suggested series capacitor value for a parallel crystal. For a 16.666 MHz crystal, the recommended C1 value is
shows frequency accuracy versus series capacitance for 19.44MHz, 16.666MHz and 15MHz crystals. As seen from this
shows the experiment results of crystal oscillator frequency drift due to temperature variation.
U1
XTAL2
X1
C1
XTAL1
FIGURE 7 - CRYSTAL INTERFACEWITH SERIES CAPACITOR C1.
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
8
Page 9
Integrated
)
y
y
)
Circuit
Systems, Inc.
60
14.318
50
ICS8535-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V L VPECL FANOUT BUFFER
40
30
20
Series Capacitor, C1 (pF
10
0
141516171819202122232425
15.000
16.666
Crystal Frequency (MHz)
19.440
20.000
FIGURE 8 - SUGGESTED SERIES CAPACITOR C1 FOR PARALLEL CRYSTAL
100
80
60
(ppm
40
20
0
Accurac
0 102030405060
-20
-40
-60
Frequenc
-80
-100
Series Capacitor, C1 (pF)
24.000
19.44MHz
16.666MHz
15.00MHz
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
FIGURE 9 - FREQUENCY ACCURACYFOR PARALLEL CRYSTAL USING SERIES CAPACITOR C1
9
Page 10
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
ICS8535-11
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
= 3.3V + 5% = 3.465V , which gives worst case results.
CC
•Power (core)
•Power (outputs)
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
T otal Power
MAX
= V
MAX
_MAX
* I
CC_MAX
= 30.2mW/Loaded Output pair
= 3.465V * 50mA = 173.25mW
EE_MAX
(3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature
θ
= junction-to-ambient thermal resistance
JA
Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T
= Ambient T emperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per T able 7 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
* Pd_total + T
JA
A
TM
devices is 125°C.
must be used . Assuming a
JA
T able 7. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
q
by V elocity (Linear Feet per Minute)
JA
0200500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W98.0°C/W88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards73.2°C/W66.6°C/W63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
10
Page 11
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V L VPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
ICS8535-11
LVPECL output driver circuit and termination are shown in
Figure 10.
VCC
Q1
V
OUT
RL
50
V
- 2V
CC
FIGURE 10 - LVPECL DRIVER CIRCUITAND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8535AG-11www.icst.com/products/hiperclocks.htmlREV. B JULY 27, 2001
14
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