Page 1
Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
,&6
HiPerClockS™
the single ended clock input accepts L VCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-01 ideal for those applications demanding well defined performance and repeatability.
The ICS8535-01 is a low skew, high performance
1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8535-01 has two single ended clock inputs.
FEATURES
• 4 differential 3.3V L VPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
• CLK0 or CLK1 can accept the following differential input
levels: LVCMOS or L VTTL
• Maximum output frequency up to 266MHz
• Translates L VCMOS and LVTTL levels to 3.3V
L VPECL levels
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.9ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
CLK_EN
CLK0
CLK1
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
4.4mm x 6.5mm x 0.92mm body package
VEE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
CC
ICS8535-01
20-Lead TSSOP
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
G Package
T op View
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
1
Page 2
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
2NE_KLCtupnIpulluP
3LES_KLCtupnInwodlluP
40KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
61KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
9,8,7,5cndesunU.tcennocoN
81,31,01V
21,113Q,3QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
51,412Q,2QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
71,611Q,1QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
02,910Q,0QntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
pulluP
:ETON
EE
CC
dna
nwodlluP
rewoP.dnuorgottcennoC.nipylppusevitageN
rewoP.V3.3ottcecnnoC.snipylppusevitisoP
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
kcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
.hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniLTTVL/SOMCVL
.tupni1KLCstceles,HGIHnehW.tupnitceleskcolC
.slevelecafretniLTTVL/SOMCVL.tupni0KLCstceles,WOLnehW
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
R
PULLUP
R
NWODLLUP
1KLC,0KLC4Fp
ecnaticapaCtupnI
rotsiseRpulluPtupnI 15KΩ
,NE_KLC
LES_KLC
rotsiseRnwodlluPtupnI 15KΩ
4Fp
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
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Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS3Qurht0Q3Qnurht0Qn
00 0KLCWOL;delbasiDHGIH;delbasiD
01 1KLCWOL;delbasiDHGIH;delbasiD
10 0KLCdelbanEdelbanE
11 1KLCdelbanEdelbanE
.1erugiFniwohssa
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
.B3elbaTnidebircsedsastupni1KLCdna0KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
CLK0, CLK1
CLK_EN
nQ0 - nQ3
Q0 - Q3
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
1KLCro0KLC3Qurht0Q3Qnurht0Qn
0WOLHGIH
1HGIHWOL
EnabledDisabled
FIGURE 1 - CLK_EN TIMING DIAGRAM
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
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Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage Temperature, T
CCx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Characteristics
extended periods may affect product reliability.
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
73.2°C/W (no airflow)
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
= 3.3V±5%, TA = 0°C TO 70°C
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
I
EE
egatloVylppuSevitisoP531.33.3564.3V
tnerruCylppuSrewoP 05Am
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
1KLC,0KLC2567.3V
V
HI
V
LI
I
HI
I
LI
egatloVhgiHtupnI
,NE_KLC
LES_KLC
1KLC,0KLC3.0-3.1V
egatloVwoLtupnI
,NE_KLC
LES_KLC
,1KLC,0KLC
tnerruChgiHtupnI
LES_KLC
NE_KLCV
,1KLC,0KLC
tnerruCwoLtupnI
LES_KLC
V
NE_KLCV
= 3.3V±5%, TA = 0°C TO 70°C
CC
V
V=
NI
CC
V=
NI
CC
V,V0=
NI
V,V0=
NI
V564.3=051Aµ
V564.3=5Aµ
CC
CC
V564.3=5-Aµ
V564.3=051-Aµ
2567.3V
3.0-8.0V
TABLE 4C. L VPECL DC CHARACTERISTICS, V
= 3.3V±5%, TA = 0°C TO 70°C
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
V
LO
V
GNIWS
05htiwdetanimretstuptuO:1ETON Ω Vot
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
1ETON;egatloVhgiHtuptuOV
1ETON;egatloVwoLtuptuOV
gniwSegatloVtuptuOkaeP-ot-kaeP6.058.0V
.V2-
CC
4
4.1-V
CC
0.2-V
CC
0.1-V
CC
7.1-V
CC
Page 5
Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
t
DP
t
)o(ks4,2ETON;wekStuptuO 1103sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 051sp
t
R
t
F
cdoelcyCytuDtuptuO840525%
emiTesiRtuptuOzHM05@%08ot%02003007sp
emiTllaFtuptuOzHM05@%08ot%02003007sp
= 3.3V±5%, TA = 0°C TO 70°C
CC
ycneuqerFtuptuOmumixaM 662zHM
1ETON;yaleDnoitagaporP IJ zHM6620.19.1sn
.stniopssorclaitnereffidtuptuoehttaderusaeM
.stniopssorclaitnereffidehtta
.esiwrehtodetonsselnuzHM662taderusaemsretemarapllA
.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcycehT
.tniopgnissorctuptuolaitnereffidehtottupniehtfotniop%05ehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisuU.snoitidnocdaollauqehtiwdna
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
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Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
V
CC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
Qx
nQx
Qy
nQy
V
-1.3V ± 0.135V
EE =
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
tsk(o)
FIGURE 3 - OUTPUT SKEW
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
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Integrated
Circuit
Systems, Inc.
Qx
PART 1
nQx
Qy
PART 2
nQy
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
Clock Inputs
and Outputs
CLK0, CLK1
Q0 - Q3
nQ0 - nQ3
80%
20%
t
R
t
F
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
t
PD
FIGURE 6 - PROPAGATION DELAY
80%
20%
V
SWING
CLK0, CLK 1, Qx
nQx
Pulse Width
t
PERIOD
t
odc =
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
PW
t
PERIOD
FIGURE 7 - odc & t
7
PERIOD
Page 8
Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
= 3.3V + 5% = 3.465V , which gives worst case results.
CC
• Power (core)
• Power (outputs)
If all outputs are loaded, the total power is 4 x 30.2mW = 120.8mW
Total Power
MAX
= V
MAX
_MAX
* I
CC_MAX
= 30.2mW/Loaded Output pair
= 3.465V * 50mA = 173.25mW
EE_MAX
(3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
The equation for Tj is as follows: Tj = θ
Tj = Junction Temperature
θ
= junction-to-ambient thermal resistance
JA
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
= Ambient T emperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
* Pd_total + T
JA
A
TM
devices is 125°C.
must be used . Assuming a
JA
Table 6. Thermal Resistance
qJA for 20-pin TSSOP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
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Integrated
Circuit
Systems, Inc.
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
ICS8535-01
LOW SKEW, 1-TO-4
LVPECL output driver circuit and termination are shown in
VCC
Figure 8.
Q1
V
OUT
RL
50
V
- 2V
CC
FIGURE 8 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
CC
- 2V .
Pd_H = [(V
Pd_L = [(V
• For logic high, V
Using V
• For logic low, V
Using V
OH_MAX
OL_MAX
– (V
– (V
CC_MAX
CC_MAX
- 2V))/RL]*(V
CC_MAX
- 2V))/RL]*(V
CC_MAX
= V
OUT
OH_MAX
= 3.465, this results in V
= V
OUT
OL_MAX
= 3.465, this results in V
= V
= V
CC_MAX
CC_MAX
CC_MAX
CC_MAX
- V
- V
OL_MAX
– 1.0V
OH_MAX
– 1.7V
OL_MAX
OH_MAX
)
)
= 2.465V
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50 Ω]*(3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50 Ω]*(3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
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Page 10
Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θ
TRANSISTOR COUNT
The transistor count for ICS8535-01 is: 412
VS
. AIR FLOW TABLE
JA
qJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
0 200 500
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
10
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Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
TABLE 8. PACKAGE DIMENSIONS
LOBMYS
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α
aaa--01.0
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
NIMXAM
°0 °8
11
sretemilliM
Page 12
<
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
10-GA5358SCI10-GA5358SCIPOSSTdael02ebutrep27C°07otC°0
T10-GA5358SCI10-GA5358SCIleeRdnaepaTnoPOSSTdael020052C°07otC°0
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
ICS8535AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 5, 2001
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