Page 1
Integrated
Circuit
Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
,&6
HiPerClockS™
able differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8533-11 ideal for those applications demanding well defined performance and repeatability.
The ICS8533-11 is a low skew , high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V
LVPECL fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8533-1 1 has select-
FEATURES
• 4 differential 3.3V LVPECL outputs
• Selectable CLK, nCLK or crystal inputs
• CLK, nCLK pair can accept the following differential input
levels: L VDS, L VPECL, L VHSTL, SSTL, HCSL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 3.3V
L VPECL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
CLK_EN
CLK
nCLK
XTAL1
XTAL2
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
6.5mm x 4.4mm x 0.92 Package Body
VEE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
nc
V
CC
ICS8533-11
20-Lead TSSOP
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
G Package
Top View
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
1
Page 2
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
2NE_KLCtupnIpulluP
3LES_KLCtupnInwodlluP
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
5KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
61LATXtupnInwodlluP.tupnirotallicsolatsyrC
72LATXtupnIpulluP.tupnirotallicsolatsyrC
9,8cndesunU.tcennocoN
81,31,01V
21,113Q,3QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD
51,412Q,2QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD
71,611Q,1QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD
02,910Q,0QntuptuO.slevelecafretniLCEPVL.stuptuokcolclaitnereffiD
pulluP
:ETON
EE
CC
dna
nwodlluP
rewoP.dnuorgottcennoC.nipylppusevitageN
rewoP.V3.3ottcennoC.snipylppusevitisoP
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
kcolcswollofstuptuokcolc,HGIHnehW.elbanekcolcgninorhcnyS
decroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniLTTVL/SOMCVL.hgih
.tupniKLCn,KLCstceles,WOLnehW.tupnitceleskcolC
.slevelecafretniLTTVL/SOMCVL.tupniLATXstceles,HGIHnehW
.seulavlacipytrof,scitsiretcarahcniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
R
PULLUP
R
NWODLLUP
ecnaticapaCtupnI
rotsiseRpulluPtupnI 15KΩ
rotsiseRnwodlluPtupnI 15KΩ
KLCn,KLC4Fp
LES_KLC,NE_KLC4Fp
REV. D JULY 16, 2001
2
Page 3
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS3Qurht0Q3Qnurht0Qn
00 KLCn,KLCWOL;delbasiDHGIH;delbasiD
01 2LATX,1LATXWOL;delbasiDHGIH;delbasiD
10 KLCn,KLCdelbanEdelbanE
11 2LATX,1LATXdelbanEdelbanE
ninwohssaegderotallicsolatsyrc
.B3elbaTni
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
rokcolctupnignillafdnagnisiragniwolofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
1erugiF
.
debircsedsastupni2LATX,1LATXdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
nCLK
Disabled
CLK
CLK_EN
nQ0 - nQ3
Q0 - Q3
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
KLCKLCn3Qurht0Q3Qnurht0Qn
01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
.sleveldedneelgnistpeccaottupni
Enabled
FIGURE 1 - CLK_EN TIMING DIAGRAM
edoMtuptuOottupnIytiraloP
laitnereffidehtgniriwsessucsidhcihw,21erugiF,01egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
3
Page 4
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
ICS8533-11
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
Outputs, V
I
O
Package Thermal Impedance, θ
Storage Temperature, T
CCx
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Characteristics
extended periods may affect product reliability .
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
= 3.3V±5%, TA = 0°C TO 70°C
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
I
EE
egatloVylppuSrewoP531.33.3564.3V
tnerruCylppuSrewoP 05Am
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
V
LI
I
HI
I
LI
egatloVhgiHtupnI
egatloVwoLtupnI
tnerruChgiHtupnI
tnerruCwoLtupnI
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
I
LI
V
PP
V
RMC
2,1ETON
tnerruChgiHtupnI
tnerruCwoLtupnI
,NE_KLC
LES_KLC
,NE_KLC
LES_KLC
NE_KLCV
LES_KLCV
NE_KLCV
LES_KLCV
NI
NI
= 3.3V±5%, TA = 0°C TO 70°C
CC
KLCnV
KLCV
KLCnV
KLCV
egatloVtupnIkaeP-ot-kaeP 51.03.1V
;egatloVtupnIedoMnommoC
VsadenifedsiegatlovedomnommoC:2ETON
.
= 3.3V±5%, TA = 0°C TO 70°C
CC
V=
NI
CC
V=
NI
CC
V,V0=
V,V0=
V=
CC
NI
V=
CC
NI
CC
CC
V564.3=5Aµ
V564.3=051Aµ
CC
CC
V564.3=051-Aµ
V564.3=5-Aµ
V564.3=5Aµ
V564.3=051Aµ
V,V564.3=
V0=051-Aµ
NI
V,V564.3=
V0=5-Aµ
NI
2567.3V
3.0-8.0V
V
5.0+V
EE
VsiKLCndnaKLCrofegatlovtupnimumixamehtsnoitacilppadedneelgnisroF:1ETON
CC
.V3.0+
58.0-V
CC
REV. D JULY 16, 2001
4
Page 5
Integrated
Circuit
Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V
= 3.3V±5%, TA = 0°C TO 70°C
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
V
LO
V
GNIWS
1ETON;egatloVhgiHtuptuOV
1ETON;egatloVwoLtuptuOV
-4.1V
CC
0.2-V
CC
gniwSegatloVtuptuOkaeP-ot-kaeP6.058.0V
05htiwdetanimretstuptuO:1ETON Ω Vot
.V2-
CC
TABLE 5. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ecnareloTycneuqerF 05-05mpp
ytilibatSycneuqerF 001-001mpp
leveLevirD 1.0Wm
)RSE(ecnatsiseRseireStnelaviuqE 0508
ecnaticapaCtnuhS 7Fp
ecnatcudnIniPseireS 37Hn
egnaRerutarepmeTgnitarepO 007C°
gnigAC°52@raeyreP5-5mpp
egnaRycneuqerF 4152zHM
0.1-V
CC
7.1-V
CC
Ω
TABLE 6. AC CHARACTERISTICS, V
= 3.3V±5%, TA = 0°C TO 70°C
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
t
DP
t
)o(ks5,2ETON;wekStuptuO 03sp
t
)pp(ks5,3ETON;wekStraP-ot-traP 051sp
t
R
t
F
emiTesiRtuptuOzHM05@%08ot%02003007sp
emiTllaFtuptuOzzHM05@%08ot%02003007sp
ycneuqerFtupnImumixaM 056zHM
1ETON;yaleDnoitagaporP IJ zHM0560.10.2sn
cdo4ETON;elcyCytuDtuptuO740535%
LOTcsoecnarelloTrotallicsOlatsyrC DBTmpp
.esiwrehtodetonsselnuzHM005taderusaemsretemarapllA
.rettijddatonseodtrapehT.tuptuoehtnorettijehtlauqelliwtupniehtnorettijelcyc-ot-elcycehT
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.etoNnoitacilppAotrefer,tupniLATXroF.KLCgnisuderusaeM:4ETON
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:5ETON
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
5
Page 6
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMA TION
V
CC
LVPECL
VCC = 2V
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
SCOPE
Qx
nQx
V
-1.3V ± 0.135V
EE =
V
CLK
nCLK
V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
CC
VPP
EE
Cross Points
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
V
CMR
REV. D JULY 16, 2001
6
Page 7
Integrated
Circuit
Systems, Inc.
Qx
nQx
Qy
nQy
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
tsk(o)
FIGURE 4 - OUTPUT SKEW
Clock Inputs
and Outputs
CLK
nCLK
Q0 - Q3
nQ0 - nQ3
80%
20%
t
R
t
F
FIGURE 5 - INPUT AND OUTPUT RISING/FALL TIME
t
PD
FIGURE 6 - PROPAGATION DELAY
80%
20%
V
SWING
CLK, Q0 - Q3
nCLK, nQ0 - nQ3
Pulse Width
t
PERIOD
t
odc =
FIGURE 7 - odc & t
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
PW
t
PERIOD
PERIOD
7
Page 8
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
ICS8533-11
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION IINFORMATION
CRYSTAL OSCILLATOR CIRCUIT FREQUENCY FINE TUNING
A crystal can be characterized for either series or parallel mode operation. The ICS8533-1 1 and ICS8535-1 1 fanout buf fers have
built-in crystal oscillator circuits that can accept either a series or parallel crystal without additional components. The frequency
accuracy provided by this configuration is sufficient for most computer applications.
For applications requiring highly accurate clock frequencies, the output frequency can be fine tuned by inserting a small series
capacitor C1 at the XT AL1 input (Pin 6 for ICS8533-11) as shown in
parallel or series crystal. The C1 value depends on the crystal type, frequency and the board layout. The parallel crystal fine
tuning results in smaller ppm and better performance. It is difficult to provide the precise value of C1. This section provides
recommended series capacitor C1 values to start with. This example uses 18pF parallel crystals.
Figure 8.
This fine tuning approach can be applied in either
Figure 9
about 33pF .
Figure 10
figure, a 24pF, 33pF and 43pF series capacitor is used to achieve the lowest ppm error for 19.44MHz, 16.666MHz and 15MHz
respectively.
Figure 11
shows the suggested series capacitor value for a parallel crystal. For a 16.666 MHz crystal, the recommended C1 value is
shows frequency accuracy versus series capacitance for 19.44MHz, 16.666MHz and 15MHz crystals. As seen from this
shows the experiment results of crystal oscillator frequency drift due to temperature variation.
U1
XTAL2
X1
C1
XTAL1
REV. D JULY 16, 2001
FIGURE 8 - CRYSTAL INTERFACE WITH SERIES CAPACITOR C1
8
.
Page 9
Integrated
)
y
y
)
Circuit
Systems, Inc.
60
50
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
14.318
40
30
20
Series Capacitor, C1 (pF
10
0
14 15 16 17 18 19 20 21 22 23 24 25
15.000
16.666
Crystal Frequency (MHz)
19.440
20.000
FIGURE 9 - SUGGESTED SERIES CAPACITOR C1 FOR PARALLEL CRYSTAL
100
80
60
(ppm
40
20
0
Accurac
0 102030405060
-20
-40
-60
Frequenc
-80
-100
Series Capacitor, C1 (pF)
24.000
19.44MHz
16.666MHz
15.00MHz
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
FIGURE 10 - FREQUENCY ACCURACY FOR PARALLEL CRYSTAL USING SERIES CAPACITOR C1
9
Page 10
Integrated
y
)
Circuit
Systems, Inc.
60
40
20
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
0
Drifted (ppm
0 1020304050607080
-20
Frequec
-40
-60
Temperature (deg. C)
19.44MHz
16.666MHz
FIGURE 11 - CRYSTAL OSCILLATOR CRCUIT FREQUENCY DRIFTED DUE TO TEMPERATURE VARIATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 12
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
= 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.
CC
R1
1K
V_REF
R2
1K
10
VCC
+
-
CLK_IN
C1
0.1uF
REV. D JULY 16, 2001
FIGURE 12: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Page 11
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
ICS8533-11
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8533-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8533-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
= 3.3V + 5% = 3.465V , which gives worst case results.
CC
• Power (core)
• Power (outputs)
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
T otal Power
MAX
= V
MAX
_MAX
* I
CC_MAX
= 30.2mW/Loaded Output pair
= 3.465V * 50mA = 173.3mW
EE_MAX
(3.465V , with all outputs switching) = 173.3mW + 120.8mW = 294.1mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature
θ
= junction-to-ambient thermal resistance
JA
Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T
= Ambient T emperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per T able 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
* Pd_total + T
JA
A
must be used . Assuming a
JA
T able 7. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
q
by V elocity (Linear Feet per Minute)
JA
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
11
Page 12
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
ICS8533-11
L VPECL output driver circuit and termination are shown in
VCC
Figure 8.
Q1
V
OUT
RL
50
V
- 2V
CC
FIGURE 13 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCC- 2V .
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
Pd_H = [(V
Pd_L = [(V
• For logic high, V
Using V
• For logic low, V
Using V
OH_MAX
OL_MAX
– (V
– (V
CC_MAX
CC_MAX
- 2V))/RL] * (V
CC_MAX
- 2V))/RL] * (V
CC_MAX
= V
OUT
OH_MAX
= 3.465, this results in V
= V
OUT
OL_MAX
= 3.465, this results in V
= V
= V
CC_MAX
CC_MAX
CC_MAX
CC_MAX
- V
OH_MAX
- V
OL_MAX
– 1.0V
OH_MAX
– 1.7V
OL_MAX
)
)
= 2.465V
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW
T otal Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
REV. D JULY 16, 2001
12
Page 13
Integrated
Circuit
Systems, Inc.
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 8. θ
TRANSISTOR COUNT
The transistor count for ICS8533-11 is: 428
VS
. AIR FLOW TABLE
JA
q
JA
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
by V elocity (Linear Feet per Minute)
0 200 500
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
13
Page 14
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REV. D JULY 16, 2001
TABLE 9. PACKAGE DIMENSIONS
LOBMYS
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α
aaa--01.0
Reference Document: JEDEC Publication 95, MS-153
14
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Page 15
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
11-GA3358SCI11-GA3358SCIPOSSTdael02ebutrep27C°07otC°0
T11-GA3358SCI11-GA3358SCIleeRdnaepaTnoPOSSTdael020052C°07otC°0
ICS8533-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLA TOR/
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
8533AG-11 www.icst.com/products/hiperclocks.html REV. D JULY 16, 2001
15
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