Page 1
Integrated
Circuit
Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
,&6
HiPerClockS™
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8532-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
The ICS8532-01 is a low skew, 1-to-17, Differential-to-3.3V LVPECL Fanout Buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8532-01 has two selectable clock inputs.
FEATURES
• 17 differential 3.3V L VPECL outputs
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: L VDS, LVPECL, L VHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 500MHz
• Translates any single-ended input signal (L VCMOS, L VTTL,
GTL) to 3.3V L VPECL levels with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2.5ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
nQ1
nQ0
Q1
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
D
Q
LE
0
1
Q0 - Q16
nQ0 - nQ16
VCCO
V
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
CLK_EN
V
CCO
Q0
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
nc
3
nc
4
CC
5
6
7
8
9
10
EE
11
12
nc
13
14 15 16 17 18 19 20 21 22 23 24 25 26
nQ16
ICS8532-01
Q15
nQ15
Q16
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
nQ2
Q3
Q2
nQ13
Q14
nQ14
T op View
nQ3
Q13
Q4
nQ12
nQ4
Q12
Q5
nQ11
nQ5
Q11
VCCO
VCCO
39
38
37
36
35
34
33
32
31
30
29
28
27
VCCO
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
nc
Vcco
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
1
Page 2
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,62,31,1
V
04,93,72
4V
82,21,3,2cndesunU.tcennocoN
5KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
6KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
7LES_KLCtupnInwodlluP
8KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
9KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
01V
11NE_KLCtupnIpulluP
51,4161Q,61QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
71,6151Q,51QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
91,8141Q,41QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
12,0231Q,31QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
32,2221Q,21QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
52,4211Q,11QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
03,9201Q,01QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
23,139Q,9QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
43,338Q,8QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
63,537Q,7QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
83,736Q,6QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
24,145Q,5QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
44,344Q,4QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
64,543Q3QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
84,742Q,2QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
05,941Q,1QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
25,150Q,0QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
:ETON
pulluP
OCC
CC
EE
dna
nwodlluP
rewoP.V3.3ottcennoC.snipylppustuptuO
rewoP.V3.3ottcennoC.nipylppusevitisoP
rewoP.dnuorgottcennoC.nipylppusevitageN
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleskcolC
.stupniKLCn,KLCstceles,WOLnehW
.slevelecafretniLTTVL/SOMCVL
kcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
.hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniLTTVL/SOMCVL
.seulavlacipytrofscitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
,KLC
KLCn
C
NI
R
PULLUP
R
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
NWODLLUP
ecnaticapaCtupnI
,KLCP
KLCPn
,NE_KLC
LES_KLC
rotsiseRpulluPtupnI 15KΩ
rotsiseRnwodlluPtupnI 15KΩ
2
4Fp
4Fp
4Fp
Page 3
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS61Qurht0Q61Qnurht0Qn
00 KLCn,KLCWOL;delbasiDHGIH;delbasiD
01 KLCPn,KLCPWOL;delbasiDHGIH;delbasiD
10 KLCn,KLCdelbanEdelbanE
11 KLCPn,KLCPdelbanEdelbanE
.
1erugiFninwohssa
.
B3elbaTni
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ16
Q0 - Q16
Disabled
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
KLCProKLCKLCPnroKLCn61Qurht0Q61Qnurht0Qn
01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIH
11ETON;desaiBHGIHWOL
1ETON;desaiB0HGIHWOL
1ETON;desaiB1WOLHGIH
.sleveldedneelgnistpeccaottupni
FIGURE 1: CLK_EN TIMING DIAGRAM
Enabled
otdednEelgniS
laitnereffiD
otdednEelgniS
laitnereffiD
otdednEelgniS
laitnereffiD
otdednEelgniS
laitnereffiD
edoMtuptuOottupnIytiraloP
gnitrevnInoN
gnitrevnInoN
gnitrevnI
gnitrevnI
laitnereffidehtgniriwsessucsidhcihw,9erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
3
Page 4
Integrated
Circuit
Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage Temperature, T
CCx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
4.6V
-0.5V to VCC + 0.5V
-0.5V to V
CCO
+ 0.5V
40°C/W
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
V
OCC
I
EE
egatloVylppuSevitisoP531.33.3564.3V
egatloVylppuStuptuO531.33.3564.3V
tnerruCylppuSrewoP 221051Am
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
V
LI
I
HI
I
LI
tnerruChgiHtupnI
tnerruCwoLtupnI
tnerruChgiHtupnI
tnerruCwoLtupnI
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
I
LI
V
PP
V
RMC
2,1ETON
KLCV
tnerruChgiHtupnI
KLCV
tnerruCwoLtupnI
,NE_KLC
LES_KLC
,NE_KLC
LES_KLC
LES_KLCV
NE_KLCV
LES_KLCV
NE_KLCV
= V
CC
NI
KLCnV
KLCnV
NI
NI
NI
egatloVtupnIkaeP-ot-kaeP 51.03.1V
;egatloVtupnIedoMnommoC
VsadenifedsiegatlovedomnommoC:1ETON
.
HI
= 3.3V±5%, TA = 0°C TO 70°C
CCO
= V
CC
NI
NI
NI
NI
CCO
V=
V=
= 3.3V±5%, TA = 0°C TO 70°C
CCO
V=
CC
V=
CC
V,V0=
V,V0=
V564.3=051Aµ
V564.3=5Aµ
CC
CC
V564.3=5-Aµ
V564.3=051-Aµ
= 3.3V±5%, TA = 0°C TO 70°C
CC
CC
V,V0=
V,V0=
V564.3=051Aµ
V564.3=5Aµ
CC
CC
V564.3=5-Aµ
V564.3=051-Aµ
2567.3V
3.0-8.0V
V
5.0+V
EE
VsiKLCndnaKLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
.V3.0+
58.0-V
CC
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
4
Page 5
Integrated
Circuit
Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V
CC
= V
= 3.3V±5%, TA = 0°C TO 70°C
CCO
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
I
LI
V
PP
V
RMC
V
HO
V
LO
V
GNIWS
tnerruChgiHtupnI
tnerruCwoLtupnI
TABLE 5. AC CHARACTERISTICS, V
KLCPV
KLCPnV
KLCPV
KLCPnV
V=
CC
NI
V=
CC
NI
CC
CC
egatloVtupnIkaeP-ot-kaeP 3.01V
2,1ETON;egatloVtupnIedoMnommoCV
3ETON;egatloVhgiHtuptuOV
3ETON;egatloVwoLtuptuOV
gniwSegatloVkaeP-ot-kaeP 6.058.0V
.
VsadenifedsiegatlovedomnommoC:1ETON
HI
.V2-
CC
05htiwdetanimretstuptuO:3ETON Ω Vot
= V
= 3.3V±5%, TA = 0°C TO 70°C
CCO
V564.3=051Aµ
V564.3=5Aµ
V,V564.3=
V0=5-Aµ
NI
V,V564.3=
V0=051-Aµ
NI
5.1+V
EE
4.1-V
OCC
0.2-V
OCC
VsiKLCPn,KLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
CC
.V3.0+
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
t
DP
t
)o(ks4,2ETON;wekStuptuO 05sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 052sp
t
R
t
F
emiTesiRtuptuOzHM05@%08ot%02003007sp
emiTllaFtuptuOzHM05@%08ot%02003007sp
cdoelcyCytuDtuptuO
ycneuqerFtuptuOmumixaM 005zHM
1ETON;yaleDnoitagaporP IJ zHM0053.15.2sn
0 ≤ ƒ≤ zHM662840525%
662 ≤ ƒ≤ zHM005740535%
.esiwrehtodetonsselnuzHM005taderusaemsretemarapllA
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
CC
0.1-V
OCC
7.1-V
OCC
V
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
5
Page 6
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
V
CC
LVPECL
VCC = 2.0V
V
CCO
V
CCO
= 2.0V
VEE = -1.3V ± 0.135V
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
SCOPE
Qx
nQx
CLK, PCLK
nCLK, nPCLK
Qx
nQx
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
V
CC
V
VPP
V
EE
Cross Points
CMR
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
6
Page 7
Integrated
Circuit
Systems, Inc.
Qx
PART 1
nQx
Qy
PART 2
nQy
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
tsk(pp)
FIGURE 5 - PART-TO-PART SKEW
Clock Inputs
and Outputs
CLK, PCLK
nCLK, nPCLK
Q0 - Q16
nQ0 - nQ16
80%
20%
t
R
t
F
FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME
t
PD
FIGURE 7 - PROPAGATION DELAY
80%
20%
V
SWING
CLK, PCLK, Qx
nCLK, nPCLK, nQx
Pulse Width
t
PERIOD
t
odc =
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
PW
t
PERIOD
FIGURE 8 - odc & t
7
PERIOD
Page 8
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
ICS8532-01
LOW SKEW, 1-TO-17
Figure 9
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.
shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
CLK_IN
C1
0.1uF
FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R1
1K
V_REF
R2
1K
VCC
+
-
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
8
Page 9
Integrated
Circuit
Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8531-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
= 3.3V + 5% = 3.465V , which gives worst case results.
CC
• Power (core)
• Power (outputs)
If all outputs are loaded, the total power is 17 * 30.2mW = 513.4mW
T otal Power
MAX
= V
MAX
_MAX
* I
CC_MAX
= 30.2mW/Loaded Output pair
= 3.465V * 150mA = 519.8mW
EE_MAX
(3.465V , with all outputs switching) = 519.8mW + 513.4mW = 1033.2mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature
θ
= junction-to-ambient thermal resistance
JA
Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T
= Ambient T emperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 0°C/W per T able 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.1033W * 0°C/W = 0°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
* Pd_total + T
JA
A
TM
devices is 125°C.
must be used . Assuming a
JA
Table 6. Thermal Resistance qJA for 52-pin LQFP Forced Convection
q
by V elocity (Linear Feet per Minute)
JA
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 0°C/W 0°C/W 0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 0°C/W 0°C/W 0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
9
Page 10
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
ICS8532-01
LOW SKEW, 1-TO-17
LVPECL output driver circuit and termination are shown in
Figure 10.
V
CCO
Q1
RL
50
V
CCO
V
OUT
- 2V
Figure 10 - LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCC- 2V .
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
Pd_H = [(V
Pd_L = [(V
• For logic high, V
Using V
• For logic low, V
Using V
OH_MAX
OL_MAX
– (V
– (V
CC_MAX
CC_MAX
- 2V))/RL] * (V
CC_MAX
- 2V))/RL] * (V
CC_MAX
= V
OUT
OH_MAX
= 3.465, this results in V
= V
OUT
OL_MAX
= 3.465, this results in V
= V
= V
CC_MAX
CC_MAX
CC_MAX
CC_MAX
- V
OH_MAX
- V
OL_MAX
– 1.0V
OH_MAX
– 1.7V
OL_MAX
)
)
= 2.465V
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW
T otal Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
10
Page 11
Integrated
Circuit
Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θ
TRANSISTOR COUNT
The transistor count for ICS8532-01 is: 1398
VS
. AIR FLOW TABLE
JA
q
by Velocity (Linear Feet per Minute)
JA
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 0°C/W 0°C/W 0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 0°C/W 0°C/W 0°C/W
NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designs.
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
11
Page 12
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 8. PACKAGE DIMENSIONS
LOBMYS
N
A
1A
2A
b
c
D
1D
2D
E
1E
2E
e
L
q
ccc
MUMINIMLANIMONMUMIXAM
----06.1
50.0--51.0
53.104.154.1
22.023.083.0
90.0--02.0
54.0--57.0
°
0
----01.0
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
CCB
25
CISAB00.21
CISAB00.01
.feR08.7
CISAB00.21
CISAB00.01
.feR08.7
CISAB56.0
--
7
°
Reference Document: JEDEC Publication 95, MS-026
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
12
Page 13
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
10-YA2358SCI10-YA2358SCIPFQLdaeL25yartrep061C°07otC°0
T10-YA2358SCI10-YA2358SCIleeRdnaepaTnoPFQLdaeL25005C°07otC°0
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
13
Loading...