Page 1
Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
,&6
HiPerClockS™
inputs. The CLK, nCLK pair can accept most standard
differential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output skew and part-to-part skew characteristics make the ICS8531-01 ideal for high performance workstation and server applications.
The ICS8531-01 is a low skew , high performance
1-to-9 Differential-to-3.3V L VPECL Fanout Buffer
and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8531-01 has two selectable clock
FEATURES
• 9 differential 3.3V L VPECL outputs
• Selectable CLK, nCLK or L VPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: L VDS, L VPECL, L VHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 500MHz
• Translates any single ended input signal (L VCMOS, L VTTL,
GTL) to 3.3V L VPECL levels with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
V
CCO
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
VCC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
EE
V
CLK_EN
7mm x 7mm x 1.4mm package body
Q0
32 31 30 29 28 27 26 25
1
2
3
4
ICS8531-01
5
6
7
8
9 10 11 12 13 14 15 16
nQ8
Vcco
32-Lead LQFP
nQ1
nQ0
Q1
Q7
nQ7
Q8
Y package
Top View
Q2
nQ6
nQ2
Q6
VCCO
Vcco
24
23
22
21
20
19
18
17
CCO
V
Q3
nQ3
Q4
nQ4
Q5
nQ5
CCO
V
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
1
Page 2
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1V
2KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
3KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
4LES_KLCtupnInwodlluP
5KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
6KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
7V
8NE_KLCtupnIpulluP
,71,61,9
23,52,42
11,018Q,8QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
31,217Q,7QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
51,416Q,6QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
91,815Q,5QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
12,024Q,4QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
32,223Q3QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
72,622Q,2QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
92,821Q,1QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
13,030Q,0QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
:ETON
pulluP
CC
EE
V
OCC
dna
nwodlluP
rewoP.V3.3ottcennoC.nipylppusevitisoP
rewoP.dnuorgottcennoC.nipylppusevitageN
rewoP.V3.3ottcennoC.snipylppustuptuO
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleSkcolC
stceles,WOLnehW.KLCn,KLC
.slevelecafretniSOMCVL/LTTVL
wollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
stuptuoQn,woldecroferastuptuoQ,WOLnehW.tupnikcolc
.slevelecafretniSOMCVL/LTTVL.hgihdecrofera
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
,KLCn,KLC
C
NI
R
PULLUP
R
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
NWODLLUP
ecnaticapaCtupnI
rotsiseRpulluPtupnI 15KΩ
rotsiseRnwodlluPtupnI 15KΩ
KCLPn,KLCP
LES_KLC,NE_KLC4Fp
2
4Fp
Page 3
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCdecruoSdetceleS8Qurht0Q8Qnurht0Qn
00 KLCn,KLCWOL;delbasiDHGIH;delbasiD
01 KLCPn,KLCPWOL;delbasiDHGIH;delbasiD
10 KLCn,KLCdelbanEdelbanE
11 KLCPn,KLCPdelbanEdelbanE
.1erugiFninwohssa
.B3elbaTni
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ8
Q0 - Q8
Disabled
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
stupnIstuptuO
KLCProKLCKLCPnroKLCn8Qurht0Q8Qnurht0Qn
01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHlaitnereffiDotdednEelgniSgnitrevnI
.sleveldedneelgnistpeccaottupni
Enabled
FIGURE 1: CLK_EN TIMING DIAGRAM
edoMtuptuOottupnIytiraloP
laitnereffidehtgniriwsessucsidhcihw,9erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
3
Page 4
Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage T emperature, T
CCx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
ods may affect product reliability .
4.6V
-0.5V to VCC + 0.5V
-0.5V to V
CCO
+ 0.5V
47.9°C/W
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for extended peri-
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
V
OCC
I
EE
TABLE 4B. LVCMOS DC CHARACTERISTICS, V
egatloVylppuSevitisoP 531.33.3564.3V
egatloVylppuStuptuO 531.33.3564.3V
tnerruCylppuSrewoP 0507Am
= V
CC
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
V
LI
I
HI
I
LI
LES_KLC,NE_KLC2567.3V
LES_KLC,NE_KLC3.0-8.0V
tnerruChgiHtupnI
tnerruCwoLtupnI
NE_KLCV
LES_KLCV
NE_KLCV
LES_KLCV
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
KLCV
I
HI
I
LI
V
PP
V
RMC
2,1ETON
tnerruChgiHtupnI
tnerruCwoLtupnI
KLCnV
KLCV
KLCnV
egatloVtupnIkaeP-ot-kaeP51.03.1V
;egatloVtupnIedoMnommoC
= V
= 3.3V±5%, TA = 0°C TO 70°C
CCO
= 3.3V±5%, TA = 0°C TO 70°C
V=
CC
NI
V=
CC
NI
V,V0=
NI
NI
CCO
V=
V=
V,V0=
V,V0=
VsadenifedsiegatlovtupniedomnommoC:2ETON
.
CC
V,V0=
CC
= 3.3V±5%, TA = 0°C TO 70°C
NI
NI
V564.3=051Aµ
V564.3=5Aµ
CC
CC
V564.3=5-Aµ
V564.3=051-Aµ
CC
NI
NI
CC
CCO
= V
CC
CC
V564.3=5Aµ
V564.3=051Aµ
V564.3=051-Aµ
V564.3=5-Aµ
V
5.0+V
EE
VsiKLCndnaKLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON
CC
.V3.0+
58.0-V
CC
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
4
Page 5
Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V
CC
= V
= 3.3V±5%, TA = 0°C TO 70°C
CCO
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
I
LI
V
PP
V
RMC
V
HO
V
LO
V
GNIWS
2,1ETON
tnerruChgiHtupnI
tnerruCwoLtupnI
TABLE 5. AC CHARACTERISTICS, V
KLCPV
KLCPnV
KLCPV
KLCPnV
egatloVtupnIkaeP-ot-kaeP 3.01V
;egatloVtupnIedoMnommoC
3ETON;egatloVhgiHtuptuOV
3ETON;egatloVwoLtuptuOV
gniwSegatloVtuptuOkaeP-ot-kaeP 6.058.0V
VsadenifedsiegatlovtupniedomnommoC:1ETON
.V2-
CC
05htiwdetanimretstuptuO:3ETON Ω Vot
= V
= 3.3V±5%, TA = 0°C TO 70°C
CCO
V=
CC
NI
V=
CC
NI
V,V0=
NI
V,V0=
NI
.
HI
V564.3=051Aµ
V564.3=5Aµ
CC
CC
V564.3=5-Aµ
V564.3=051-Aµ
V
5.1+V
EE
4.1-V
OCC
0.2-V
OCC
VsiKLCPndnaKLCProfegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
CC
.V3.0+
CC
0.1-V
OCC
7.1-V
OCC
V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
t
DP
t
)o(ks4,2ETON;wekStuptuO 05sp
t
)pp(ks4,3ETON;wekStraP-ot-traP 052sp
t
R
t
F
emiTesiRtuptuOzHM05@%08ot%02003007sp
emiTllaFtuptuOzHM05@%08ot%02003007sp
ycneuqerFtuptuOmumixaM 005zHM
1ETON;yaleDnoitagaporP IJ zHM0521 2sn
cdoelcyCytuDtuptuO 840525%
.esiwrehtodetonsselnuzHM052taderusaemsretemarapllA
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiwdna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
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Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
V
CC
LVPECL
VCC = 2.0V
V
CCO
V
CCO
= 2.0V
VEE = -1.3V ± 0.135V
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
SCOPE
Qx
nQx
CLK, PCLK
nCLK, nPCLK
Qx
nQx
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
V
CC
V
VPP
V
EE
Cross Points
CMR
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qy
nQy
tsk(o)
FIGURE 4 - O UTPUT SKEW
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
6
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Integrated
Circuit
Systems, Inc.
PART 1
nQx
PART 2
nQy
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Qx
Qy
tsk(pp)
FIGURE 5 - P ART-TO-PART SKEW
Clock Inputs
and Outputs
CLK, PCLK
nCLK, nPCLK
Q0 - Q8
nQ0 - nQ8
80%
20%
t
R
t
F
FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME
t
PD
FIGURE 7 - PROPAGATION DELAY
80%
20%
V
SWING
CLK, PCLK, Qx
nCLK, nPCLK, nQx
Pulse Width
t
PERIOD
t
odc =
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
PW
t
PERIOD
FIGURE 8 - odc & t
7
PERIOD
Page 8
Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICA TION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 9
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
= 3.3V , V_REF should be 1.25V and R2/R1 = 0.609.
CC
CLK_IN
CLK_IN
C1
0.1uF
C1
0.1uF
R1
1K
R1
1K
V_REF
V_REF
R2
1K
R2
1K
VCC
VCC
+
+
-
-
FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
8
Page 9
Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8531-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
= 3.3V + 5% = 3.465V , which gives worst case results.
CC
• Power (core)
• Power (outputs)
If all outputs are loaded, the total power is 9 * 30.2mW = 271.8mW
T otal Power
MAX
= V
MAX
_MAX
* I
CC_MAX
= 30.2mW/Loaded Output pair
= 3.465V * 70mA = 242.6mW
EE_MAX
(3.465V , with all outputs switching) = 242.6mW + 271.8mW = 514.4mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
The equation for Tj is as follows: Tj = θ
Tj = Junction T emperature
θ
= junction-to-ambient thermal resistance
JA
Pd_total = T otal device power dissipation (example calculation is in section 1 above)
T
= Ambient T emperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per T able 6 below .
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.514W * 42.1°C/W = 91.6°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
* Pd_total + T
JA
A
TM
devices is 125°C.
must be used . Assuming a
JA
Table 6. Thermal Resistance qJA for 32-pin LQFP Forced Convection
q
by Velocity (Linear Feet per Minute)
JA
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
9
Page 10
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
ICS8531-01
LOW SKEW, 1-TO-9
LVPECL output driver circuit and termination are shown in
Figure 10.
V
CCO
Q1
RL
50
V
CCO
V
OUT
- 2V
FIGURE 10 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCC- 2V .
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low .
Pd_H = [(V
Pd_L = [(V
• For logic high, V
Using V
• For logic low, V
Using V
OH_MAX
OL_MAX
– (V
– (V
CC_MAX
CC_MAX
- 2V))/RL] * (V
CC_MAX
- 2V))/RL] * (V
CC_MAX
= V
OUT
OH_MAX
= 3.465, this results in V
= V
OUT
OL_MAX
= 3.465, this results in V
= V
= V
CC_MAX
CC_MAX
CC_MAX
CC_MAX
- V
OH_MAX
- V
OL_MAX
– 1.0V
OH_MAX
– 1.7V
OL_MAX
)
)
= 2.465V
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW
T otal Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
10
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Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θ
TRANSISTOR COUNT
The transistor count for ICS8531-01 is: 632
VS
. AIR FLOW TABLE
JA
qJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designs.
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
11
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Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 8. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ
LOBMYS
N
A
1A
2A
b
c
D
1D
2D
E
1E
2E
e
L
q
ccc
Reference Document: JEDEC Publication 95, MS-026
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
MUMINIMLANIMONMUMIXAM
----06.1
50.0--51.0
53.104.154.1
03.073.054.0
90.0--02.0
54.006.057.0
°
0
----01.0
SRETEMILLIMNISNOISNEMIDLLA
ABB
23
CISAB00.9
CISAB00.7
.feR06.5
CISAB00.9
CISAB00.7
.feR06.5
CISAB08.0
--
7
°
12
Page 13
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
10-YA1358SCI10-YA1358SCIPFQLdaeL23yartrep052C°07otC°0
T10-YA1358SCI10-YA1358SCIleeRdnaepaTnoPFQLdaeL230001C°07otC°0
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8531AY-01 www.icst.com/products/hiperclocks.html REV. B AUGUST 9, 2001
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